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From: Alexandre Belloni <alexandre.belloni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
To: Cyrille Pitchen
	<cyrille.pitchen-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org>
Cc: nicolas.ferre-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org,
	gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r@public.gmane.org,
	wenyou.yang-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org,
	ludovic.desroches-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org,
	leilei.zhao-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org,
	josh.wu-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org,
	linux-serial-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
	devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org,
	ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org,
	mark.rutland-5wv7dgnIgG8@public.gmane.org,
	pawel.moll-5wv7dgnIgG8@public.gmane.org,
	robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org
Subject: Re: [PATCH linux-next v2 3/4] tty/serial: at91: add support to FIFOs
Date: Thu, 18 Jun 2015 18:36:36 +0200	[thread overview]
Message-ID: <20150618163636.GP27492@piout.net> (raw)
In-Reply-To: <e9b7445f103969a286d586054d79461a6efacd65.1434038494.git.cyrille.pitchen-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org>

Hi,

On 11/06/2015 at 18:20:16 +0200, Cyrille Pitchen wrote :
> 
> Signed-off-by: Cyrille Pitchen <cyrille.pitchen-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org>

Seems good to me, a few comments:

> +	if (port->fifo_size < 8 || port->fifo_size > 32) {

I'm not sure why you limit the size to 32. At some point, a new SoC may
be release with a bigger FIFO then we'll have to change the code instead
of just putting the appropriate value in the device tree.

> +		port->fifo_size = 0;
> +		dev_err(&pdev->dev, "Invalid FIFO size\n");
> +		return;
> +	}
> +
> +	/*
> +	 * 0 <= rts_low <= rts_high <= fifo_size
> +	 * Once their CTS line asserted by the remote peer, some x86 UARTs tend
> +	 * to flush their internal TX FIFO, commonly up to 8 data, before
> +	 * actually stopping to send new data. So we try to set the RTS High
> +	 * Threshold to a raisonable high value respecting this 8 data empirical
              reasonably --^

-- 
Alexandre Belloni, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
--
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WARNING: multiple messages have this Message-ID (diff)
From: alexandre.belloni@free-electrons.com (Alexandre Belloni)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH linux-next v2 3/4] tty/serial: at91: add support to FIFOs
Date: Thu, 18 Jun 2015 18:36:36 +0200	[thread overview]
Message-ID: <20150618163636.GP27492@piout.net> (raw)
In-Reply-To: <e9b7445f103969a286d586054d79461a6efacd65.1434038494.git.cyrille.pitchen@atmel.com>

Hi,

On 11/06/2015 at 18:20:16 +0200, Cyrille Pitchen wrote :
> 
> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>

Seems good to me, a few comments:

> +	if (port->fifo_size < 8 || port->fifo_size > 32) {

I'm not sure why you limit the size to 32. At some point, a new SoC may
be release with a bigger FIFO then we'll have to change the code instead
of just putting the appropriate value in the device tree.

> +		port->fifo_size = 0;
> +		dev_err(&pdev->dev, "Invalid FIFO size\n");
> +		return;
> +	}
> +
> +	/*
> +	 * 0 <= rts_low <= rts_high <= fifo_size
> +	 * Once their CTS line asserted by the remote peer, some x86 UARTs tend
> +	 * to flush their internal TX FIFO, commonly up to 8 data, before
> +	 * actually stopping to send new data. So we try to set the RTS High
> +	 * Threshold to a raisonable high value respecting this 8 data empirical
              reasonably --^

-- 
Alexandre Belloni, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

WARNING: multiple messages have this Message-ID (diff)
From: Alexandre Belloni <alexandre.belloni@free-electrons.com>
To: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Cc: nicolas.ferre@atmel.com, gregkh@linuxfoundation.org,
	wenyou.yang@atmel.com, ludovic.desroches@atmel.com,
	leilei.zhao@atmel.com, josh.wu@atmel.com,
	linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
	galak@codeaurora.org, ijc+devicetree@hellion.org.uk,
	mark.rutland@arm.com, pawel.moll@arm.com, robh+dt@kernel.org
Subject: Re: [PATCH linux-next v2 3/4] tty/serial: at91: add support to FIFOs
Date: Thu, 18 Jun 2015 18:36:36 +0200	[thread overview]
Message-ID: <20150618163636.GP27492@piout.net> (raw)
In-Reply-To: <e9b7445f103969a286d586054d79461a6efacd65.1434038494.git.cyrille.pitchen@atmel.com>

Hi,

On 11/06/2015 at 18:20:16 +0200, Cyrille Pitchen wrote :
> 
> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>

Seems good to me, a few comments:

> +	if (port->fifo_size < 8 || port->fifo_size > 32) {

I'm not sure why you limit the size to 32. At some point, a new SoC may
be release with a bigger FIFO then we'll have to change the code instead
of just putting the appropriate value in the device tree.

> +		port->fifo_size = 0;
> +		dev_err(&pdev->dev, "Invalid FIFO size\n");
> +		return;
> +	}
> +
> +	/*
> +	 * 0 <= rts_low <= rts_high <= fifo_size
> +	 * Once their CTS line asserted by the remote peer, some x86 UARTs tend
> +	 * to flush their internal TX FIFO, commonly up to 8 data, before
> +	 * actually stopping to send new data. So we try to set the RTS High
> +	 * Threshold to a raisonable high value respecting this 8 data empirical
              reasonably --^

-- 
Alexandre Belloni, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

  parent reply	other threads:[~2015-06-18 16:36 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-06-11 16:20 [PATCH linux-next v2 0/4] tty/serial: at91: add support to FIFOs Cyrille Pitchen
2015-06-11 16:20 ` Cyrille Pitchen
2015-06-11 16:20 ` Cyrille Pitchen
     [not found] ` <cover.1434038494.git.cyrille.pitchen-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org>
2015-06-11 16:20   ` [PATCH linux-next v2 1/4] ARM: at91/dt: add a new DT property to support FIFOs on Atmel USARTs Cyrille Pitchen
2015-06-11 16:20     ` Cyrille Pitchen
2015-06-11 16:20     ` Cyrille Pitchen
2015-06-18 16:39     ` Alexandre Belloni
2015-06-18 16:39       ` Alexandre Belloni
     [not found]     ` <16bdcf0c3f710ca46df86eeea82c9840454cb7aa.1434038494.git.cyrille.pitchen-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org>
2015-06-29 13:00       ` Nicolas Ferre
2015-06-29 13:00         ` Nicolas Ferre
2015-06-29 13:00         ` Nicolas Ferre
2015-06-11 16:20 ` [PATCH linux-next v2 2/4] tty/serial: at91: fix some macro definitions to fit coding style Cyrille Pitchen
2015-06-11 16:20   ` Cyrille Pitchen
2015-06-11 16:20   ` Cyrille Pitchen
     [not found]   ` <f22220ee42ecf9301def7e90154b74937ca9ffab.1434038494.git.cyrille.pitchen-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org>
2015-06-18 16:39     ` Alexandre Belloni
2015-06-18 16:39       ` Alexandre Belloni
2015-06-18 16:39       ` Alexandre Belloni
2015-06-29 13:00     ` Nicolas Ferre
2015-06-29 13:00       ` Nicolas Ferre
2015-06-29 13:00       ` Nicolas Ferre
2015-06-11 16:20 ` [PATCH linux-next v2 3/4] tty/serial: at91: add support to FIFOs Cyrille Pitchen
2015-06-11 16:20   ` Cyrille Pitchen
2015-06-11 16:20   ` Cyrille Pitchen
     [not found]   ` <e9b7445f103969a286d586054d79461a6efacd65.1434038494.git.cyrille.pitchen-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org>
2015-06-18 16:36     ` Alexandre Belloni [this message]
2015-06-18 16:36       ` Alexandre Belloni
2015-06-18 16:36       ` Alexandre Belloni
2015-06-29 13:11     ` Nicolas Ferre
2015-06-29 13:11       ` Nicolas Ferre
2015-06-29 13:11       ` Nicolas Ferre
2015-06-11 16:20 ` [PATCH linux-next v2 4/4] tty/serial: at91: use 32bit writes into TX FIFO when DMA is enabled Cyrille Pitchen
2015-06-11 16:20   ` Cyrille Pitchen
2015-06-11 16:20   ` Cyrille Pitchen
2015-06-29 13:28   ` Nicolas Ferre
2015-06-29 13:28     ` Nicolas Ferre
2015-06-29 13:28     ` Nicolas Ferre

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