From: vinod.koul@intel.com (Vinod Koul)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v7] dma: Add Xilinx AXI Direct Memory Access Engine driver support
Date: Sun, 28 Jun 2015 20:15:29 +0530 [thread overview]
Message-ID: <20150628144529.GZ19530@localhost> (raw)
In-Reply-To: <CAH=tA9F3=oqWi66EpkG-ecWHuVbOua+ceeiQD03WjiA=QdgA-g@mail.gmail.com>
On Sat, Jun 27, 2015 at 05:44:38PM +0300, Nicolae Rosia wrote:
> On Sat, Jun 27, 2015 at 5:40 PM, Vinod Koul <vinod.koul@intel.com> wrote:
> [...]
> >> Please let me know if you are not clear.
> > No sorry am not...
> >
> > I asked how the device address in configured. For both MM2S S2MM you are
> > using sg for memory address, where are you getting device adress, are you
> > assuming/hardcoding or getting somehow, if so how?
> As the name says, one end is memory (MM) and the other end is an AXI4
> Stream Bus (S) which has no concept of memory address.
> So yes, it is hardcoded at design time.
So where does the data go at the end of stream bus, who configures that?
Shouldnt all this be at least documented...
--
~Vinod
WARNING: multiple messages have this Message-ID (diff)
From: Vinod Koul <vinod.koul@intel.com>
To: Nicolae Rosia <nicolae.rosia@gmail.com>
Cc: Appana Durga Kedareswara Rao <appana.durga.rao@xilinx.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
Srikanth Thokala <sthokal@xilinx.com>,
Michal Simek <michals@xilinx.com>,
Soren Brinkmann <sorenb@xilinx.com>,
Anirudha Sarangi <anirudh@xilinx.com>,
"dmaengine@vger.kernel.org" <dmaengine@vger.kernel.org>,
Punnaiah Choudary Kalluri <punnaia@xilinx.com>,
"dan.j.williams@intel.com" <dan.j.williams@intel.com>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH v7] dma: Add Xilinx AXI Direct Memory Access Engine driver support
Date: Sun, 28 Jun 2015 20:15:29 +0530 [thread overview]
Message-ID: <20150628144529.GZ19530@localhost> (raw)
In-Reply-To: <CAH=tA9F3=oqWi66EpkG-ecWHuVbOua+ceeiQD03WjiA=QdgA-g@mail.gmail.com>
On Sat, Jun 27, 2015 at 05:44:38PM +0300, Nicolae Rosia wrote:
> On Sat, Jun 27, 2015 at 5:40 PM, Vinod Koul <vinod.koul@intel.com> wrote:
> [...]
> >> Please let me know if you are not clear.
> > No sorry am not...
> >
> > I asked how the device address in configured. For both MM2S S2MM you are
> > using sg for memory address, where are you getting device adress, are you
> > assuming/hardcoding or getting somehow, if so how?
> As the name says, one end is memory (MM) and the other end is an AXI4
> Stream Bus (S) which has no concept of memory address.
> So yes, it is hardcoded at design time.
So where does the data go at the end of stream bus, who configures that?
Shouldnt all this be at least documented...
--
~Vinod
next prev parent reply other threads:[~2015-06-28 14:45 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-06-09 6:35 [PATCH v7] dma: Add Xilinx AXI Direct Memory Access Engine driver support Kedareswara rao Appana
2015-06-09 6:35 ` Kedareswara rao Appana
2015-06-16 19:19 ` Nicolae Rosia
2015-06-16 19:19 ` Nicolae Rosia
2015-06-18 10:16 ` Appana Durga Kedareswara Rao
2015-06-18 10:16 ` Appana Durga Kedareswara Rao
2015-06-19 16:49 ` Jeremy Trimble
2015-06-19 16:49 ` Jeremy Trimble
2015-06-24 17:12 ` Appana Durga Kedareswara Rao
2015-06-24 17:12 ` Appana Durga Kedareswara Rao
2015-06-22 10:49 ` Vinod Koul
2015-06-22 10:49 ` Vinod Koul
2015-06-24 17:12 ` Appana Durga Kedareswara Rao
2015-06-24 17:12 ` Appana Durga Kedareswara Rao
2015-06-27 14:40 ` Vinod Koul
2015-06-27 14:40 ` Vinod Koul
2015-06-27 14:44 ` Nicolae Rosia
2015-06-27 14:44 ` Nicolae Rosia
2015-06-28 14:45 ` Vinod Koul [this message]
2015-06-28 14:45 ` Vinod Koul
2015-06-28 15:06 ` Nicolae Rosia
2015-06-28 15:06 ` Nicolae Rosia
2015-07-07 15:31 ` Appana Durga Kedareswara Rao
2015-07-07 15:31 ` Appana Durga Kedareswara Rao
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