From: Stephen Boyd <sboyd@codeaurora.org>
To: Georgi Djakov <georgi.djakov@linaro.org>
Cc: agross@codeaurora.org, mturquette@linaro.org,
linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-msm@vger.kernel.org
Subject: Re: [PATCH 1/5] clk: qcom: Add support for SR2 PLLs
Date: Mon, 6 Jul 2015 15:15:04 -0700 [thread overview]
Message-ID: <20150706221504.GB30412@codeaurora.org> (raw)
In-Reply-To: <1434098519-26406-2-git-send-email-georgi.djakov@linaro.org>
On 06/12, Georgi Djakov wrote:
> Add support for SR2 type pll operations. SR2 is optimized for Time Interval
> Error (TIE) or absolute jitter.
>
> Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
> ---
Applied to clk-next
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
next prev parent reply other threads:[~2015-07-06 22:15 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-06-12 8:41 [PATCH 0/5] Add support for A53 CPU clock Georgi Djakov
2015-06-12 8:41 ` [PATCH 1/5] clk: qcom: Add support for SR2 PLLs Georgi Djakov
2015-07-06 22:15 ` Stephen Boyd [this message]
2015-06-12 8:41 ` [PATCH 2/5] clk: Add safe switch hook Georgi Djakov
2015-06-12 8:41 ` [PATCH 3/5] clk: qcom: Add support for regmap mux-div clocks Georgi Djakov
2015-06-12 8:41 ` [PATCH 4/5] clk: qcom: Add A53 clock driver Georgi Djakov
2015-06-15 13:58 ` Paul Bolle
2015-06-15 15:36 ` Georgi Djakov
2015-06-16 7:14 ` Paul Bolle
2015-06-12 8:41 ` [PATCH 5/5] arm64: dts: qcom: msm8916: Add A53 DT node Georgi Djakov
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