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From: LABBE Corentin <clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
To: Herbert Xu <herbert-lOAM2aK0SrRLBo1qDEOMRrpzq4S04n8Q@public.gmane.org>
Cc: robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org,
	pawel.moll-5wv7dgnIgG8@public.gmane.org,
	mark.rutland-5wv7dgnIgG8@public.gmane.org,
	ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org,
	galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org,
	maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org,
	linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org,
	davem-fT/PcQaiUtIeIZ0/mPfg9Q@public.gmane.org,
	akpm-de/tnXTf+JLsfHDXvbKv3WD2FQJk+8+b@public.gmane.org,
	gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r@public.gmane.org,
	mchehab-JPH+aEBZ4P+UEJcrhfAQsw@public.gmane.org,
	arnd-r2nGTMty4D4@public.gmane.org,
	joe-6d6DIl74uiNBDgjK7y7TUQ@public.gmane.org,
	devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-doc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-crypto-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org
Subject: Re: Re: [PATCH v10 4/5] crypto: Add Allwinner Security System crypto accelerator
Date: Thu, 9 Jul 2015 08:41:50 +0200	[thread overview]
Message-ID: <20150709064150.GA4028@Red> (raw)
In-Reply-To: <20150707134936.GA2958-lOAM2aK0SrRLBo1qDEOMRrpzq4S04n8Q@public.gmane.org>

On Tue, Jul 07, 2015 at 09:49:36PM +0800, Herbert Xu wrote:
> On Mon, Jul 06, 2015 at 09:10:47PM +0200, LABBE Corentin wrote:
> >
> > +int sun4i_hash_init(struct ahash_request *areq)
> > +{
> > +	const char *hash_type;
> > +	struct sun4i_req_ctx *op = ahash_request_ctx(areq);
> > +	struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
> > +	struct ahash_alg *alg = __crypto_ahash_alg(tfm->base.__crt_alg);
> > +	struct sun4i_ss_alg_template *algt;
> > +	struct sun4i_ss_ctx *ss;
> > +
> > +	memset(op, 0, sizeof(struct sun4i_req_ctx));
> > +
> > +	algt = container_of(alg, struct sun4i_ss_alg_template, alg.hash);
> > +	ss = algt->ss;
> > +	op->ss = algt->ss;
> > +
> > +	hash_type = crypto_tfm_alg_name(areq->base.tfm);
> > +
> > +	if (strcmp(hash_type, "sha1") == 0)
> > +		op->mode = SS_OP_SHA1;
> > +	else if (strcmp(hash_type, "md5") == 0)
> > +		op->mode = SS_OP_MD5;
> 
> Please store these modes in algt and then you wouldn't need to do
> the strcmp.
> 

thanks, that's better

> > +int sun4i_hash_import_md5(struct ahash_request *areq, const void *in)
> > +{
> > +	struct sun4i_req_ctx *op = ahash_request_ctx(areq);
> > +	const struct md5_state *ictx = in;
> > +	int i;
> 
> You need to initialise op->ss here.  Ditto for SHA.
> 

Ok

> > +	/* get the partial hash only if something was written */
> > +	if (op->mode == SS_OP_SHA1) {
> > +		for (i = 0; i < 5; i++)
> > +			op->hash[i] = readl(ss->base + SS_MD0 + i * 4);
> > +	} else {
> > +		for (i = 0; i < 4; i++)
> > +			op->hash[i] = readl(ss->base + SS_MD0 + i * 4);
> > +	}
> 
> You can avoid the op->mode check by storing the hash size in algt.
> 

It seems that I can use crypto_ahash_digestsize() that do the same thing.

> > +int sun4i_hash_finup(struct ahash_request *areq)
> > +{
> > +	int err;
> > +
> > +	err = sun4i_hash_update(areq);
> > +	if (err != 0)
> > +		return err;
> > +
> > +	return sun4i_hash_final(areq);
> 
> You can drop finup since the API provides a default finup that's
> exactly the same as this.  You only need to provide finup if it
> can optimise on this.
> 
> Ditto for digest.

If I remove digest(), loading the driver crash the kernel with:

Unable to handle kernel NULL pointer dereference at virtual address 00000000
pgd = c0004000
[00000000] *pgd=00000000
Internal error: Oops: 80000007 [#1] PREEMPT SMP ARM
CPU: 0 PID: 10120 Comm: cryptomgr_test Tainted: G            E   4.2.0-rc1+ #78
LR is at crypto_ahash_op+0x30/0x68

For using the default one does I need to do something particular ?

Thanks

LABBE Corentin

WARNING: multiple messages have this Message-ID (diff)
From: clabbe.montjoie@gmail.com (LABBE Corentin)
To: linux-arm-kernel@lists.infradead.org
Subject: [linux-sunxi] Re: [PATCH v10 4/5] crypto: Add Allwinner Security System crypto accelerator
Date: Thu, 9 Jul 2015 08:41:50 +0200	[thread overview]
Message-ID: <20150709064150.GA4028@Red> (raw)
In-Reply-To: <20150707134936.GA2958@gondor.apana.org.au>

On Tue, Jul 07, 2015 at 09:49:36PM +0800, Herbert Xu wrote:
> On Mon, Jul 06, 2015 at 09:10:47PM +0200, LABBE Corentin wrote:
> >
> > +int sun4i_hash_init(struct ahash_request *areq)
> > +{
> > +	const char *hash_type;
> > +	struct sun4i_req_ctx *op = ahash_request_ctx(areq);
> > +	struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
> > +	struct ahash_alg *alg = __crypto_ahash_alg(tfm->base.__crt_alg);
> > +	struct sun4i_ss_alg_template *algt;
> > +	struct sun4i_ss_ctx *ss;
> > +
> > +	memset(op, 0, sizeof(struct sun4i_req_ctx));
> > +
> > +	algt = container_of(alg, struct sun4i_ss_alg_template, alg.hash);
> > +	ss = algt->ss;
> > +	op->ss = algt->ss;
> > +
> > +	hash_type = crypto_tfm_alg_name(areq->base.tfm);
> > +
> > +	if (strcmp(hash_type, "sha1") == 0)
> > +		op->mode = SS_OP_SHA1;
> > +	else if (strcmp(hash_type, "md5") == 0)
> > +		op->mode = SS_OP_MD5;
> 
> Please store these modes in algt and then you wouldn't need to do
> the strcmp.
> 

thanks, that's better

> > +int sun4i_hash_import_md5(struct ahash_request *areq, const void *in)
> > +{
> > +	struct sun4i_req_ctx *op = ahash_request_ctx(areq);
> > +	const struct md5_state *ictx = in;
> > +	int i;
> 
> You need to initialise op->ss here.  Ditto for SHA.
> 

Ok

> > +	/* get the partial hash only if something was written */
> > +	if (op->mode == SS_OP_SHA1) {
> > +		for (i = 0; i < 5; i++)
> > +			op->hash[i] = readl(ss->base + SS_MD0 + i * 4);
> > +	} else {
> > +		for (i = 0; i < 4; i++)
> > +			op->hash[i] = readl(ss->base + SS_MD0 + i * 4);
> > +	}
> 
> You can avoid the op->mode check by storing the hash size in algt.
> 

It seems that I can use crypto_ahash_digestsize() that do the same thing.

> > +int sun4i_hash_finup(struct ahash_request *areq)
> > +{
> > +	int err;
> > +
> > +	err = sun4i_hash_update(areq);
> > +	if (err != 0)
> > +		return err;
> > +
> > +	return sun4i_hash_final(areq);
> 
> You can drop finup since the API provides a default finup that's
> exactly the same as this.  You only need to provide finup if it
> can optimise on this.
> 
> Ditto for digest.

If I remove digest(), loading the driver crash the kernel with:

Unable to handle kernel NULL pointer dereference at virtual address 00000000
pgd = c0004000
[00000000] *pgd=00000000
Internal error: Oops: 80000007 [#1] PREEMPT SMP ARM
CPU: 0 PID: 10120 Comm: cryptomgr_test Tainted: G            E   4.2.0-rc1+ #78
LR is at crypto_ahash_op+0x30/0x68

For using the default one does I need to do something particular ?

Thanks

LABBE Corentin

WARNING: multiple messages have this Message-ID (diff)
From: LABBE Corentin <clabbe.montjoie@gmail.com>
To: Herbert Xu <herbert@gondor.apana.org.au>
Cc: robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com,
	ijc+devicetree@hellion.org.uk, galak@codeaurora.org,
	maxime.ripard@free-electrons.com, linux@arm.linux.org.uk,
	davem@davemloft.net, akpm@linux-foundation.org,
	gregkh@linuxfoundation.org, mchehab@osg.samsung.com,
	arnd@arndb.de, joe@perches.com, devicetree@vger.kernel.org,
	linux-doc@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-crypto@vger.kernel.org,
	linux-sunxi@googlegroups.com
Subject: Re: [linux-sunxi] Re: [PATCH v10 4/5] crypto: Add Allwinner Security System crypto accelerator
Date: Thu, 9 Jul 2015 08:41:50 +0200	[thread overview]
Message-ID: <20150709064150.GA4028@Red> (raw)
In-Reply-To: <20150707134936.GA2958@gondor.apana.org.au>

On Tue, Jul 07, 2015 at 09:49:36PM +0800, Herbert Xu wrote:
> On Mon, Jul 06, 2015 at 09:10:47PM +0200, LABBE Corentin wrote:
> >
> > +int sun4i_hash_init(struct ahash_request *areq)
> > +{
> > +	const char *hash_type;
> > +	struct sun4i_req_ctx *op = ahash_request_ctx(areq);
> > +	struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
> > +	struct ahash_alg *alg = __crypto_ahash_alg(tfm->base.__crt_alg);
> > +	struct sun4i_ss_alg_template *algt;
> > +	struct sun4i_ss_ctx *ss;
> > +
> > +	memset(op, 0, sizeof(struct sun4i_req_ctx));
> > +
> > +	algt = container_of(alg, struct sun4i_ss_alg_template, alg.hash);
> > +	ss = algt->ss;
> > +	op->ss = algt->ss;
> > +
> > +	hash_type = crypto_tfm_alg_name(areq->base.tfm);
> > +
> > +	if (strcmp(hash_type, "sha1") == 0)
> > +		op->mode = SS_OP_SHA1;
> > +	else if (strcmp(hash_type, "md5") == 0)
> > +		op->mode = SS_OP_MD5;
> 
> Please store these modes in algt and then you wouldn't need to do
> the strcmp.
> 

thanks, that's better

> > +int sun4i_hash_import_md5(struct ahash_request *areq, const void *in)
> > +{
> > +	struct sun4i_req_ctx *op = ahash_request_ctx(areq);
> > +	const struct md5_state *ictx = in;
> > +	int i;
> 
> You need to initialise op->ss here.  Ditto for SHA.
> 

Ok

> > +	/* get the partial hash only if something was written */
> > +	if (op->mode == SS_OP_SHA1) {
> > +		for (i = 0; i < 5; i++)
> > +			op->hash[i] = readl(ss->base + SS_MD0 + i * 4);
> > +	} else {
> > +		for (i = 0; i < 4; i++)
> > +			op->hash[i] = readl(ss->base + SS_MD0 + i * 4);
> > +	}
> 
> You can avoid the op->mode check by storing the hash size in algt.
> 

It seems that I can use crypto_ahash_digestsize() that do the same thing.

> > +int sun4i_hash_finup(struct ahash_request *areq)
> > +{
> > +	int err;
> > +
> > +	err = sun4i_hash_update(areq);
> > +	if (err != 0)
> > +		return err;
> > +
> > +	return sun4i_hash_final(areq);
> 
> You can drop finup since the API provides a default finup that's
> exactly the same as this.  You only need to provide finup if it
> can optimise on this.
> 
> Ditto for digest.

If I remove digest(), loading the driver crash the kernel with:

Unable to handle kernel NULL pointer dereference at virtual address 00000000
pgd = c0004000
[00000000] *pgd=00000000
Internal error: Oops: 80000007 [#1] PREEMPT SMP ARM
CPU: 0 PID: 10120 Comm: cryptomgr_test Tainted: G            E   4.2.0-rc1+ #78
LR is at crypto_ahash_op+0x30/0x68

For using the default one does I need to do something particular ?

Thanks

LABBE Corentin


  parent reply	other threads:[~2015-07-09  6:41 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-07-06 19:10 [PATCH v10] crypto: Add Allwinner Security System crypto accelerator LABBE Corentin
2015-07-06 19:10 ` LABBE Corentin
2015-07-06 19:10 ` LABBE Corentin
     [not found] ` <1436209848-16530-1-git-send-email-clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2015-07-06 19:10   ` [PATCH v10 1/5] ARM: sun4i: dt: Add Security System to A10 SoC DTS LABBE Corentin
2015-07-06 19:10     ` LABBE Corentin
2015-07-06 19:10     ` LABBE Corentin
2015-07-06 19:10   ` [PATCH v10 2/5] ARM: sun7i: dt: Add Security System to A20 " LABBE Corentin
2015-07-06 19:10     ` LABBE Corentin
2015-07-06 19:10     ` LABBE Corentin
2015-07-06 19:10   ` [PATCH v10 3/5] ARM: sun4i: dt: Add DT bindings documentation for SUN4I Security System LABBE Corentin
2015-07-06 19:10     ` LABBE Corentin
2015-07-06 19:10     ` LABBE Corentin
2015-07-06 19:10   ` [PATCH v10 4/5] crypto: Add Allwinner Security System crypto accelerator LABBE Corentin
2015-07-06 19:10     ` LABBE Corentin
2015-07-06 19:10     ` LABBE Corentin
2015-07-07 13:49     ` Herbert Xu
2015-07-07 13:49       ` Herbert Xu
     [not found]       ` <20150707134936.GA2958-lOAM2aK0SrRLBo1qDEOMRrpzq4S04n8Q@public.gmane.org>
2015-07-09  6:41         ` LABBE Corentin [this message]
2015-07-09  6:41           ` [linux-sunxi] " LABBE Corentin
2015-07-09  6:41           ` LABBE Corentin
2015-07-09  6:59           ` Herbert Xu
2015-07-09  6:59             ` Herbert Xu
     [not found]     ` <1436209848-16530-5-git-send-email-clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2015-07-07 14:01       ` Maxime Ripard
2015-07-07 14:01         ` Maxime Ripard
2015-07-07 14:01         ` Maxime Ripard
2015-07-06 19:10   ` [PATCH v10 5/5] MAINTAINERS: Add myself as maintainer of Allwinner Security System LABBE Corentin
2015-07-06 19:10     ` LABBE Corentin
2015-07-06 19:10     ` LABBE Corentin

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