From: Thierry Reding <thierry.reding@gmail.com>
To: Kyle Huey <me@kylehuey.com>
Cc: Rob Herring <robh+dt@kernel.org>, Pawel Moll <pawel.moll@arm.com>,
Mark Rutland <mark.rutland@arm.com>,
Ian Campbell <ijc+devicetree@hellion.org.uk>,
Kumar Gala <galak@codeaurora.org>,
Russell King <linux@arm.linux.org.uk>,
Stephen Warren <swarren@wwwdotorg.org>,
Alexandre Courbot <gnurou@gmail.com>,
"open list:OPEN FIRMWARE AND..." <devicetree@vger.kernel.org>,
"moderated list:ARM PORT" <linux-arm-kernel@lists.infradead.org>,
"open list:TEGRA ARCHITECTUR..." <linux-tegra@vger.kernel.org>,
open list <linux-kernel@vger.kernel.org>,
Jon Hunter <jonathanh@nvidia.com>, Kyle Huey <khuey@kylehuey.com>
Subject: Re: [RESEND PATCH v3] ARM: tegra124: pmu support
Date: Fri, 17 Jul 2015 10:59:47 +0200 [thread overview]
Message-ID: <20150717085946.GB3057@ulmo> (raw)
In-Reply-To: <1436808945-14524-1-git-send-email-khuey@kylehuey.com>
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On Mon, Jul 13, 2015 at 10:35:45AM -0700, Kyle Huey wrote:
> This patch modifies the device tree for tegra124 based devices to enable
> the Cortex A15 PMU. The interrupt numbers are taken from NVIDIA TRM
> DP-06905-001_v03p. This patch was tested on a Jetson TK1.
>
> Updated for proper ordering and to add interrupt-affinity values.
>
> Signed-off-by: Kyle Huey <khuey@kylehuey.com>
> ---
> arch/arm/boot/dts/tegra124.dtsi | 17 +++++++++++++----
> 1 file changed, 13 insertions(+), 4 deletions(-)
Is there any way to test this? What are the effects of adding this? Does
it enable using perf for profiling?
> diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
> index 13cc7ca..de07d7e 100644
> --- a/arch/arm/boot/dts/tegra124.dtsi
> +++ b/arch/arm/boot/dts/tegra124.dtsi
> @@ -918,31 +918,40 @@
> #address-cells = <1>;
> #size-cells = <0>;
>
> - cpu@0 {
> + A15_0: cpu@0 {
> device_type = "cpu";
> compatible = "arm,cortex-a15";
> reg = <0>;
> };
>
> - cpu@1 {
> + A15_1: cpu@1 {
> device_type = "cpu";
> compatible = "arm,cortex-a15";
> reg = <1>;
> };
>
> - cpu@2 {
> + A15_2: cpu@2 {
> device_type = "cpu";
> compatible = "arm,cortex-a15";
> reg = <2>;
> };
>
> - cpu@3 {
> + A15_3: cpu@3 {
> device_type = "cpu";
> compatible = "arm,cortex-a15";
> reg = <3>;
> };
> };
>
> + pmu {
> + compatible = "arm,cortex-a15-pmu";
> + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-affinity = <&A15_0>, <&A15_1>, <&A15_2>, <&A15_3>;
These labels look somewhat artificial to me, perhaps we could do
something like the following instead?
interrupt-affinity = <&{/cpus/cpu@0}>, ...;
That's slightly more obvious and avoids the need to "invent" labels for
the CPUs.
No need to respin, I can fix that up when applying if nobody objects to
using the alternative notation.
Thierry
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WARNING: multiple messages have this Message-ID (diff)
From: thierry.reding@gmail.com (Thierry Reding)
To: linux-arm-kernel@lists.infradead.org
Subject: [RESEND PATCH v3] ARM: tegra124: pmu support
Date: Fri, 17 Jul 2015 10:59:47 +0200 [thread overview]
Message-ID: <20150717085946.GB3057@ulmo> (raw)
In-Reply-To: <1436808945-14524-1-git-send-email-khuey@kylehuey.com>
On Mon, Jul 13, 2015 at 10:35:45AM -0700, Kyle Huey wrote:
> This patch modifies the device tree for tegra124 based devices to enable
> the Cortex A15 PMU. The interrupt numbers are taken from NVIDIA TRM
> DP-06905-001_v03p. This patch was tested on a Jetson TK1.
>
> Updated for proper ordering and to add interrupt-affinity values.
>
> Signed-off-by: Kyle Huey <khuey@kylehuey.com>
> ---
> arch/arm/boot/dts/tegra124.dtsi | 17 +++++++++++++----
> 1 file changed, 13 insertions(+), 4 deletions(-)
Is there any way to test this? What are the effects of adding this? Does
it enable using perf for profiling?
> diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
> index 13cc7ca..de07d7e 100644
> --- a/arch/arm/boot/dts/tegra124.dtsi
> +++ b/arch/arm/boot/dts/tegra124.dtsi
> @@ -918,31 +918,40 @@
> #address-cells = <1>;
> #size-cells = <0>;
>
> - cpu at 0 {
> + A15_0: cpu at 0 {
> device_type = "cpu";
> compatible = "arm,cortex-a15";
> reg = <0>;
> };
>
> - cpu at 1 {
> + A15_1: cpu at 1 {
> device_type = "cpu";
> compatible = "arm,cortex-a15";
> reg = <1>;
> };
>
> - cpu at 2 {
> + A15_2: cpu at 2 {
> device_type = "cpu";
> compatible = "arm,cortex-a15";
> reg = <2>;
> };
>
> - cpu at 3 {
> + A15_3: cpu at 3 {
> device_type = "cpu";
> compatible = "arm,cortex-a15";
> reg = <3>;
> };
> };
>
> + pmu {
> + compatible = "arm,cortex-a15-pmu";
> + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-affinity = <&A15_0>, <&A15_1>, <&A15_2>, <&A15_3>;
These labels look somewhat artificial to me, perhaps we could do
something like the following instead?
interrupt-affinity = <&{/cpus/cpu@0}>, ...;
That's slightly more obvious and avoids the need to "invent" labels for
the CPUs.
No need to respin, I can fix that up when applying if nobody objects to
using the alternative notation.
Thierry
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next prev parent reply other threads:[~2015-07-17 8:59 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-07-13 17:35 [RESEND PATCH v3] ARM: tegra124: pmu support Kyle Huey
2015-07-13 17:35 ` Kyle Huey
2015-07-13 17:35 ` Kyle Huey
2015-07-15 9:35 ` Mark Rutland
2015-07-15 9:35 ` Mark Rutland
2015-07-17 7:58 ` Jon Hunter
2015-07-17 7:58 ` Jon Hunter
2015-07-17 7:58 ` Jon Hunter
2015-07-17 8:59 ` Thierry Reding [this message]
2015-07-17 8:59 ` Thierry Reding
2015-07-18 13:54 ` Kyle Huey
2015-07-18 13:54 ` Kyle Huey
[not found] ` <CAP045ArZ0PUcpiWYeXsHbjo6BR3YD-ZzTRsBskZzUaQXfOohrg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2015-07-27 16:46 ` Kyle Huey
2015-07-27 16:46 ` Kyle Huey
2015-07-27 16:46 ` Kyle Huey
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