* [PATCH 2/2] clk: zx: Add audio and GPIO clock for zx296702
2015-07-08 9:58 [PATCH 1/2] clk: zx: Add audio div clock method for zx296702 Jun Nie
@ 2015-07-08 9:58 ` Jun Nie
2015-07-21 18:43 ` Stephen Boyd
2015-07-20 3:03 ` [PATCH 1/2] clk: zx: Add audio div clock method " Jun Nie
2015-07-21 18:42 ` Stephen Boyd
2 siblings, 1 reply; 5+ messages in thread
From: Jun Nie @ 2015-07-08 9:58 UTC (permalink / raw)
To: mturquette, sboyd, linux-clk; +Cc: shawn.guo, jason.liu, wan.zhijun, Jun Nie
Add SPDIF/I2S and GPIO clock for zx296702
Signed-off-by: Jun Nie <jun.nie@linaro.org>
---
drivers/clk/zte/clk-zx296702.c | 92 +++++++++++++++++++++++++++++-
include/dt-bindings/clock/zx296702-clock.h | 17 +++++-
2 files changed, 105 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/zte/clk-zx296702.c b/drivers/clk/zte/clk-zx296702.c
index 929d033..9dcac73 100644
--- a/drivers/clk/zte/clk-zx296702.c
+++ b/drivers/clk/zte/clk-zx296702.c
@@ -36,10 +36,21 @@ static struct clk_onecell_data lsp1clk_data;
#define CLK_MUX1 (topcrm_base + 0x8c)
#define CLK_SDMMC1 (lsp0crpm_base + 0x0c)
+#define CLK_GPIO (lsp0crpm_base + 0x2c)
+#define CLK_SPDIF0 (lsp0crpm_base + 0x10)
+#define SPDIF0_DIV (lsp0crpm_base + 0x14)
+#define CLK_I2S0 (lsp0crpm_base + 0x18)
+#define I2S0_DIV (lsp0crpm_base + 0x1c)
+#define CLK_I2S1 (lsp0crpm_base + 0x20)
+#define I2S1_DIV (lsp0crpm_base + 0x24)
+#define CLK_I2S2 (lsp0crpm_base + 0x34)
+#define I2S2_DIV (lsp0crpm_base + 0x38)
#define CLK_UART0 (lsp1crpm_base + 0x20)
#define CLK_UART1 (lsp1crpm_base + 0x24)
#define CLK_SDMMC0 (lsp1crpm_base + 0x2c)
+#define CLK_SPDIF1 (lsp1crpm_base + 0x30)
+#define SPDIF1_DIV (lsp1crpm_base + 0x34)
static const struct zx_pll_config pll_a9_config[] = {
{ .rate = 700000000, .cfg0 = 0x800405d1, .cfg1 = 0x04555555 },
@@ -170,6 +181,21 @@ static const char * uart_wclk_sel[] = {
"lsp1_26M_wclk",
};
+static const char * spdif0_wclk_sel[] = {
+ "lsp0_104M_wclk",
+ "lsp0_26M_wclk",
+};
+
+static const char * spdif1_wclk_sel[] = {
+ "lsp1_104M_wclk",
+ "lsp1_26M_wclk",
+};
+
+static const char * i2s_wclk_sel[] = {
+ "lsp0_104M_wclk",
+ "lsp0_26M_wclk",
+};
+
static inline struct clk *zx_divtbl(const char *name, const char *parent,
void __iomem *reg, u8 shift, u8 width,
const struct clk_div_table *table)
@@ -196,7 +222,7 @@ static inline struct clk *zx_gate(const char *name, const char *parent,
void __iomem *reg, u8 shift)
{
return clk_register_gate(NULL, name, parent, CLK_IGNORE_UNUSED,
- reg, shift, 0, ®_lock);
+ reg, shift, CLK_SET_RATE_PARENT, ®_lock);
}
static void __init zx296702_top_clocks_init(struct device_node *np)
@@ -585,7 +611,57 @@ static void __init zx296702_lsp0_clocks_init(struct device_node *np)
clk[ZX296702_SDMMC1_WCLK] =
zx_gate("sdmmc1_wclk", "sdmmc1_wclk_div", CLK_SDMMC1, 1);
clk[ZX296702_SDMMC1_PCLK] =
- zx_gate("sdmmc1_pclk", "lsp1_apb_pclk", CLK_SDMMC1, 0);
+ zx_gate("sdmmc1_pclk", "lsp0_apb_pclk", CLK_SDMMC1, 0);
+
+ clk[ZX296702_GPIO_CLK] =
+ zx_gate("gpio_clk", "lsp0_apb_pclk", CLK_GPIO, 0);
+
+ /* SPDIF */
+ clk[ZX296702_SPDIF0_WCLK_MUX] =
+ zx_mux("spdif0_wclk_mux", spdif0_wclk_sel,
+ ARRAY_SIZE(spdif0_wclk_sel), CLK_SPDIF0, 4, 1);
+ clk[ZX296702_SPDIF0_WCLK] =
+ zx_gate("spdif0_wclk", "spdif0_wclk_mux", CLK_SPDIF0, 1);
+ clk[ZX296702_SPDIF0_PCLK] =
+ zx_gate("spdif0_pclk", "lsp0_apb_pclk", CLK_SPDIF0, 0);
+
+ clk[ZX296702_SPDIF0_DIV] =
+ clk_register_zx_audio("spdif0_div", "spdif0_wclk", 0,
+ SPDIF0_DIV);
+
+ /* I2S */
+ clk[ZX296702_I2S0_WCLK_MUX] =
+ zx_mux("i2s0_wclk_mux", i2s_wclk_sel,
+ ARRAY_SIZE(i2s_wclk_sel), CLK_I2S0, 4, 1);
+ clk[ZX296702_I2S0_WCLK] =
+ zx_gate("i2s0_wclk", "i2s0_wclk_mux", CLK_I2S0, 1);
+ clk[ZX296702_I2S0_PCLK] =
+ zx_gate("i2s0_pclk", "lsp0_apb_pclk", CLK_I2S0, 0);
+
+ clk[ZX296702_I2S0_DIV] =
+ clk_register_zx_audio("i2s0_div", "i2s0_wclk", 0, I2S0_DIV);
+
+ clk[ZX296702_I2S1_WCLK_MUX] =
+ zx_mux("i2s1_wclk_mux", i2s_wclk_sel,
+ ARRAY_SIZE(i2s_wclk_sel), CLK_I2S1, 4, 1);
+ clk[ZX296702_I2S1_WCLK] =
+ zx_gate("i2s1_wclk", "i2s1_wclk_mux", CLK_I2S1, 1);
+ clk[ZX296702_I2S1_PCLK] =
+ zx_gate("i2s1_pclk", "lsp0_apb_pclk", CLK_I2S1, 0);
+
+ clk[ZX296702_I2S1_DIV] =
+ clk_register_zx_audio("i2s1_div", "i2s1_wclk", 0, I2S1_DIV);
+
+ clk[ZX296702_I2S2_WCLK_MUX] =
+ zx_mux("i2s2_wclk_mux", i2s_wclk_sel,
+ ARRAY_SIZE(i2s_wclk_sel), CLK_I2S2, 4, 1);
+ clk[ZX296702_I2S2_WCLK] =
+ zx_gate("i2s2_wclk", "i2s2_wclk_mux", CLK_I2S2, 1);
+ clk[ZX296702_I2S2_PCLK] =
+ zx_gate("i2s2_pclk", "lsp0_apb_pclk", CLK_I2S2, 0);
+
+ clk[ZX296702_I2S2_DIV] =
+ clk_register_zx_audio("i2s2_div", "i2s2_wclk", 0, I2S2_DIV);
for (i = 0; i < ARRAY_SIZE(lsp0clk); i++) {
if (IS_ERR(clk[i])) {
@@ -641,6 +717,18 @@ static void __init zx296702_lsp1_clocks_init(struct device_node *np)
clk[ZX296702_SDMMC0_PCLK] =
zx_gate("sdmmc0_pclk", "lsp1_apb_pclk", CLK_SDMMC0, 0);
+ clk[ZX296702_SPDIF1_WCLK_MUX] =
+ zx_mux("spdif1_wclk_mux", spdif1_wclk_sel,
+ ARRAY_SIZE(spdif1_wclk_sel), CLK_SPDIF1, 4, 1);
+ clk[ZX296702_SPDIF1_WCLK] =
+ zx_gate("spdif1_wclk", "spdif1_wclk_mux", CLK_SPDIF1, 1);
+ clk[ZX296702_SPDIF1_PCLK] =
+ zx_gate("spdif1_pclk", "lsp1_apb_pclk", CLK_SPDIF1, 0);
+
+ clk[ZX296702_SPDIF1_DIV] =
+ clk_register_zx_audio("spdif1_div", "spdif1_wclk", 0,
+ SPDIF1_DIV);
+
for (i = 0; i < ARRAY_SIZE(lsp1clk); i++) {
if (IS_ERR(clk[i])) {
pr_err("zx296702 clk %d: register failed with %ld\n",
diff --git a/include/dt-bindings/clock/zx296702-clock.h b/include/dt-bindings/clock/zx296702-clock.h
index e683dbb..26ee564 100644
--- a/include/dt-bindings/clock/zx296702-clock.h
+++ b/include/dt-bindings/clock/zx296702-clock.h
@@ -153,7 +153,16 @@
#define ZX296702_I2S0_WCLK 9
#define ZX296702_I2S0_PCLK 10
#define ZX296702_I2S0_DIV 11
-#define ZX296702_LSP0CLK_END 12
+#define ZX296702_I2S1_WCLK_MUX 12
+#define ZX296702_I2S1_WCLK 13
+#define ZX296702_I2S1_PCLK 14
+#define ZX296702_I2S1_DIV 15
+#define ZX296702_I2S2_WCLK_MUX 16
+#define ZX296702_I2S2_WCLK 17
+#define ZX296702_I2S2_PCLK 18
+#define ZX296702_I2S2_DIV 19
+#define ZX296702_GPIO_CLK 20
+#define ZX296702_LSP0CLK_END 21
#define ZX296702_UART0_WCLK_MUX 0
#define ZX296702_UART0_WCLK 1
@@ -165,6 +174,10 @@
#define ZX296702_SDMMC0_WCLK_DIV 7
#define ZX296702_SDMMC0_WCLK 8
#define ZX296702_SDMMC0_PCLK 9
-#define ZX296702_LSP1CLK_END 10
+#define ZX296702_SPDIF1_WCLK_MUX 10
+#define ZX296702_SPDIF1_WCLK 11
+#define ZX296702_SPDIF1_PCLK 12
+#define ZX296702_SPDIF1_DIV 13
+#define ZX296702_LSP1CLK_END 14
#endif /* __DT_BINDINGS_CLOCK_ZX296702_H */
--
1.9.1
^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH 1/2] clk: zx: Add audio div clock method for zx296702
2015-07-08 9:58 [PATCH 1/2] clk: zx: Add audio div clock method for zx296702 Jun Nie
2015-07-08 9:58 ` [PATCH 2/2] clk: zx: Add audio and GPIO clock " Jun Nie
@ 2015-07-20 3:03 ` Jun Nie
2015-07-21 18:42 ` Stephen Boyd
2 siblings, 0 replies; 5+ messages in thread
From: Jun Nie @ 2015-07-20 3:03 UTC (permalink / raw)
To: Stephen Boyd, linux-clk, mturquette
Cc: Shawn Guo, Jason Liu, wan.zhijun, Jun Nie
2015-07-08 17:58 GMT+08:00 Jun Nie <jun.nie@linaro.org>:
> Add SPDIF/I2S divider clock method for zx296702
>
> Signed-off-by: Jun Nie <jun.nie@linaro.org>
> ---
> drivers/clk/zte/clk-pll.c | 113 ++++++++++++++++++++++++++++++++++++++++++++++
> drivers/clk/zte/clk.h | 11 +++++
> 2 files changed, 124 insertions(+)
>
> diff --git a/drivers/clk/zte/clk-pll.c b/drivers/clk/zte/clk-pll.c
> index c3b221a..63f8852 100644
> --- a/drivers/clk/zte/clk-pll.c
> +++ b/drivers/clk/zte/clk-pll.c
> @@ -13,10 +13,12 @@
> #include <linux/iopoll.h>
> #include <linux/slab.h>
> #include <linux/spinlock.h>
> +#include <asm/div64.h>
>
> #include "clk.h"
>
> #define to_clk_zx_pll(_hw) container_of(_hw, struct clk_zx_pll, hw)
> +#define to_clk_zx_audio(_hw) container_of(_hw, struct clk_zx_audio, hw)
>
> #define CFG0_CFG1_OFFSET 4
> #define LOCK_FLAG BIT(30)
> @@ -170,3 +172,114 @@ struct clk *clk_register_zx_pll(const char *name, const char *parent_name,
>
> return clk;
> }
> +
> +#define BPAR 1000000
> +static unsigned long zx_audio_recalc_rate(struct clk_hw *hw,
> + unsigned long parent_rate)
> +{
> + struct clk_zx_audio *zx_audio = to_clk_zx_audio(hw);
> + u32 sel, integ, fra_div, tmp;
> + u64 tmp64 = (u64)parent_rate * BPAR;
> +
> + tmp = readl_relaxed(zx_audio->reg_base);
> + sel = (tmp >> 24) & BIT(0);
> + integ = (tmp >> 16) & 0xff;
> + fra_div = tmp & 0xff;
> +
> + tmp = fra_div * BPAR;
> + tmp = tmp / 0x255;
> + tmp += sel * BPAR;
> + tmp += 2 * integ * BPAR;
> + do_div(tmp64, tmp);
> +
> + return (u32)tmp64;
> +}
> +
> +static long zx_audio_round_rate(struct clk_hw *hw, unsigned long rate,
> + unsigned long *prate)
> +{
> + return rate;
> +}
> +
> +static int zx_audio_set_rate(struct clk_hw *hw, unsigned long rate,
> + unsigned long parent_rate)
> +{
> + struct clk_zx_audio *zx_audio = to_clk_zx_audio(hw);
> + u32 sel, integ, fra_div, tmp;
> + u64 tmp64 = (u64)parent_rate * BPAR;
> +
> + do_div(tmp64, rate);
> + integ = (u32)tmp64 / BPAR;
> +
> + tmp = (u32)tmp64 % BPAR;
> + tmp = tmp * 2;
> + sel = tmp / BPAR;
> +
> + tmp = tmp % BPAR;
> + fra_div = tmp * 0xff / BPAR;
> + tmp = (sel << 24) | (integ << 16) | (0xff << 8) | fra_div;
> +
> + /* Set I2S integer divider as 1. This bit is reserved for SPDIF
> + * and do no harm.
> + */
> + tmp |= BIT(28);
> + writel_relaxed(tmp, zx_audio->reg_base);
> +
> + return 0;
> +}
> +
> +#define ZX_AUDIO_EN BIT(25)
> +static int zx_audio_enable(struct clk_hw *hw)
> +{
> + struct clk_zx_audio *zx_audio = to_clk_zx_audio(hw);
> + u32 reg;
> +
> + reg = readl_relaxed(zx_audio->reg_base);
> + writel_relaxed(reg & ~ZX_AUDIO_EN, zx_audio->reg_base);
> + return 0;
> +}
> +
> +static void zx_audio_disable(struct clk_hw *hw)
> +{
> + struct clk_zx_audio *zx_audio = to_clk_zx_audio(hw);
> + u32 reg;
> +
> + reg = readl_relaxed(zx_audio->reg_base);
> + writel_relaxed(reg | ZX_AUDIO_EN, zx_audio->reg_base);
> +}
> +
> +static const struct clk_ops zx_audio_ops = {
> + .recalc_rate = zx_audio_recalc_rate,
> + .round_rate = zx_audio_round_rate,
> + .set_rate = zx_audio_set_rate,
> + .enable = zx_audio_enable,
> + .disable = zx_audio_disable,
> +};
> +
> +struct clk *clk_register_zx_audio(const char *name, const char *parent_name,
> + unsigned long flags, void __iomem *reg_base)
> +{
> + struct clk_zx_audio *zx_audio;
> + struct clk *clk;
> + struct clk_init_data init;
> +
> + zx_audio = kzalloc(sizeof(*zx_audio), GFP_KERNEL);
> + if (!zx_audio)
> + return ERR_PTR(-ENOMEM);
> +
> + init.name = name;
> + init.ops = &zx_audio_ops;
> + init.flags = flags;
> + init.parent_names = parent_name ? &parent_name : NULL;
> + init.num_parents = parent_name ? 1 : 0;
> +
> + zx_audio->reg_base = reg_base;
> + zx_audio->hw.init = &init;
> +
> + clk = clk_register(NULL, &zx_audio->hw);
> +
> + if (IS_ERR(clk))
> + kfree(zx_audio);
> +
> + return clk;
> +}
> diff --git a/drivers/clk/zte/clk.h b/drivers/clk/zte/clk.h
> index 0914a82..eca4a87 100644
> --- a/drivers/clk/zte/clk.h
> +++ b/drivers/clk/zte/clk.h
> @@ -29,4 +29,15 @@ struct clk_zx_pll {
> struct clk *clk_register_zx_pll(const char *name, const char *parent_name,
> unsigned long flags, void __iomem *reg_base,
> const struct zx_pll_config *lookup_table, int count, spinlock_t *lock);
> +
> +
> +struct clk_zx_audio {
> + struct clk_hw hw;
> + void __iomem *reg_base;
> + const struct zx_audio_config *lookup_table; /* order by rate asc */
> + int count;
> +};
> +
> +struct clk *clk_register_zx_audio(const char *name, const char *parent_name,
> + unsigned long flags, void __iomem *reg_base);
> #endif
> --
> 1.9.1
>
Stephen,
Could you help comments or merge these two patches? Thanks!
Jun
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH 1/2] clk: zx: Add audio div clock method for zx296702
2015-07-08 9:58 [PATCH 1/2] clk: zx: Add audio div clock method for zx296702 Jun Nie
2015-07-08 9:58 ` [PATCH 2/2] clk: zx: Add audio and GPIO clock " Jun Nie
2015-07-20 3:03 ` [PATCH 1/2] clk: zx: Add audio div clock method " Jun Nie
@ 2015-07-21 18:42 ` Stephen Boyd
2 siblings, 0 replies; 5+ messages in thread
From: Stephen Boyd @ 2015-07-21 18:42 UTC (permalink / raw)
To: Jun Nie; +Cc: mturquette, linux-clk, shawn.guo, jason.liu, wan.zhijun
On 07/08, Jun Nie wrote:
> diff --git a/drivers/clk/zte/clk-pll.c b/drivers/clk/zte/clk-pll.c
> index c3b221a..63f8852 100644
> --- a/drivers/clk/zte/clk-pll.c
> +++ b/drivers/clk/zte/clk-pll.c
> @@ -13,10 +13,12 @@
> #include <linux/iopoll.h>
> #include <linux/slab.h>
> #include <linux/spinlock.h>
> +#include <asm/div64.h>
>
> #include "clk.h"
>
> #define to_clk_zx_pll(_hw) container_of(_hw, struct clk_zx_pll, hw)
> +#define to_clk_zx_audio(_hw) container_of(_hw, struct clk_zx_audio, hw)
>
> #define CFG0_CFG1_OFFSET 4
> #define LOCK_FLAG BIT(30)
> @@ -170,3 +172,114 @@ struct clk *clk_register_zx_pll(const char *name, const char *parent_name,
>
> return clk;
> }
> +
> +#define BPAR 1000000
> +static unsigned long zx_audio_recalc_rate(struct clk_hw *hw,
This doesn't look to be a PLL. So please make a new file or
rename this file to something more generic.
> + unsigned long parent_rate)
> +{
> + struct clk_zx_audio *zx_audio = to_clk_zx_audio(hw);
> + u32 sel, integ, fra_div, tmp;
> + u64 tmp64 = (u64)parent_rate * BPAR;
> +
> + tmp = readl_relaxed(zx_audio->reg_base);
> + sel = (tmp >> 24) & BIT(0);
> + integ = (tmp >> 16) & 0xff;
> + fra_div = tmp & 0xff;
> +
> + tmp = fra_div * BPAR;
> + tmp = tmp / 0x255;
> + tmp += sel * BPAR;
> + tmp += 2 * integ * BPAR;
> + do_div(tmp64, tmp);
> +
> + return (u32)tmp64;
> +}
> +
> +static long zx_audio_round_rate(struct clk_hw *hw, unsigned long rate,
> + unsigned long *prate)
> +{
> + return rate;
> +}
This doesn't seem to match the zx_audio_recalc_rate()
implementation. This function needs to tell us what the rate of
the clock is going to be if we call zx_audio_set_rate() with the
same arguments.
> +
> +static int zx_audio_set_rate(struct clk_hw *hw, unsigned long rate,
> + unsigned long parent_rate)
> +{
> + struct clk_zx_audio *zx_audio = to_clk_zx_audio(hw);
> + u32 sel, integ, fra_div, tmp;
> + u64 tmp64 = (u64)parent_rate * BPAR;
> +
> + do_div(tmp64, rate);
> + integ = (u32)tmp64 / BPAR;
> +
> + tmp = (u32)tmp64 % BPAR;
> + tmp = tmp * 2;
> + sel = tmp / BPAR;
> +
> + tmp = tmp % BPAR;
> + fra_div = tmp * 0xff / BPAR;
> + tmp = (sel << 24) | (integ << 16) | (0xff << 8) | fra_div;
> +
> + /* Set I2S integer divider as 1. This bit is reserved for SPDIF
> + * and do no harm.
> + */
> + tmp |= BIT(28);
> + writel_relaxed(tmp, zx_audio->reg_base);
> +
> + return 0;
> +}
[...]
> +
> +static const struct clk_ops zx_audio_ops = {
> + .recalc_rate = zx_audio_recalc_rate,
> + .round_rate = zx_audio_round_rate,
> + .set_rate = zx_audio_set_rate,
> + .enable = zx_audio_enable,
> + .disable = zx_audio_disable,
> +};
> +
> +struct clk *clk_register_zx_audio(const char *name, const char *parent_name,
Can this be const char * const parent_name?
> + unsigned long flags, void __iomem *reg_base)
> +{
> + struct clk_zx_audio *zx_audio;
> + struct clk *clk;
> + struct clk_init_data init;
> +
> + zx_audio = kzalloc(sizeof(*zx_audio), GFP_KERNEL);
> + if (!zx_audio)
> + return ERR_PTR(-ENOMEM);
> +
> + init.name = name;
> + init.ops = &zx_audio_ops;
> + init.flags = flags;
> + init.parent_names = parent_name ? &parent_name : NULL;
> + init.num_parents = parent_name ? 1 : 0;
> +
> + zx_audio->reg_base = reg_base;
> + zx_audio->hw.init = &init;
> +
> + clk = clk_register(NULL, &zx_audio->hw);
> +
Nitpick: Remove this newline
> + if (IS_ERR(clk))
> + kfree(zx_audio);
> +
> + return clk;
> +}
--
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a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 5+ messages in thread