[PATCH 1/7] mtd: spi-nor: fsl-quadspi: use quirk to distinguish different qspi version

[PATCH 1/7] mtd: spi-nor: fsl-quadspi: use quirk to distinguish different qspi version

[Frank.Li]

From: Han Xu <b45815@freescale.com>

add several quirk to distinguish different version of qspi module.

Signed-off-by: Han Xu <b45815@freescale.com>
---
 drivers/mtd/spi-nor/fsl-quadspi.c | 24 ++++++++++++++++--------
 1 file changed, 16 insertions(+), 8 deletions(-)

diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl-quadspi.c
index e854004..258bebf 100644
--- a/drivers/mtd/spi-nor/fsl-quadspi.c
+++ b/drivers/mtd/spi-nor/fsl-quadspi.c
@@ -28,6 +28,11 @@
 #include <linux/mtd/spi-nor.h>
 #include <linux/mutex.h>
 
+/* Controller needs driver to swap endian */
+#define QUADSPI_QUIRK_SWAP_ENDIAN	(1 << 0)
+/* Controller needs 4x internal clock */
+#define QUADSPI_QUIRK_4X_INT_CLK	(1 << 1)
+
 /* The registers */
 #define QUADSPI_MCR			0x00
 #define QUADSPI_MCR_RESERVED_SHIFT	16
@@ -202,20 +207,23 @@ struct fsl_qspi_devtype_data {
 	int rxfifo;
 	int txfifo;
 	int ahb_buf_size;
+	int driver_data;
 };
 
 static struct fsl_qspi_devtype_data vybrid_data = {
 	.devtype = FSL_QUADSPI_VYBRID,
 	.rxfifo = 128,
 	.txfifo = 64,
-	.ahb_buf_size = 1024
+	.ahb_buf_size = 1024,
+	.driver_data = QUADSPI_QUIRK_SWAP_ENDIAN
 };
 
 static struct fsl_qspi_devtype_data imx6sx_data = {
 	.devtype = FSL_QUADSPI_IMX6SX,
 	.rxfifo = 128,
 	.txfifo = 512,
-	.ahb_buf_size = 1024
+	.ahb_buf_size = 1024,
+	.driver_data = QUADSPI_QUIRK_4X_INT_CLK
 };
 
 #define FSL_QSPI_MAX_CHIP	4
@@ -239,14 +247,14 @@ struct fsl_qspi {
 	struct mutex lock;
 };
 
-static inline int is_vybrid_qspi(struct fsl_qspi *q)
+static inline int needs_swap_endian(struct fsl_qspi *q)
 {
-	return q->devtype_data->devtype == FSL_QUADSPI_VYBRID;
+	return q->devtype_data->driver_data & QUADSPI_QUIRK_SWAP_ENDIAN;
 }
 
-static inline int is_imx6sx_qspi(struct fsl_qspi *q)
+static inline int needs_4x_clock(struct fsl_qspi *q)
 {
-	return q->devtype_data->devtype == FSL_QUADSPI_IMX6SX;
+	return q->devtype_data->driver_data & QUADSPI_QUIRK_4X_INT_CLK;
 }
 
 /*
@@ -255,7 +263,7 @@ static inline int is_imx6sx_qspi(struct fsl_qspi *q)
  */
 static inline u32 fsl_qspi_endian_xchg(struct fsl_qspi *q, u32 a)
 {
-	return is_vybrid_qspi(q) ? __swab32(a) : a;
+	return needs_swap_endian(q) ? __swab32(a) : a;
 }
 
 static inline void fsl_qspi_unlock_lut(struct fsl_qspi *q)
@@ -650,7 +658,7 @@ static int fsl_qspi_nor_setup_last(struct fsl_qspi *q)
 	unsigned long rate = q->clk_rate;
 	int ret;
 
-	if (is_imx6sx_qspi(q))
+	if (needs_4x_clock(q))
 		rate *= 4;
 
 	ret = clk_set_rate(q->clk, rate);
-- 
1.9.1

[PATCH 2/7] mtd: spi-nor: fsl-quadspi: add imx7d support

[Frank.Li]

From: Frank Li <Frank.Li@freescale.com>

Support i.mx7d.
quadspi in i.mx7d increase rxfifo.
require fill at least 16byte to trigger data transfer.

Signed-off-by: Frank Li <Frank.Li@freescale.com>
Signed-off-by: Han Xu <b45815@freescale.com>
---
 drivers/mtd/spi-nor/fsl-quadspi.c | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl-quadspi.c
index 258bebf..9c3e38d 100644
--- a/drivers/mtd/spi-nor/fsl-quadspi.c
+++ b/drivers/mtd/spi-nor/fsl-quadspi.c
@@ -32,6 +32,11 @@
 #define QUADSPI_QUIRK_SWAP_ENDIAN	(1 << 0)
 /* Controller needs 4x internal clock */
 #define QUADSPI_QUIRK_4X_INT_CLK	(1 << 1)
+/*
+ * TKT253890, Controller needs driver to fill txfifo till 16 byte to
+ * trigger data transfer even though extern data will not transferred.
+ */
+#define QUADSPI_QUIRK_TKT253890		(1 << 2)
 
 /* The registers */
 #define QUADSPI_MCR			0x00
@@ -200,6 +205,7 @@
 enum fsl_qspi_devtype {
 	FSL_QUADSPI_VYBRID,
 	FSL_QUADSPI_IMX6SX,
+	FSL_QUADSPI_IMX7D,
 };
 
 struct fsl_qspi_devtype_data {
@@ -226,6 +232,15 @@ static struct fsl_qspi_devtype_data imx6sx_data = {
 	.driver_data = QUADSPI_QUIRK_4X_INT_CLK
 };
 
+static struct fsl_qspi_devtype_data imx7d_data = {
+	.devtype = FSL_QUADSPI_IMX7D,
+	.rxfifo = 512,
+	.txfifo = 512,
+	.ahb_buf_size = 1024,
+	.driver_data = QUADSPI_QUIRK_TKT253890
+		       | QUADSPI_QUIRK_4X_INT_CLK
+};
+
 #define FSL_QSPI_MAX_CHIP	4
 struct fsl_qspi {
 	struct mtd_info mtd[FSL_QSPI_MAX_CHIP];
@@ -257,6 +272,11 @@ static inline int needs_4x_clock(struct fsl_qspi *q)
 	return q->devtype_data->driver_data & QUADSPI_QUIRK_4X_INT_CLK;
 }
 
+static inline int needs_fill_txfifo(struct fsl_qspi *q)
+{
+	return q->devtype_data->driver_data & QUADSPI_QUIRK_TKT253890;
+}
+
 /*
  * An IC bug makes us to re-arrange the 32-bit data.
  * The following chips, such as IMX6SLX, have fixed this bug.
@@ -558,6 +578,11 @@ static int fsl_qspi_nor_write(struct fsl_qspi *q, struct spi_nor *nor,
 		txbuf++;
 	}
 
+	/* fill the TXFIFO upto 16 bytes for i.MX7d */
+	if (needs_fill_txfifo(q))
+		for (; i < 4; i++)
+			writel(tmp, q->iobase + QUADSPI_TBDR);
+
 	/* Trigger it */
 	ret = fsl_qspi_runcmd(q, opcode, to, count);
 
@@ -677,6 +702,7 @@ static int fsl_qspi_nor_setup_last(struct fsl_qspi *q)
 static const struct of_device_id fsl_qspi_dt_ids[] = {
 	{ .compatible = "fsl,vf610-qspi", .data = (void *)&vybrid_data, },
 	{ .compatible = "fsl,imx6sx-qspi", .data = (void *)&imx6sx_data, },
+	{ .compatible = "fsl,imx7d-qspi", .data = (void *)&imx7d_data, },
 	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, fsl_qspi_dt_ids);
-- 
1.9.1

Re: [PATCH 2/7] mtd: spi-nor: fsl-quadspi: add imx7d support

[Han Xu]

On Tue, Jul 21, 2015 at 2:39 PM,  <Frank.Li@freescale.com> wrote:
> From: Frank Li <Frank.Li@freescale.com>
>
> Support i.mx7d.
> quadspi in i.mx7d increase rxfifo.
> require fill at least 16byte to trigger data transfer.
>
> Signed-off-by: Frank Li <Frank.Li@freescale.com>
> Signed-off-by: Han Xu <b45815@freescale.com>

Acked-by: Han Xu <han.xu@freescale.com>

> ---
>  drivers/mtd/spi-nor/fsl-quadspi.c | 26 ++++++++++++++++++++++++++
>  1 file changed, 26 insertions(+)
>
> diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl-quadspi.c
> index 258bebf..9c3e38d 100644
> --- a/drivers/mtd/spi-nor/fsl-quadspi.c
> +++ b/drivers/mtd/spi-nor/fsl-quadspi.c
> @@ -32,6 +32,11 @@
>  #define QUADSPI_QUIRK_SWAP_ENDIAN      (1 << 0)
>  /* Controller needs 4x internal clock */
>  #define QUADSPI_QUIRK_4X_INT_CLK       (1 << 1)
> +/*
> + * TKT253890, Controller needs driver to fill txfifo till 16 byte to
> + * trigger data transfer even though extern data will not transferred.
> + */
> +#define QUADSPI_QUIRK_TKT253890                (1 << 2)
>
>  /* The registers */
>  #define QUADSPI_MCR                    0x00
> @@ -200,6 +205,7 @@
>  enum fsl_qspi_devtype {
>         FSL_QUADSPI_VYBRID,
>         FSL_QUADSPI_IMX6SX,
> +       FSL_QUADSPI_IMX7D,
>  };
>
>  struct fsl_qspi_devtype_data {
> @@ -226,6 +232,15 @@ static struct fsl_qspi_devtype_data imx6sx_data = {
>         .driver_data = QUADSPI_QUIRK_4X_INT_CLK
>  };
>
> +static struct fsl_qspi_devtype_data imx7d_data = {
> +       .devtype = FSL_QUADSPI_IMX7D,
> +       .rxfifo = 512,
> +       .txfifo = 512,
> +       .ahb_buf_size = 1024,
> +       .driver_data = QUADSPI_QUIRK_TKT253890
> +                      | QUADSPI_QUIRK_4X_INT_CLK
> +};
> +
>  #define FSL_QSPI_MAX_CHIP      4
>  struct fsl_qspi {
>         struct mtd_info mtd[FSL_QSPI_MAX_CHIP];
> @@ -257,6 +272,11 @@ static inline int needs_4x_clock(struct fsl_qspi *q)
>         return q->devtype_data->driver_data & QUADSPI_QUIRK_4X_INT_CLK;
>  }
>
> +static inline int needs_fill_txfifo(struct fsl_qspi *q)
> +{
> +       return q->devtype_data->driver_data & QUADSPI_QUIRK_TKT253890;
> +}
> +
>  /*
>   * An IC bug makes us to re-arrange the 32-bit data.
>   * The following chips, such as IMX6SLX, have fixed this bug.
> @@ -558,6 +578,11 @@ static int fsl_qspi_nor_write(struct fsl_qspi *q, struct spi_nor *nor,
>                 txbuf++;
>         }
>
> +       /* fill the TXFIFO upto 16 bytes for i.MX7d */
> +       if (needs_fill_txfifo(q))
> +               for (; i < 4; i++)
> +                       writel(tmp, q->iobase + QUADSPI_TBDR);
> +
>         /* Trigger it */
>         ret = fsl_qspi_runcmd(q, opcode, to, count);
>
> @@ -677,6 +702,7 @@ static int fsl_qspi_nor_setup_last(struct fsl_qspi *q)
>  static const struct of_device_id fsl_qspi_dt_ids[] = {
>         { .compatible = "fsl,vf610-qspi", .data = (void *)&vybrid_data, },
>         { .compatible = "fsl,imx6sx-qspi", .data = (void *)&imx6sx_data, },
> +       { .compatible = "fsl,imx7d-qspi", .data = (void *)&imx7d_data, },
>         { /* sentinel */ }
>  };
>  MODULE_DEVICE_TABLE(of, fsl_qspi_dt_ids);
> --
> 1.9.1
>
>
> ______________________________________________________
> Linux MTD discussion mailing list
> http://lists.infradead.org/mailman/listinfo/linux-mtd/

[PATCH 3/7] mtd: spi-nor: fsl-quadspi: add i.mx6ul support

[Frank.Li]

From: Frank Li <Frank.Li@freescale.com>

Add i.mx6ul chip support

Signed-off-by: Frank Li <Frank.Li@freescale.com>
---
 drivers/mtd/spi-nor/fsl-quadspi.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl-quadspi.c
index 9c3e38d..921fba1 100644
--- a/drivers/mtd/spi-nor/fsl-quadspi.c
+++ b/drivers/mtd/spi-nor/fsl-quadspi.c
@@ -206,6 +206,7 @@ enum fsl_qspi_devtype {
 	FSL_QUADSPI_VYBRID,
 	FSL_QUADSPI_IMX6SX,
 	FSL_QUADSPI_IMX7D,
+	FSL_QUADSPI_IMX6UL,
 };
 
 struct fsl_qspi_devtype_data {
@@ -241,6 +242,15 @@ static struct fsl_qspi_devtype_data imx7d_data = {
 		       | QUADSPI_QUIRK_4X_INT_CLK
 };
 
+static struct fsl_qspi_devtype_data imx6ul_data = {
+	.devtype = FSL_QUADSPI_IMX6UL,
+	.rxfifo = 128,
+	.txfifo = 512,
+	.ahb_buf_size = 1024,
+	.driver_data = QUADSPI_QUIRK_TKT253890
+		       | QUADSPI_QUIRK_4X_INT_CLK
+};
+
 #define FSL_QSPI_MAX_CHIP	4
 struct fsl_qspi {
 	struct mtd_info mtd[FSL_QSPI_MAX_CHIP];
@@ -703,6 +713,7 @@ static const struct of_device_id fsl_qspi_dt_ids[] = {
 	{ .compatible = "fsl,vf610-qspi", .data = (void *)&vybrid_data, },
 	{ .compatible = "fsl,imx6sx-qspi", .data = (void *)&imx6sx_data, },
 	{ .compatible = "fsl,imx7d-qspi", .data = (void *)&imx7d_data, },
+	{ .compatible = "fsl,imx6ul-qspi", .data = (void *)&imx6ul_data, },
 	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, fsl_qspi_dt_ids);
-- 
1.9.1

Re: [PATCH 3/7] mtd: spi-nor: fsl-quadspi: add i.mx6ul support

[Han Xu]

On Tue, Jul 21, 2015 at 2:39 PM,  <Frank.Li@freescale.com> wrote:
> From: Frank Li <Frank.Li@freescale.com>
>
> Add i.mx6ul chip support
>
> Signed-off-by: Frank Li <Frank.Li@freescale.com>

Acked-by: Han Xu <han.xu@freescale.com>

> ---
>  drivers/mtd/spi-nor/fsl-quadspi.c | 11 +++++++++++
>  1 file changed, 11 insertions(+)
>
> diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl-quadspi.c
> index 9c3e38d..921fba1 100644
> --- a/drivers/mtd/spi-nor/fsl-quadspi.c
> +++ b/drivers/mtd/spi-nor/fsl-quadspi.c
> @@ -206,6 +206,7 @@ enum fsl_qspi_devtype {
>         FSL_QUADSPI_VYBRID,
>         FSL_QUADSPI_IMX6SX,
>         FSL_QUADSPI_IMX7D,
> +       FSL_QUADSPI_IMX6UL,
>  };
>
>  struct fsl_qspi_devtype_data {
> @@ -241,6 +242,15 @@ static struct fsl_qspi_devtype_data imx7d_data = {
>                        | QUADSPI_QUIRK_4X_INT_CLK
>  };
>
> +static struct fsl_qspi_devtype_data imx6ul_data = {
> +       .devtype = FSL_QUADSPI_IMX6UL,
> +       .rxfifo = 128,
> +       .txfifo = 512,
> +       .ahb_buf_size = 1024,
> +       .driver_data = QUADSPI_QUIRK_TKT253890
> +                      | QUADSPI_QUIRK_4X_INT_CLK
> +};
> +
>  #define FSL_QSPI_MAX_CHIP      4
>  struct fsl_qspi {
>         struct mtd_info mtd[FSL_QSPI_MAX_CHIP];
> @@ -703,6 +713,7 @@ static const struct of_device_id fsl_qspi_dt_ids[] = {
>         { .compatible = "fsl,vf610-qspi", .data = (void *)&vybrid_data, },
>         { .compatible = "fsl,imx6sx-qspi", .data = (void *)&imx6sx_data, },
>         { .compatible = "fsl,imx7d-qspi", .data = (void *)&imx7d_data, },
> +       { .compatible = "fsl,imx6ul-qspi", .data = (void *)&imx6ul_data, },
>         { /* sentinel */ }
>  };
>  MODULE_DEVICE_TABLE(of, fsl_qspi_dt_ids);
> --
> 1.9.1
>
>
> ______________________________________________________
> Linux MTD discussion mailing list
> http://lists.infradead.org/mailman/listinfo/linux-mtd/

[PATCH 4/7] mtd: spi-nor: fsl-quadspi: i.MX6SX: fixed the random QSPI access failed issue

[Frank.Li]

From: Allen Xu <b45815@freescale.com>

We found there is a low probability(5%) QSPI access timeout issue,
usually it happened on kernel boot stage, the first time kernel tried to
access QSPI chip. The READ_ID command was sent but not executed,
consequently the probe function failed.

Finally we located the issue by these steps.

1. Since the issue happened randomly and usually it cost half day to
reproduce, we add more debug code in driver, to create a timeout file if
the issue occurred.

2. Prepared an autorun script to keep rebooting the system and check if
the timeout file existed, if the file existed, stop reboot.

3. The system will stop rebooting when timeout error occurred, set the
CCM_CCOSR register and related IOMUX to measure QPSI clock, found there
is no clock output, while clock output can be measured when QSPI driver
successfully probed.

4. Check the code and found QSPI clock rate was changed while not
disabled clock gate, most of the multiplexers on i.MX6 are glitch ones,
clock glitch may occurred and propagated into downstream clock dividers

Based on the new clock flag(CLK_SET_RATE_GATE) and new framework, we
need to change the approach of seting clock rate. In current
implementation, there are several places in which the clock was touched.

1. probe function. prepare and enable clock before setting the QSPI
register, disable and unprepare the clock before exit.

2. nor_setup & nor_setup_last, since we change clock rate in these two
functions.

3. fsl_qspi_prep and fsl_qspi_unprep, clock was enabled only when got
QSPI access request.

4. resume function. Clock was required to restroe the setting after
resume, disable the clock before exit.

Signed-off-by: Allen Xu <b45815@freescale.com>
Signed-off-by: Frank Li <Frank.Li@freescale.com>
---
 drivers/mtd/spi-nor/fsl-quadspi.c | 83 +++++++++++++++++++++++++++------------
 1 file changed, 58 insertions(+), 25 deletions(-)

diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl-quadspi.c
index 921fba1..1419f1f 100644
--- a/drivers/mtd/spi-nor/fsl-quadspi.c
+++ b/drivers/mtd/spi-nor/fsl-quadspi.c
@@ -653,6 +653,32 @@ static void fsl_qspi_init_abh_read(struct fsl_qspi *q)
 		q->iobase + QUADSPI_BFGENCR);
 }
 
+/* This function was used to prepare and enable QSPI clock */
+static int fsl_qspi_clk_prep_enable(struct fsl_qspi *q)
+{
+	int ret;
+
+	ret = clk_prepare_enable(q->clk_en);
+	if (ret)
+		return ret;
+
+	ret = clk_prepare_enable(q->clk);
+	if (ret) {
+		clk_disable_unprepare(q->clk_en);
+		return ret;
+	}
+
+	return 0;
+}
+
+/* This function was used to disable and unprepare QSPI clock */
+static void fsl_qspi_clk_disable_unprep(struct fsl_qspi *q)
+{
+	clk_disable_unprepare(q->clk);
+	clk_disable_unprepare(q->clk_en);
+
+}
+
 /* We use this function to do some basic init for spi_nor_scan(). */
 static int fsl_qspi_nor_setup(struct fsl_qspi *q)
 {
@@ -660,11 +686,19 @@ static int fsl_qspi_nor_setup(struct fsl_qspi *q)
 	u32 reg;
 	int ret;
 
-	/* the default frequency, we will change it in the future.*/
+	/* disable and unprepare clock first */
+	fsl_qspi_clk_disable_unprep(q);
+
+	/* the default frequency, we will change it in the future. */
 	ret = clk_set_rate(q->clk, 66000000);
 	if (ret)
 		return ret;
 
+	/* prepare and enable the clock */
+	ret = fsl_qspi_clk_prep_enable(q);
+	if (ret)
+		return ret;
+
 	/* Init the LUT table. */
 	fsl_qspi_init_lut(q);
 
@@ -696,10 +730,18 @@ static int fsl_qspi_nor_setup_last(struct fsl_qspi *q)
 	if (needs_4x_clock(q))
 		rate *= 4;
 
+	/* disable and unprepare clock first */
+	fsl_qspi_clk_disable_unprep(q);
+
 	ret = clk_set_rate(q->clk, rate);
 	if (ret)
 		return ret;
 
+	/* prepare and enable the clock */
+	ret = fsl_qspi_clk_prep_enable(q);
+	if (ret)
+		return ret;
+
 	/* Init the LUT table again. */
 	fsl_qspi_init_lut(q);
 
@@ -841,22 +883,16 @@ static int fsl_qspi_prep(struct spi_nor *nor, enum spi_nor_ops ops)
 	int ret;
 
 	mutex_lock(&q->lock);
-	ret = clk_enable(q->clk_en);
-	if (ret)
-		goto err_mutex;
 
-	ret = clk_enable(q->clk);
+	ret = fsl_qspi_clk_prep_enable(q);
 	if (ret)
-		goto err_clk;
+		goto err_mutex;
 
 	fsl_qspi_set_base_addr(q, nor);
 	return 0;
 
-err_clk:
-	clk_disable(q->clk_en);
 err_mutex:
 	mutex_unlock(&q->lock);
-
 	return ret;
 }
 
@@ -864,8 +900,7 @@ static void fsl_qspi_unprep(struct spi_nor *nor, enum spi_nor_ops ops)
 {
 	struct fsl_qspi *q = nor->priv;
 
-	clk_disable(q->clk);
-	clk_disable(q->clk_en);
+	fsl_qspi_clk_disable_unprep(q);
 	mutex_unlock(&q->lock);
 }
 
@@ -909,15 +944,9 @@ static int fsl_qspi_probe(struct platform_device *pdev)
 	if (IS_ERR(q->clk))
 		return PTR_ERR(q->clk);
 
-	ret = clk_prepare_enable(q->clk_en);
+	ret = fsl_qspi_clk_prep_enable(q);
 	if (ret) {
-		dev_err(dev, "cannot enable the qspi_en clock: %d\n", ret);
-		return ret;
-	}
-
-	ret = clk_prepare_enable(q->clk);
-	if (ret) {
-		dev_err(dev, "cannot enable the qspi clock: %d\n", ret);
+		dev_err(dev, "can not enable the clock\n");
 		goto clk_failed;
 	}
 
@@ -1023,8 +1052,7 @@ static int fsl_qspi_probe(struct platform_device *pdev)
 	if (ret)
 		goto last_init_failed;
 
-	clk_disable(q->clk);
-	clk_disable(q->clk_en);
+	fsl_qspi_clk_disable_unprep(q);
 	return 0;
 
 last_init_failed:
@@ -1037,9 +1065,9 @@ last_init_failed:
 mutex_failed:
 	mutex_destroy(&q->lock);
 irq_failed:
-	clk_disable_unprepare(q->clk);
+	fsl_qspi_clk_disable_unprep(q);
 clk_failed:
-	clk_disable_unprepare(q->clk_en);
+	dev_err(dev, "Freescale QuadSPI probe failed\n");
 	return ret;
 }
 
@@ -1060,8 +1088,6 @@ static int fsl_qspi_remove(struct platform_device *pdev)
 	writel(0x0, q->iobase + QUADSPI_RSER);
 
 	mutex_destroy(&q->lock);
-	clk_unprepare(q->clk);
-	clk_unprepare(q->clk_en);
 
 	if (q->ahb_addr)
 		iounmap(q->ahb_addr);
@@ -1076,12 +1102,19 @@ static int fsl_qspi_suspend(struct platform_device *pdev, pm_message_t state)
 
 static int fsl_qspi_resume(struct platform_device *pdev)
 {
+	int ret;
 	struct fsl_qspi *q = platform_get_drvdata(pdev);
 
+	ret = fsl_qspi_clk_prep_enable(q);
+	if (ret)
+		return ret;
+
 	fsl_qspi_nor_setup(q);
 	fsl_qspi_set_map_addr(q);
 	fsl_qspi_nor_setup_last(q);
 
+	fsl_qspi_clk_disable_unprep(q);
+
 	return 0;
 }
 
-- 
1.9.1

Re: [PATCH 4/7] mtd: spi-nor: fsl-quadspi: i.MX6SX: fixed the random QSPI access failed issue

[Han Xu]

On Tue, Jul 21, 2015 at 2:39 PM,  <Frank.Li@freescale.com> wrote:
> From: Allen Xu <b45815@freescale.com>
>
> We found there is a low probability(5%) QSPI access timeout issue,
> usually it happened on kernel boot stage, the first time kernel tried to
> access QSPI chip. The READ_ID command was sent but not executed,
> consequently the probe function failed.
>
> Finally we located the issue by these steps.
>
> 1. Since the issue happened randomly and usually it cost half day to
> reproduce, we add more debug code in driver, to create a timeout file if
> the issue occurred.
>
> 2. Prepared an autorun script to keep rebooting the system and check if
> the timeout file existed, if the file existed, stop reboot.
>
> 3. The system will stop rebooting when timeout error occurred, set the
> CCM_CCOSR register and related IOMUX to measure QPSI clock, found there
> is no clock output, while clock output can be measured when QSPI driver
> successfully probed.
>
> 4. Check the code and found QSPI clock rate was changed while not
> disabled clock gate, most of the multiplexers on i.MX6 are glitch ones,
> clock glitch may occurred and propagated into downstream clock dividers
>
> Based on the new clock flag(CLK_SET_RATE_GATE) and new framework, we
> need to change the approach of seting clock rate. In current
> implementation, there are several places in which the clock was touched.
>
> 1. probe function. prepare and enable clock before setting the QSPI
> register, disable and unprepare the clock before exit.
>
> 2. nor_setup & nor_setup_last, since we change clock rate in these two
> functions.
>
> 3. fsl_qspi_prep and fsl_qspi_unprep, clock was enabled only when got
> QSPI access request.
>
> 4. resume function. Clock was required to restroe the setting after
> resume, disable the clock before exit.
>
> Signed-off-by: Allen Xu <b45815@freescale.com>
> Signed-off-by: Frank Li <Frank.Li@freescale.com>

Acked-by: Han Xu <han.xu@freescale.com>

> ---
>  drivers/mtd/spi-nor/fsl-quadspi.c | 83 +++++++++++++++++++++++++++------------
>  1 file changed, 58 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl-quadspi.c
> index 921fba1..1419f1f 100644
> --- a/drivers/mtd/spi-nor/fsl-quadspi.c
> +++ b/drivers/mtd/spi-nor/fsl-quadspi.c
> @@ -653,6 +653,32 @@ static void fsl_qspi_init_abh_read(struct fsl_qspi *q)
>                 q->iobase + QUADSPI_BFGENCR);
>  }
>
> +/* This function was used to prepare and enable QSPI clock */
> +static int fsl_qspi_clk_prep_enable(struct fsl_qspi *q)
> +{
> +       int ret;
> +
> +       ret = clk_prepare_enable(q->clk_en);
> +       if (ret)
> +               return ret;
> +
> +       ret = clk_prepare_enable(q->clk);
> +       if (ret) {
> +               clk_disable_unprepare(q->clk_en);
> +               return ret;
> +       }
> +
> +       return 0;
> +}
> +
> +/* This function was used to disable and unprepare QSPI clock */
> +static void fsl_qspi_clk_disable_unprep(struct fsl_qspi *q)
> +{
> +       clk_disable_unprepare(q->clk);
> +       clk_disable_unprepare(q->clk_en);
> +
> +}
> +
>  /* We use this function to do some basic init for spi_nor_scan(). */
>  static int fsl_qspi_nor_setup(struct fsl_qspi *q)
>  {
> @@ -660,11 +686,19 @@ static int fsl_qspi_nor_setup(struct fsl_qspi *q)
>         u32 reg;
>         int ret;
>
> -       /* the default frequency, we will change it in the future.*/
> +       /* disable and unprepare clock first */
> +       fsl_qspi_clk_disable_unprep(q);
> +
> +       /* the default frequency, we will change it in the future. */
>         ret = clk_set_rate(q->clk, 66000000);
>         if (ret)
>                 return ret;
>
> +       /* prepare and enable the clock */
> +       ret = fsl_qspi_clk_prep_enable(q);
> +       if (ret)
> +               return ret;
> +
>         /* Init the LUT table. */
>         fsl_qspi_init_lut(q);
>
> @@ -696,10 +730,18 @@ static int fsl_qspi_nor_setup_last(struct fsl_qspi *q)
>         if (needs_4x_clock(q))
>                 rate *= 4;
>
> +       /* disable and unprepare clock first */
> +       fsl_qspi_clk_disable_unprep(q);
> +
>         ret = clk_set_rate(q->clk, rate);
>         if (ret)
>                 return ret;
>
> +       /* prepare and enable the clock */
> +       ret = fsl_qspi_clk_prep_enable(q);
> +       if (ret)
> +               return ret;
> +
>         /* Init the LUT table again. */
>         fsl_qspi_init_lut(q);
>
> @@ -841,22 +883,16 @@ static int fsl_qspi_prep(struct spi_nor *nor, enum spi_nor_ops ops)
>         int ret;
>
>         mutex_lock(&q->lock);
> -       ret = clk_enable(q->clk_en);
> -       if (ret)
> -               goto err_mutex;
>
> -       ret = clk_enable(q->clk);
> +       ret = fsl_qspi_clk_prep_enable(q);
>         if (ret)
> -               goto err_clk;
> +               goto err_mutex;
>
>         fsl_qspi_set_base_addr(q, nor);
>         return 0;
>
> -err_clk:
> -       clk_disable(q->clk_en);
>  err_mutex:
>         mutex_unlock(&q->lock);
> -
>         return ret;
>  }
>
> @@ -864,8 +900,7 @@ static void fsl_qspi_unprep(struct spi_nor *nor, enum spi_nor_ops ops)
>  {
>         struct fsl_qspi *q = nor->priv;
>
> -       clk_disable(q->clk);
> -       clk_disable(q->clk_en);
> +       fsl_qspi_clk_disable_unprep(q);
>         mutex_unlock(&q->lock);
>  }
>
> @@ -909,15 +944,9 @@ static int fsl_qspi_probe(struct platform_device *pdev)
>         if (IS_ERR(q->clk))
>                 return PTR_ERR(q->clk);
>
> -       ret = clk_prepare_enable(q->clk_en);
> +       ret = fsl_qspi_clk_prep_enable(q);
>         if (ret) {
> -               dev_err(dev, "cannot enable the qspi_en clock: %d\n", ret);
> -               return ret;
> -       }
> -
> -       ret = clk_prepare_enable(q->clk);
> -       if (ret) {
> -               dev_err(dev, "cannot enable the qspi clock: %d\n", ret);
> +               dev_err(dev, "can not enable the clock\n");
>                 goto clk_failed;
>         }
>
> @@ -1023,8 +1052,7 @@ static int fsl_qspi_probe(struct platform_device *pdev)
>         if (ret)
>                 goto last_init_failed;
>
> -       clk_disable(q->clk);
> -       clk_disable(q->clk_en);
> +       fsl_qspi_clk_disable_unprep(q);
>         return 0;
>
>  last_init_failed:
> @@ -1037,9 +1065,9 @@ last_init_failed:
>  mutex_failed:
>         mutex_destroy(&q->lock);
>  irq_failed:
> -       clk_disable_unprepare(q->clk);
> +       fsl_qspi_clk_disable_unprep(q);
>  clk_failed:
> -       clk_disable_unprepare(q->clk_en);
> +       dev_err(dev, "Freescale QuadSPI probe failed\n");
>         return ret;
>  }
>
> @@ -1060,8 +1088,6 @@ static int fsl_qspi_remove(struct platform_device *pdev)
>         writel(0x0, q->iobase + QUADSPI_RSER);
>
>         mutex_destroy(&q->lock);
> -       clk_unprepare(q->clk);
> -       clk_unprepare(q->clk_en);
>
>         if (q->ahb_addr)
>                 iounmap(q->ahb_addr);
> @@ -1076,12 +1102,19 @@ static int fsl_qspi_suspend(struct platform_device *pdev, pm_message_t state)
>
>  static int fsl_qspi_resume(struct platform_device *pdev)
>  {
> +       int ret;
>         struct fsl_qspi *q = platform_get_drvdata(pdev);
>
> +       ret = fsl_qspi_clk_prep_enable(q);
> +       if (ret)
> +               return ret;
> +
>         fsl_qspi_nor_setup(q);
>         fsl_qspi_set_map_addr(q);
>         fsl_qspi_nor_setup_last(q);
>
> +       fsl_qspi_clk_disable_unprep(q);
> +
>         return 0;
>  }
>
> --
> 1.9.1
>
>
> ______________________________________________________
> Linux MTD discussion mailing list
> http://lists.infradead.org/mailman/listinfo/linux-mtd/

Re: [PATCH 4/7] mtd: spi-nor: fsl-quadspi: i.MX6SX: fixed the random QSPI access failed issue

[Brian Norris]

On Wed, Jul 22, 2015 at 03:39:56AM +0800, Frank.Li@freescale.com wrote:
> From: Allen Xu <b45815@freescale.com>
> 
> We found there is a low probability(5%) QSPI access timeout issue,
> usually it happened on kernel boot stage, the first time kernel tried to
> access QSPI chip. The READ_ID command was sent but not executed,
> consequently the probe function failed.
> 
> Finally we located the issue by these steps.
> 
> 1. Since the issue happened randomly and usually it cost half day to
> reproduce, we add more debug code in driver, to create a timeout file if
> the issue occurred.
> 
> 2. Prepared an autorun script to keep rebooting the system and check if
> the timeout file existed, if the file existed, stop reboot.
> 
> 3. The system will stop rebooting when timeout error occurred, set the
> CCM_CCOSR register and related IOMUX to measure QPSI clock, found there
> is no clock output, while clock output can be measured when QSPI driver
> successfully probed.
> 
> 4. Check the code and found QSPI clock rate was changed while not
> disabled clock gate, most of the multiplexers on i.MX6 are glitch ones,
> clock glitch may occurred and propagated into downstream clock dividers
> 
> Based on the new clock flag(CLK_SET_RATE_GATE) and new framework, we
> need to change the approach of seting clock rate. In current
> implementation, there are several places in which the clock was touched.
> 
> 1. probe function. prepare and enable clock before setting the QSPI
> register, disable and unprepare the clock before exit.
> 
> 2. nor_setup & nor_setup_last, since we change clock rate in these two
> functions.
> 
> 3. fsl_qspi_prep and fsl_qspi_unprep, clock was enabled only when got
> QSPI access request.
> 
> 4. resume function. Clock was required to restroe the setting after
> resume, disable the clock before exit.
> 
> Signed-off-by: Allen Xu <b45815@freescale.com>
> Signed-off-by: Frank Li <Frank.Li@freescale.com>
> ---
>  drivers/mtd/spi-nor/fsl-quadspi.c | 83 +++++++++++++++++++++++++++------------
>  1 file changed, 58 insertions(+), 25 deletions(-)

[...]

This patch does not apply to l2-mtd.git.

Re: [PATCH 4/7] mtd: spi-nor: fsl-quadspi: i.MX6SX: fixed the random QSPI access failed issue

[Zhi Li]

On Fri, Jul 24, 2015 at 11:56 AM, Brian Norris
<computersforpeace@gmail.com> wrote:
> On Wed, Jul 22, 2015 at 03:39:56AM +0800, Frank.Li@freescale.com wrote:
>> From: Allen Xu <b45815@freescale.com>
>>
>> We found there is a low probability(5%) QSPI access timeout issue,
>> usually it happened on kernel boot stage, the first time kernel tried to
>> access QSPI chip. The READ_ID command was sent but not executed,
>> consequently the probe function failed.
>>
>> Finally we located the issue by these steps.
>>
>> 1. Since the issue happened randomly and usually it cost half day to
>> reproduce, we add more debug code in driver, to create a timeout file if
>> the issue occurred.
>>
>> 2. Prepared an autorun script to keep rebooting the system and check if
>> the timeout file existed, if the file existed, stop reboot.
>>
>> 3. The system will stop rebooting when timeout error occurred, set the
>> CCM_CCOSR register and related IOMUX to measure QPSI clock, found there
>> is no clock output, while clock output can be measured when QSPI driver
>> successfully probed.
>>
>> 4. Check the code and found QSPI clock rate was changed while not
>> disabled clock gate, most of the multiplexers on i.MX6 are glitch ones,
>> clock glitch may occurred and propagated into downstream clock dividers
>>
>> Based on the new clock flag(CLK_SET_RATE_GATE) and new framework, we
>> need to change the approach of seting clock rate. In current
>> implementation, there are several places in which the clock was touched.
>>
>> 1. probe function. prepare and enable clock before setting the QSPI
>> register, disable and unprepare the clock before exit.
>>
>> 2. nor_setup & nor_setup_last, since we change clock rate in these two
>> functions.
>>
>> 3. fsl_qspi_prep and fsl_qspi_unprep, clock was enabled only when got
>> QSPI access request.
>>
>> 4. resume function. Clock was required to restroe the setting after
>> resume, disable the clock before exit.
>>
>> Signed-off-by: Allen Xu <b45815@freescale.com>
>> Signed-off-by: Frank Li <Frank.Li@freescale.com>
>> ---
>>  drivers/mtd/spi-nor/fsl-quadspi.c | 83 +++++++++++++++++++++++++++------------
>>  1 file changed, 58 insertions(+), 25 deletions(-)
>
> [...]
>
> This patch does not apply to l2-mtd.git.

Did you try to apply below patch firstly?

[PATCH 1/1] mtd: spi-nor: fsl-qspi: dynamically map memory space for AHB read

Which branch? I can double check.

best regards
Frank Li

Re: [PATCH 4/7] mtd: spi-nor: fsl-quadspi: i.MX6SX: fixed the random QSPI access failed issue

[Brian Norris]

On Fri, Jul 24, 2015 at 12:10:54PM -0500, Zhi Li wrote:
> On Fri, Jul 24, 2015 at 11:56 AM, Brian Norris
> <computersforpeace@gmail.com> wrote:
> > This patch does not apply to l2-mtd.git.
> 
> Did you try to apply below patch firstly?
> 
> [PATCH 1/1] mtd: spi-nor: fsl-qspi: dynamically map memory space for AHB read

No. Why should I? You didn't tell me or any other reviewer. Please list
dependencies explicitly in the cover letter next time.

> Which branch? I can double check.

master

[PATCH 5/7] mtd: spi-nor: fsl-quadspi: workaround qspi can't wakeup from wait mode

[Frank.Li]

From: Frank Li <Frank.Li@freescale.com>

QSPI1 cannot wake up CCM from WAIT mode on SX ARD board, add pmqos to
let PM NOT enter WAIT mode when accessing QSPI1, refer to TKT245618.

Signed-off-by: Frank Li <Frank.Li@freescale.com>
Signed-off-by: Allen Xu <b45815@freescale.com>
---
 drivers/mtd/spi-nor/fsl-quadspi.c | 24 ++++++++++++++++++++----
 1 file changed, 20 insertions(+), 4 deletions(-)

diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl-quadspi.c
index 1419f1f..10a2c23 100644
--- a/drivers/mtd/spi-nor/fsl-quadspi.c
+++ b/drivers/mtd/spi-nor/fsl-quadspi.c
@@ -27,6 +27,7 @@
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/spi-nor.h>
 #include <linux/mutex.h>
+#include <linux/pm_qos.h>
 
 /* Controller needs driver to swap endian */
 #define QUADSPI_QUIRK_SWAP_ENDIAN	(1 << 0)
@@ -37,6 +38,8 @@
  * trigger data transfer even though extern data will not transferred.
  */
 #define QUADSPI_QUIRK_TKT253890		(1 << 2)
+/* Controller cannot wake up from wait mode, TKT245618 */
+#define QUADSPI_QUIRK_TKT245618         (1 << 3)
 
 /* The registers */
 #define QUADSPI_MCR			0x00
@@ -231,6 +234,7 @@ static struct fsl_qspi_devtype_data imx6sx_data = {
 	.txfifo = 512,
 	.ahb_buf_size = 1024,
 	.driver_data = QUADSPI_QUIRK_4X_INT_CLK
+		       | QUADSPI_QUIRK_TKT245618
 };
 
 static struct fsl_qspi_devtype_data imx7d_data = {
@@ -270,6 +274,7 @@ struct fsl_qspi {
 	unsigned int chip_base_addr; /* We may support two chips. */
 	bool has_second_chip;
 	struct mutex lock;
+	struct pm_qos_request pm_qos_req;
 };
 
 static inline int needs_swap_endian(struct fsl_qspi *q)
@@ -287,6 +292,11 @@ static inline int needs_fill_txfifo(struct fsl_qspi *q)
 	return q->devtype_data->driver_data & QUADSPI_QUIRK_TKT253890;
 }
 
+static inline int needs_wakeup_wait_mode(struct fsl_qspi *q)
+{
+	return q->devtype_data->driver_data & QUADSPI_QUIRK_TKT245618;
+}
+
 /*
  * An IC bug makes us to re-arrange the 32-bit data.
  * The following chips, such as IMX6SLX, have fixed this bug.
@@ -668,12 +678,18 @@ static int fsl_qspi_clk_prep_enable(struct fsl_qspi *q)
 		return ret;
 	}
 
+	if (needs_wakeup_wait_mode(q))
+		pm_qos_add_request(&q->pm_qos_req, PM_QOS_CPU_DMA_LATENCY, 0);
+
 	return 0;
 }
 
 /* This function was used to disable and unprepare QSPI clock */
 static void fsl_qspi_clk_disable_unprep(struct fsl_qspi *q)
 {
+	if (needs_wakeup_wait_mode(q))
+		pm_qos_remove_request(&q->pm_qos_req);
+
 	clk_disable_unprepare(q->clk);
 	clk_disable_unprepare(q->clk_en);
 
@@ -925,6 +941,10 @@ static int fsl_qspi_probe(struct platform_device *pdev)
 	if (!q->nor_num || q->nor_num > FSL_QSPI_MAX_CHIP)
 		return -ENODEV;
 
+	q->dev = dev;
+	q->devtype_data = (struct fsl_qspi_devtype_data *)of_id->data;
+	platform_set_drvdata(pdev, q);
+
 	/* find the resources */
 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "QuadSPI");
 	q->iobase = devm_ioremap_resource(dev, res);
@@ -964,10 +984,6 @@ static int fsl_qspi_probe(struct platform_device *pdev)
 		goto irq_failed;
 	}
 
-	q->dev = dev;
-	q->devtype_data = (struct fsl_qspi_devtype_data *)of_id->data;
-	platform_set_drvdata(pdev, q);
-
 	ret = fsl_qspi_nor_setup(q);
 	if (ret)
 		goto irq_failed;
-- 
1.9.1

Re: [PATCH 5/7] mtd: spi-nor: fsl-quadspi: workaround qspi can't wakeup from wait mode

[Han Xu]

On Tue, Jul 21, 2015 at 2:39 PM,  <Frank.Li@freescale.com> wrote:
> From: Frank Li <Frank.Li@freescale.com>
>
> QSPI1 cannot wake up CCM from WAIT mode on SX ARD board, add pmqos to
> let PM NOT enter WAIT mode when accessing QSPI1, refer to TKT245618.
>
> Signed-off-by: Frank Li <Frank.Li@freescale.com>
> Signed-off-by: Allen Xu <b45815@freescale.com>

Acked-by: Han Xu <han.xu@freescale.com>

> ---
>  drivers/mtd/spi-nor/fsl-quadspi.c | 24 ++++++++++++++++++++----
>  1 file changed, 20 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl-quadspi.c
> index 1419f1f..10a2c23 100644
> --- a/drivers/mtd/spi-nor/fsl-quadspi.c
> +++ b/drivers/mtd/spi-nor/fsl-quadspi.c
> @@ -27,6 +27,7 @@
>  #include <linux/mtd/partitions.h>
>  #include <linux/mtd/spi-nor.h>
>  #include <linux/mutex.h>
> +#include <linux/pm_qos.h>
>
>  /* Controller needs driver to swap endian */
>  #define QUADSPI_QUIRK_SWAP_ENDIAN      (1 << 0)
> @@ -37,6 +38,8 @@
>   * trigger data transfer even though extern data will not transferred.
>   */
>  #define QUADSPI_QUIRK_TKT253890                (1 << 2)
> +/* Controller cannot wake up from wait mode, TKT245618 */
> +#define QUADSPI_QUIRK_TKT245618         (1 << 3)
>
>  /* The registers */
>  #define QUADSPI_MCR                    0x00
> @@ -231,6 +234,7 @@ static struct fsl_qspi_devtype_data imx6sx_data = {
>         .txfifo = 512,
>         .ahb_buf_size = 1024,
>         .driver_data = QUADSPI_QUIRK_4X_INT_CLK
> +                      | QUADSPI_QUIRK_TKT245618
>  };
>
>  static struct fsl_qspi_devtype_data imx7d_data = {
> @@ -270,6 +274,7 @@ struct fsl_qspi {
>         unsigned int chip_base_addr; /* We may support two chips. */
>         bool has_second_chip;
>         struct mutex lock;
> +       struct pm_qos_request pm_qos_req;
>  };
>
>  static inline int needs_swap_endian(struct fsl_qspi *q)
> @@ -287,6 +292,11 @@ static inline int needs_fill_txfifo(struct fsl_qspi *q)
>         return q->devtype_data->driver_data & QUADSPI_QUIRK_TKT253890;
>  }
>
> +static inline int needs_wakeup_wait_mode(struct fsl_qspi *q)
> +{
> +       return q->devtype_data->driver_data & QUADSPI_QUIRK_TKT245618;
> +}
> +
>  /*
>   * An IC bug makes us to re-arrange the 32-bit data.
>   * The following chips, such as IMX6SLX, have fixed this bug.
> @@ -668,12 +678,18 @@ static int fsl_qspi_clk_prep_enable(struct fsl_qspi *q)
>                 return ret;
>         }
>
> +       if (needs_wakeup_wait_mode(q))
> +               pm_qos_add_request(&q->pm_qos_req, PM_QOS_CPU_DMA_LATENCY, 0);
> +
>         return 0;
>  }
>
>  /* This function was used to disable and unprepare QSPI clock */
>  static void fsl_qspi_clk_disable_unprep(struct fsl_qspi *q)
>  {
> +       if (needs_wakeup_wait_mode(q))
> +               pm_qos_remove_request(&q->pm_qos_req);
> +
>         clk_disable_unprepare(q->clk);
>         clk_disable_unprepare(q->clk_en);
>
> @@ -925,6 +941,10 @@ static int fsl_qspi_probe(struct platform_device *pdev)
>         if (!q->nor_num || q->nor_num > FSL_QSPI_MAX_CHIP)
>                 return -ENODEV;
>
> +       q->dev = dev;
> +       q->devtype_data = (struct fsl_qspi_devtype_data *)of_id->data;
> +       platform_set_drvdata(pdev, q);
> +
>         /* find the resources */
>         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "QuadSPI");
>         q->iobase = devm_ioremap_resource(dev, res);
> @@ -964,10 +984,6 @@ static int fsl_qspi_probe(struct platform_device *pdev)
>                 goto irq_failed;
>         }
>
> -       q->dev = dev;
> -       q->devtype_data = (struct fsl_qspi_devtype_data *)of_id->data;
> -       platform_set_drvdata(pdev, q);
> -
>         ret = fsl_qspi_nor_setup(q);
>         if (ret)
>                 goto irq_failed;
> --
> 1.9.1
>
>
> ______________________________________________________
> Linux MTD discussion mailing list
> http://lists.infradead.org/mailman/listinfo/linux-mtd/

[PATCH 6/7] mtd: spi-nor: fsl-quadspi: reset the module in the probe

[Frank.Li]

From: Frank Li <Frank.Li@freescale.com>

The uboot may run the QuadSpi controler with command:
    #sf probe

So we should reset the module in the probe.
This patch also clear the pending interrupts which arised by the uboot
code.

Signed-off-by: Huang Shijie <shijie8@gmail.com>
Signed-off-by: Frank Li <Frank.Li@freescale.com>
---
 drivers/mtd/spi-nor/fsl-quadspi.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl-quadspi.c
index 10a2c23..68054c1 100644
--- a/drivers/mtd/spi-nor/fsl-quadspi.c
+++ b/drivers/mtd/spi-nor/fsl-quadspi.c
@@ -715,6 +715,11 @@ static int fsl_qspi_nor_setup(struct fsl_qspi *q)
 	if (ret)
 		return ret;
 
+	/* Reset the module */
+	writel(QUADSPI_MCR_SWRSTSD_MASK | QUADSPI_MCR_SWRSTHD_MASK,
+		base + QUADSPI_MCR);
+	udelay(1);
+
 	/* Init the LUT table. */
 	fsl_qspi_init_lut(q);
 
@@ -732,6 +737,9 @@ static int fsl_qspi_nor_setup(struct fsl_qspi *q)
 	writel(QUADSPI_MCR_RESERVED_MASK | QUADSPI_MCR_END_CFG_MASK,
 			base + QUADSPI_MCR);
 
+	/* clear all interrupt status */
+	writel(0xffffffff, q->iobase + QUADSPI_FR);
+
 	/* enable the interrupt */
 	writel(QUADSPI_RSER_TFIE, q->iobase + QUADSPI_RSER);
 
-- 
1.9.1

Re: [PATCH 6/7] mtd: spi-nor: fsl-quadspi: reset the module in the probe

[Han Xu]

On Tue, Jul 21, 2015 at 2:39 PM,  <Frank.Li@freescale.com> wrote:
> From: Frank Li <Frank.Li@freescale.com>
>
> The uboot may run the QuadSpi controler with command:
>     #sf probe
>
> So we should reset the module in the probe.
> This patch also clear the pending interrupts which arised by the uboot
> code.
>
> Signed-off-by: Huang Shijie <shijie8@gmail.com>
> Signed-off-by: Frank Li <Frank.Li@freescale.com>

Acked-by: Han Xu <han.xu@freescale.com>

> ---
>  drivers/mtd/spi-nor/fsl-quadspi.c | 8 ++++++++
>  1 file changed, 8 insertions(+)
>
> diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl-quadspi.c
> index 10a2c23..68054c1 100644
> --- a/drivers/mtd/spi-nor/fsl-quadspi.c
> +++ b/drivers/mtd/spi-nor/fsl-quadspi.c
> @@ -715,6 +715,11 @@ static int fsl_qspi_nor_setup(struct fsl_qspi *q)
>         if (ret)
>                 return ret;
>
> +       /* Reset the module */
> +       writel(QUADSPI_MCR_SWRSTSD_MASK | QUADSPI_MCR_SWRSTHD_MASK,
> +               base + QUADSPI_MCR);
> +       udelay(1);
> +
>         /* Init the LUT table. */
>         fsl_qspi_init_lut(q);
>
> @@ -732,6 +737,9 @@ static int fsl_qspi_nor_setup(struct fsl_qspi *q)
>         writel(QUADSPI_MCR_RESERVED_MASK | QUADSPI_MCR_END_CFG_MASK,
>                         base + QUADSPI_MCR);
>
> +       /* clear all interrupt status */
> +       writel(0xffffffff, q->iobase + QUADSPI_FR);
> +
>         /* enable the interrupt */
>         writel(QUADSPI_RSER_TFIE, q->iobase + QUADSPI_RSER);
>
> --
> 1.9.1
>
>
> ______________________________________________________
> Linux MTD discussion mailing list
> http://lists.infradead.org/mailman/listinfo/linux-mtd/

[PATCH 7/7] mtd: spi-nor: fsl-quadspi: fix unsupported cmd when run flash_erase

[Frank.Li]

From: Frank Li <Frank.Li@freescale.com>

fsl-quadspi 21e0000.qspi: Unsupported cmd 0x20

when config CONFIG_MTD_SPI_NOR_USE_4K_SECTORS enable,
erase will use SPINOR_OP_BE_4K, which was not supported by fsl-quadspi
driver

Signed-off-by: Frank Li <Frank.Li@freescale.com>
---
 drivers/mtd/spi-nor/fsl-quadspi.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl-quadspi.c
index 68054c1..d2981c5 100644
--- a/drivers/mtd/spi-nor/fsl-quadspi.c
+++ b/drivers/mtd/spi-nor/fsl-quadspi.c
@@ -396,11 +396,11 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
 	lut_base = SEQID_SE * 4;
 
 	if (q->nor_size <= SZ_16M) {
-		cmd = SPINOR_OP_SE;
+		cmd = q->nor[0].erase_opcode;
 		addrlen = ADDR24BIT;
 	} else {
 		/* use the 4-byte address */
-		cmd = SPINOR_OP_SE;
+		cmd = q->nor[0].erase_opcode;
 		addrlen = ADDR32BIT;
 	}
 
@@ -471,6 +471,8 @@ static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd)
 	case SPINOR_OP_BRWR:
 		return SEQID_BRWR;
 	default:
+		if (cmd == q->nor[0].erase_opcode)
+			return SEQID_SE;
 		dev_err(q->dev, "Unsupported cmd 0x%.2x\n", cmd);
 		break;
 	}
-- 
1.9.1

Re: [PATCH 7/7] mtd: spi-nor: fsl-quadspi: fix unsupported cmd when run flash_erase

[Han Xu]

On Tue, Jul 21, 2015 at 2:39 PM,  <Frank.Li@freescale.com> wrote:
> From: Frank Li <Frank.Li@freescale.com>
>
> fsl-quadspi 21e0000.qspi: Unsupported cmd 0x20
>
> when config CONFIG_MTD_SPI_NOR_USE_4K_SECTORS enable,
> erase will use SPINOR_OP_BE_4K, which was not supported by fsl-quadspi
> driver
>
> Signed-off-by: Frank Li <Frank.Li@freescale.com>

Acked-by: Han Xu <han.xu@freescale.com>

> ---
>  drivers/mtd/spi-nor/fsl-quadspi.c | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl-quadspi.c
> index 68054c1..d2981c5 100644
> --- a/drivers/mtd/spi-nor/fsl-quadspi.c
> +++ b/drivers/mtd/spi-nor/fsl-quadspi.c
> @@ -396,11 +396,11 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
>         lut_base = SEQID_SE * 4;
>
>         if (q->nor_size <= SZ_16M) {
> -               cmd = SPINOR_OP_SE;
> +               cmd = q->nor[0].erase_opcode;
>                 addrlen = ADDR24BIT;
>         } else {
>                 /* use the 4-byte address */
> -               cmd = SPINOR_OP_SE;
> +               cmd = q->nor[0].erase_opcode;
>                 addrlen = ADDR32BIT;
>         }
>
> @@ -471,6 +471,8 @@ static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd)
>         case SPINOR_OP_BRWR:
>                 return SEQID_BRWR;
>         default:
> +               if (cmd == q->nor[0].erase_opcode)
> +                       return SEQID_SE;
>                 dev_err(q->dev, "Unsupported cmd 0x%.2x\n", cmd);
>                 break;
>         }
> --
> 1.9.1
>
>
> ______________________________________________________
> Linux MTD discussion mailing list
> http://lists.infradead.org/mailman/listinfo/linux-mtd/

Re: [PATCH 1/7] mtd: spi-nor: fsl-quadspi: use quirk to distinguish different qspi version

[Han Xu]

On Tue, Jul 21, 2015 at 2:39 PM,  <Frank.Li@freescale.com> wrote:
> From: Han Xu <b45815@freescale.com>
>
> add several quirk to distinguish different version of qspi module.
>
> Signed-off-by: Han Xu <b45815@freescale.com>

Acked-by: Han Xu <han.xu@freescale.com>

> ---
>  drivers/mtd/spi-nor/fsl-quadspi.c | 24 ++++++++++++++++--------
>  1 file changed, 16 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl-quadspi.c
> index e854004..258bebf 100644
> --- a/drivers/mtd/spi-nor/fsl-quadspi.c
> +++ b/drivers/mtd/spi-nor/fsl-quadspi.c
> @@ -28,6 +28,11 @@
>  #include <linux/mtd/spi-nor.h>
>  #include <linux/mutex.h>
>
> +/* Controller needs driver to swap endian */
> +#define QUADSPI_QUIRK_SWAP_ENDIAN      (1 << 0)
> +/* Controller needs 4x internal clock */
> +#define QUADSPI_QUIRK_4X_INT_CLK       (1 << 1)
> +
>  /* The registers */
>  #define QUADSPI_MCR                    0x00
>  #define QUADSPI_MCR_RESERVED_SHIFT     16
> @@ -202,20 +207,23 @@ struct fsl_qspi_devtype_data {
>         int rxfifo;
>         int txfifo;
>         int ahb_buf_size;
> +       int driver_data;
>  };
>
>  static struct fsl_qspi_devtype_data vybrid_data = {
>         .devtype = FSL_QUADSPI_VYBRID,
>         .rxfifo = 128,
>         .txfifo = 64,
> -       .ahb_buf_size = 1024
> +       .ahb_buf_size = 1024,
> +       .driver_data = QUADSPI_QUIRK_SWAP_ENDIAN
>  };
>
>  static struct fsl_qspi_devtype_data imx6sx_data = {
>         .devtype = FSL_QUADSPI_IMX6SX,
>         .rxfifo = 128,
>         .txfifo = 512,
> -       .ahb_buf_size = 1024
> +       .ahb_buf_size = 1024,
> +       .driver_data = QUADSPI_QUIRK_4X_INT_CLK
>  };
>
>  #define FSL_QSPI_MAX_CHIP      4
> @@ -239,14 +247,14 @@ struct fsl_qspi {
>         struct mutex lock;
>  };
>
> -static inline int is_vybrid_qspi(struct fsl_qspi *q)
> +static inline int needs_swap_endian(struct fsl_qspi *q)
>  {
> -       return q->devtype_data->devtype == FSL_QUADSPI_VYBRID;
> +       return q->devtype_data->driver_data & QUADSPI_QUIRK_SWAP_ENDIAN;
>  }
>
> -static inline int is_imx6sx_qspi(struct fsl_qspi *q)
> +static inline int needs_4x_clock(struct fsl_qspi *q)
>  {
> -       return q->devtype_data->devtype == FSL_QUADSPI_IMX6SX;
> +       return q->devtype_data->driver_data & QUADSPI_QUIRK_4X_INT_CLK;
>  }
>
>  /*
> @@ -255,7 +263,7 @@ static inline int is_imx6sx_qspi(struct fsl_qspi *q)
>   */
>  static inline u32 fsl_qspi_endian_xchg(struct fsl_qspi *q, u32 a)
>  {
> -       return is_vybrid_qspi(q) ? __swab32(a) : a;
> +       return needs_swap_endian(q) ? __swab32(a) : a;
>  }
>
>  static inline void fsl_qspi_unlock_lut(struct fsl_qspi *q)
> @@ -650,7 +658,7 @@ static int fsl_qspi_nor_setup_last(struct fsl_qspi *q)
>         unsigned long rate = q->clk_rate;
>         int ret;
>
> -       if (is_imx6sx_qspi(q))
> +       if (needs_4x_clock(q))
>                 rate *= 4;
>
>         ret = clk_set_rate(q->clk, rate);
> --
> 1.9.1
>
>
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