Re: [Qemu-devel] [PATCH 2/5] target-arm: Wire up AArch64 EL2 and EL3 address translation ops

["Edgar E. Iglesias" <edgar.iglesias@gmail.com>]

On Fri, Jul 24, 2015 at 04:21:00PM +0100, Peter Maydell wrote:
> Wire up the AArch64 EL2 and EL3 address translation operations
> (AT S12E1*, AT S12E0*, AT S1E2*, AT S1E3*), and correct some
> errors in the ats_write64() function in previously unused code
> that would have done the wrong kind of lookup for accesses from
> EL3 when SCR.NS==0.
> 
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


THis one didn't apply for me, I guess some context has moved around a little..

The changes look OK to me though:
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>




> ---
>  target-arm/helper.c | 45 +++++++++++++++++++++++++++++++++++++++++++--
>  1 file changed, 43 insertions(+), 2 deletions(-)
> 
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index 1ac6594..1974fa6 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -1602,6 +1602,14 @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
>      A32_BANKED_CURRENT_REG_SET(env, par, par64);
>  }
>  
> +static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo *ri)
> +{
> +    if (arm_current_el(env) == 3 && !(env->cp15.scr_el3 & SCR_NS)) {
> +        return CP_ACCESS_TRAP;
> +    }
> +    return CP_ACCESS_OK;
> +}
> +
>  static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
>                          uint64_t value)
>  {
> @@ -1629,10 +1637,10 @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
>          mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0;
>          break;
>      case 4: /* AT S12E1R, AT S12E1W */
> -        mmu_idx = ARMMMUIdx_S12NSE1;
> +        mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S12NSE1;
>          break;
>      case 6: /* AT S12E0R, AT S12E0W */
> -        mmu_idx = ARMMMUIdx_S12NSE0;
> +        mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S12NSE0;
>          break;
>      default:
>          g_assert_not_reached();
> @@ -2504,6 +2512,25 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
>      { .name = "AT_S1E0W", .state = ARM_CP_STATE_AA64,
>        .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 3,
>        .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
> +    { .name = "AT_S12E1R", .state = ARM_CP_STATE_AA64,
> +      .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 4,
> +      .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
> +    { .name = "AT_S12E1W", .state = ARM_CP_STATE_AA64,
> +      .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 5,
> +      .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
> +    { .name = "AT_S12E0R", .state = ARM_CP_STATE_AA64,
> +      .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 6,
> +      .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
> +    { .name = "AT_S12E0W", .state = ARM_CP_STATE_AA64,
> +      .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 7,
> +      .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
> +    /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */
> +    { .name = "AT_S1E3R", .state = ARM_CP_STATE_AA64,
> +      .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 0,
> +      .access = PL3_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
> +    { .name = "AT_S1E3W", .state = ARM_CP_STATE_AA64,
> +      .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 1,
> +      .access = PL3_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
>  #endif
>      /* TLB invalidate last level of translation table walk */
>      { .name = "TLBIMVALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
> @@ -2724,6 +2751,20 @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
>        .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1,
>        .type = ARM_CP_NO_RAW, .access = PL2_W,
>        .writefn = tlbi_aa64_vaa_write },
> +#ifndef CONFIG_USER_ONLY
> +    /* Unlike the other EL2-related AT operations, these must
> +     * UNDEF from EL3 if EL2 is not implemented, which is why we
> +     * define them here rather than with the rest of the AT ops.
> +     */
> +    { .name = "AT_S1E2R", .state = ARM_CP_STATE_AA64,
> +      .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0,
> +      .access = PL2_W, .accessfn = at_s1e2_access,
> +      .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
> +    { .name = "AT_S1E2W", .state = ARM_CP_STATE_AA64,
> +      .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1,
> +      .access = PL2_W, .accessfn = at_s1e2_access,
> +      .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
> +#endif
>      REGINFO_SENTINEL
>  };
>  
> -- 
> 1.9.1
>