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From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-devel@nongnu.org, patches@linaro.org
Subject: Re: [Qemu-devel] [PATCH 3/5] target-arm: Add CP_ACCESS_TRAP_UNCATEGORIZED_EL2, 3
Date: Mon, 17 Aug 2015 03:52:46 +0200	[thread overview]
Message-ID: <20150817015246.GG16713@toto> (raw)
In-Reply-To: <1437751263-21913-4-git-send-email-peter.maydell@linaro.org>

On Fri, Jul 24, 2015 at 04:21:01PM +0100, Peter Maydell wrote:
> Some coprocessor register access functions need to be able
> to report "trap to EL3 with an 'uncategorized' syndrome";
> add the necessary CPAccessResult enum and handling for it.
> 
> I don't currently know of any registers that need to trap
> to EL2 with the 'uncategorized' syndrome, but adding the
> _EL2 enum as well is trivial and fills in what would
> otherwise be an odd gap in the handling.
> 
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>


> ---
>  target-arm/cpu.h       | 3 +++
>  target-arm/op_helper.c | 8 ++++++++
>  2 files changed, 11 insertions(+)
> 
> diff --git a/target-arm/cpu.h b/target-arm/cpu.h
> index 7e89152..685474e 100644
> --- a/target-arm/cpu.h
> +++ b/target-arm/cpu.h
> @@ -1280,6 +1280,9 @@ typedef enum CPAccessResult {
>      /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */
>      CP_ACCESS_TRAP_EL2 = 3,
>      CP_ACCESS_TRAP_EL3 = 4,
> +    /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */
> +    CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5,
> +    CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6,
>  } CPAccessResult;
>  
>  /* Access functions for coprocessor registers. These cannot fail and
> diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
> index 663c05d..1425a1d 100644
> --- a/target-arm/op_helper.c
> +++ b/target-arm/op_helper.c
> @@ -444,6 +444,14 @@ void HELPER(access_check_cp_reg)(CPUARMState *env, void *rip, uint32_t syndrome)
>          target_el = exception_target_el(env);
>          syndrome = syn_uncategorized();
>          break;
> +    case CP_ACCESS_TRAP_UNCATEGORIZED_EL2:
> +        target_el = 2;
> +        syndrome = syn_uncategorized();
> +        break;
> +    case CP_ACCESS_TRAP_UNCATEGORIZED_EL3:
> +        target_el = 3;
> +        syndrome = syn_uncategorized();
> +        break;
>      default:
>          g_assert_not_reached();
>      }
> -- 
> 1.9.1
> 

  reply	other threads:[~2015-08-17  2:01 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-07-24 15:20 [Qemu-devel] [PATCH 0/5] Wire up various EL2/EL3 address translation ops Peter Maydell
2015-07-24 15:20 ` [Qemu-devel] [PATCH 1/5] target-arm: there is no TTBR1 for 32-bit EL2 stage 1 translations Peter Maydell
2015-08-17  1:38   ` Edgar E. Iglesias
2015-07-24 15:21 ` [Qemu-devel] [PATCH 2/5] target-arm: Wire up AArch64 EL2 and EL3 address translation ops Peter Maydell
2015-08-17  1:51   ` Edgar E. Iglesias
2015-07-24 15:21 ` [Qemu-devel] [PATCH 3/5] target-arm: Add CP_ACCESS_TRAP_UNCATEGORIZED_EL2, 3 Peter Maydell
2015-08-17  1:52   ` Edgar E. Iglesias [this message]
2015-07-24 15:21 ` [Qemu-devel] [PATCH 4/5] target-arm: Enable the AArch32 ATS12NSO ops Peter Maydell
2015-08-17 13:31   ` Edgar E. Iglesias
2015-07-24 15:21 ` [Qemu-devel] [PATCH 5/5] target-arm: Implement AArch32 ATS1H* operations Peter Maydell
2015-08-17 13:36   ` Edgar E. Iglesias
2015-08-14 10:10 ` [Qemu-devel] [PATCH 0/5] Wire up various EL2/EL3 address translation ops Peter Maydell

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