From: Marek Vasut <marex@denx.de>
To: linux-mtd@lists.infradead.org
Cc: "Brian Norris" <computersforpeace@gmail.com>,
"Viet Nga Dao" <vndao@altera.com>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"Rafał Miłecki" <zajec5@gmail.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"David Woodhouse" <dwmw2@infradead.org>,
"Graham Moore" <grmoore@opensource.altera.com>
Subject: Re: [PATCH] [PATCH v4] mtd:spi-nor: Add Altera Quad SPI Driver
Date: Mon, 17 Aug 2015 19:53:23 +0200 [thread overview]
Message-ID: <201508171953.23955.marex@denx.de> (raw)
In-Reply-To: <20150817160338.GN60523@google.com>
On Monday, August 17, 2015 at 06:03:38 PM, Brian Norris wrote:
Hi!
[...]
> > Hi Brian,
> > It is really unfortunate that this controller is not able to read full
> > JEDEC ID. It only can provide 1 byte ID. I did discuss with IP
> > designer about this, but it is really unfortunate that they are not
> > able to fix that issue. Hence it requires software to make changes.
Thanks for CCing me, I assume this is a driver for that "altera_epcq_controller"
which you can synthesise into your FPGA, is that correct? Is there an Hard IP
variant of this controller in the public or is this purely Soft IP?
Also, I cannot find any documentation for this IP block even if I search through
Quartus/QSys, is there any proper documentation available anywhere?
[...]
Best regards,
Marek Vasut
WARNING: multiple messages have this Message-ID (diff)
From: Marek Vasut <marex-ynQEQJNshbs@public.gmane.org>
To: linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Cc: "Brian Norris"
<computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
"Viet Nga Dao" <vndao-EIB2kfCEclfQT0dZR+AlfA@public.gmane.org>,
"devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org"
<devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
"Rafał Miłecki" <zajec5-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
"linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org"
<linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
"David Woodhouse" <dwmw2-wEGCiKHe2LqWVfeAwA7xHQ@public.gmane.org>,
"Graham Moore"
<grmoore-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
Subject: Re: [PATCH] [PATCH v4] mtd:spi-nor: Add Altera Quad SPI Driver
Date: Mon, 17 Aug 2015 19:53:23 +0200 [thread overview]
Message-ID: <201508171953.23955.marex@denx.de> (raw)
In-Reply-To: <20150817160338.GN60523-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org>
On Monday, August 17, 2015 at 06:03:38 PM, Brian Norris wrote:
Hi!
[...]
> > Hi Brian,
> > It is really unfortunate that this controller is not able to read full
> > JEDEC ID. It only can provide 1 byte ID. I did discuss with IP
> > designer about this, but it is really unfortunate that they are not
> > able to fix that issue. Hence it requires software to make changes.
Thanks for CCing me, I assume this is a driver for that "altera_epcq_controller"
which you can synthesise into your FPGA, is that correct? Is there an Hard IP
variant of this controller in the public or is this purely Soft IP?
Also, I cannot find any documentation for this IP block even if I search through
Quartus/QSys, is there any proper documentation available anywhere?
[...]
Best regards,
Marek Vasut
--
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next prev parent reply other threads:[~2015-08-17 17:53 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-06-03 7:30 [PATCH] [PATCH v4] mtd:spi-nor: Add Altera Quad SPI Driver vndao
2015-06-03 7:30 ` vndao
2015-06-03 7:30 ` vndao
2015-07-24 18:37 ` Brian Norris
2015-07-27 7:10 ` Viet Nga Dao
2015-07-27 7:10 ` Viet Nga Dao
2015-08-17 16:03 ` Brian Norris
2015-08-17 16:03 ` Brian Norris
2015-08-17 17:53 ` Marek Vasut [this message]
2015-08-17 17:53 ` Marek Vasut
2015-08-18 1:24 ` Brian Norris
2015-08-18 1:24 ` Brian Norris
2015-08-18 1:32 ` Marek Vasut
2015-08-18 1:32 ` Marek Vasut
-- strict thread matches above, loose matches on Subject: below --
2015-08-20 7:33 Viet Nga Dao
2015-08-20 7:37 ` Viet Nga Dao
2015-08-20 7:37 ` Viet Nga Dao
2015-08-20 7:55 ` Marek Vasut
2015-08-20 8:06 ` Viet Nga Dao
2015-08-20 8:48 ` Marek Vasut
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