Re: [PATCH] drm/i915: Flush pipecontrol post-sync writes

From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>
Cc: intel-gfx@lists.freedesktop.org, stable@vger.kernel.org
Subject: Re: [PATCH] drm/i915: Flush pipecontrol post-sync writes
Date: Fri, 21 Aug 2015 18:21:16 +0300	[thread overview]
Message-ID: <20150821152116.GF5176@intel.com> (raw)
In-Reply-To: <1440169721-25861-1-git-send-email-chris@chris-wilson.co.uk>

On Fri, Aug 21, 2015 at 04:08:41PM +0100, Chris Wilson wrote:
> In order to flush the results from in-batch pipecontrol writes (used for
> example in glQuery) before declaring the batch complete (and so declaring
> the query results coherent), we need to set the FlushEnable bit in our
> flushing pipecontrol. The FlushEnable bit "waits until all previous
> writes of immediate data from post-sync circles are complete before
> executing the next command".
> 
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: stable@vger.kernel.org

Yeah makes as much sense as anything about pipecontrols.
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Though the spec makes me thing it would be even more appropriate if
we did the seqno write using a post-sync operation and followed it
with such a pipecontrol flush. But I've not actually played around
with this stuff, so can't say for sure.

Oh and we're also lacking DC flushes everywhere, in case someone
cares.

> ---
>  drivers/gpu/drm/i915/intel_lrc.c        | 1 +
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 2 ++
>  2 files changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 01cf0ca21990..e0c19d75b196 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1771,6 +1771,7 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
>  	if (flush_domains) {
>  		flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
>  		flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
> +		flags |= PIPE_CONTROL_FLUSH_ENABLE;
>  	}
>  
>  	if (invalidate_domains) {
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index c2392f6c4204..551af7399ca1 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -330,6 +330,7 @@ gen7_render_ring_flush(struct drm_i915_gem_request *req,
>  	if (flush_domains) {
>  		flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
>  		flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
> +		flags |= PIPE_CONTROL_FLUSH_ENABLE;
>  	}
>  	if (invalidate_domains) {
>  		flags |= PIPE_CONTROL_TLB_INVALIDATE;
> @@ -401,6 +402,7 @@ gen8_render_ring_flush(struct drm_i915_gem_request *req,
>  	if (flush_domains) {
>  		flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
>  		flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
> +		flags |= PIPE_CONTROL_FLUSH_ENABLE;
>  	}
>  	if (invalidate_domains) {
>  		flags |= PIPE_CONTROL_TLB_INVALIDATE;
> -- 
> 2.5.0
> 
> _______________________________________________
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-- 
Ville Syrjälä
Intel OTC
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