From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Chandra Konduru <chandra.konduru@intel.com>
Cc: daniel.vetter@intel.com, intel-gfx@lists.freedesktop.org,
ville.syrjala@intel.com
Subject: Re: [PATCH 02/15] drm/i915: In DBUF/WM calcs for 90/270, swap w & h
Date: Fri, 4 Sep 2015 11:31:23 +0300 [thread overview]
Message-ID: <20150904083123.GZ29811@intel.com> (raw)
In-Reply-To: <1440032556-9920-3-git-send-email-chandra.konduru@intel.com>
On Wed, Aug 19, 2015 at 06:02:23PM -0700, Chandra Konduru wrote:
> This patch swaps src width and height for dbuf/wm calculations
> when rotation is 90/270 as per hw requirements.
The spec is rather unclear about this. It only says:
"If plane 90 or 270 rotation is enabled, use the rotated width and
height in pixel rate calculations."
Although it does make sense based on the fact that the display
fetch will happen in the rotated direction.
I tried to reconcile some if this stuff in my head but when I went to
read the Yf/Ys tiling documentation I got even more confused. What it
says there is that a single cacheline always contains 4 rows of pixels,
but then in the next sentence it claims the aspect ratio will be 1:1
for 8,32,128 bpp, and 2:1 for 16,64 bpp. Those two things can't both be
true. Can someone tell me which one is true?
>
> Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 32 ++++++++++++++++++++++++++++----
> 1 file changed, 28 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index da3046f..c455946 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3193,6 +3193,8 @@ static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc,
> enum pipe pipe = intel_crtc->pipe;
> struct drm_plane *plane;
> struct drm_framebuffer *fb;
> + struct intel_plane_state *plane_state;
> + int src_w, src_h;
These can be moved to a narrower scope. plane_state could be const I
believe.
> int i = 1; /* Index for sprite planes start */
>
> p->active = intel_crtc->active;
> @@ -3201,6 +3203,7 @@ static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc,
> p->pixel_rate = skl_pipe_pixel_rate(intel_crtc->config);
>
> fb = crtc->primary->state->fb;
> + plane_state = to_intel_plane_state(crtc->primary->state);
> /* For planar: Bpp is for uv plane, y_Bpp is for y plane */
> if (fb) {
> p->plane[0].enabled = true;
> @@ -3215,8 +3218,22 @@ static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc,
> p->plane[0].y_bytes_per_pixel = 0;
> p->plane[0].tiling = DRM_FORMAT_MOD_NONE;
> }
> - p->plane[0].horiz_pixels = intel_crtc->config->pipe_src_w;
> - p->plane[0].vert_pixels = intel_crtc->config->pipe_src_h;
> +
> + if (drm_rect_width(&plane_state->src)) {
> + src_w = drm_rect_width(&plane_state->src) >> 16;
> + src_h = drm_rect_height(&plane_state->src) >> 16;
> + } else {
> + src_w = intel_crtc->config->pipe_src_w;
> + src_h = intel_crtc->config->pipe_src_h;
> + }
Are we still not having a consistent plane state all the time, or why is
this kludge needed?
> +
> + if (intel_rotation_90_or_270(crtc->primary->state->rotation)) {
> + p->plane[0].horiz_pixels = src_h;
> + p->plane[0].vert_pixels = src_w;
> + } else {
> + p->plane[0].horiz_pixels = src_w;
> + p->plane[0].vert_pixels = src_h;
> + }
> p->plane[0].rotation = crtc->primary->state->rotation;
>
> fb = crtc->cursor->state->fb;
> @@ -3750,8 +3767,15 @@ skl_update_sprite_wm(struct drm_plane *plane, struct drm_crtc *crtc,
>
> intel_plane->wm.enabled = enabled;
> intel_plane->wm.scaled = scaled;
> - intel_plane->wm.horiz_pixels = sprite_width;
> - intel_plane->wm.vert_pixels = sprite_height;
> +
> + if (intel_rotation_90_or_270(plane->state->rotation)) {
> + intel_plane->wm.horiz_pixels = sprite_height;
> + intel_plane->wm.vert_pixels = sprite_width;
> + } else {
> + intel_plane->wm.horiz_pixels = sprite_width;
> + intel_plane->wm.vert_pixels = sprite_height;
> + }
> +
> intel_plane->wm.tiling = DRM_FORMAT_MOD_NONE;
>
> /* For planar: Bpp is for UV plane, y_Bpp is for Y plane */
> --
> 1.7.9.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2015-09-04 8:31 UTC|newest]
Thread overview: 59+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-08-20 1:02 [PATCH 00/15] drm/i915: Adding NV12 for skylake display Chandra Konduru
2015-08-20 1:02 ` [PATCH 01/15] drm/i915: Allocate min dbuf blocks per bspec Chandra Konduru
2015-09-04 8:17 ` Ville Syrjälä
2015-08-20 1:02 ` [PATCH 02/15] drm/i915: In DBUF/WM calcs for 90/270, swap w & h Chandra Konduru
2015-09-04 8:31 ` Ville Syrjälä [this message]
2015-08-20 1:02 ` [PATCH 03/15] drm/i915: Add register definitions for NV12 support Chandra Konduru
2015-09-04 8:40 ` Ville Syrjälä
2015-08-20 1:02 ` [PATCH 04/15] drm/i915: Set scaler mode for NV12 Chandra Konduru
2015-09-04 8:53 ` Ville Syrjälä
2015-09-04 15:03 ` Daniel Vetter
2015-08-20 1:02 ` [PATCH 05/15] drm/i915: Stage scaler request for NV12 as src format Chandra Konduru
2015-09-04 10:17 ` Ville Syrjälä
2015-08-20 1:02 ` [PATCH 06/15] drm/i915: Update format_is_yuv() to include NV12 Chandra Konduru
2015-09-04 10:17 ` Ville Syrjälä
2015-08-20 1:02 ` [PATCH 07/15] drm/i915: Upscale scaler max scale for NV12 Chandra Konduru
2015-09-04 10:22 ` Ville Syrjälä
2015-08-20 1:02 ` [PATCH 08/15] drm/i915: Add NV12 as supported format for primary plane Chandra Konduru
2015-08-26 8:40 ` Daniel Vetter
2015-08-27 1:40 ` Konduru, Chandra
2015-08-20 1:02 ` [PATCH 09/15] drm/i915: Add NV12 as supported format for sprite plane Chandra Konduru
2015-09-04 10:28 ` Ville Syrjälä
2015-08-20 1:02 ` [PATCH 10/15] drm/i915: Add NV12 support to intel_framebuffer_init Chandra Konduru
2015-09-04 10:40 ` Ville Syrjälä
2015-08-20 1:02 ` [PATCH 11/15] drm/i915: Add NV12 to primary plane programming Chandra Konduru
2015-09-04 11:09 ` Ville Syrjälä
2015-09-04 15:06 ` Daniel Vetter
2015-09-05 1:10 ` Konduru, Chandra
2015-09-05 14:59 ` Ville Syrjälä
2015-09-08 23:30 ` Konduru, Chandra
2015-09-09 11:41 ` Ville Syrjälä
2015-09-09 17:12 ` Konduru, Chandra
2015-09-09 18:05 ` Ville Syrjälä
2015-09-09 20:10 ` Konduru, Chandra
2015-09-09 20:40 ` Ville Syrjälä
2015-09-09 21:09 ` Konduru, Chandra
2015-09-09 22:27 ` Ville Syrjälä
2015-09-09 23:31 ` Konduru, Chandra
2015-08-20 1:02 ` [PATCH 12/15] drm/i915: Add NV12 to sprite " Chandra Konduru
2015-08-20 1:02 ` [PATCH 13/15] drm/i915: Set initial phase & trip for NV12 scaler Chandra Konduru
2015-09-04 11:15 ` Ville Syrjälä
2015-08-20 1:02 ` [PATCH 14/15] drm/i915: skl nv12 workarounds Chandra Konduru
2015-08-26 8:42 ` Daniel Vetter
2015-08-27 1:44 ` Konduru, Chandra
2015-09-02 8:02 ` Daniel Vetter
2015-09-03 18:33 ` Konduru, Chandra
2015-09-04 7:40 ` Daniel Vetter
2015-09-05 2:09 ` Konduru, Chandra
2015-09-04 11:26 ` Ville Syrjälä
2015-09-05 1:28 ` Konduru, Chandra
2015-09-05 14:52 ` Ville Syrjälä
2015-09-08 23:51 ` Konduru, Chandra
2015-09-09 11:46 ` Ville Syrjälä
2015-09-09 17:20 ` Konduru, Chandra
2015-08-20 1:02 ` [PATCH 15/15] drm/i915: Add 90/270 rotation for NV12 format Chandra Konduru
2015-09-04 11:30 ` Ville Syrjälä
2015-09-05 1:38 ` Konduru, Chandra
2015-09-05 14:48 ` Ville Syrjälä
-- strict thread matches above, loose matches on Subject: below --
2015-09-05 2:32 [PATCH 00/15] drm/i915: Adding NV12 for skylake display Chandra Konduru
2015-09-05 2:32 ` [PATCH 02/15] drm/i915: In DBUF/WM calcs for 90/270, swap w & h Chandra Konduru
2015-09-29 17:46 ` Ville Syrjälä
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