From: Stephen Boyd <sboyd@codeaurora.org>
To: Jisheng Zhang <jszhang@marvell.com>
Cc: sebastian.hesselbarth@gmail.com, catalin.marinas@arm.com,
will.deacon@arm.com, mark.rutland@arm.com, robh+dt@kernel.org,
pawel.moll@arm.com, ijc+devicetree@hellion.org.uk,
galak@codeaurora.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH 2/5] clk: berlin: add common clk driver for newer SoCs
Date: Thu, 1 Oct 2015 15:38:36 -0700 [thread overview]
Message-ID: <20151001223836.GR19319@codeaurora.org> (raw)
In-Reply-To: <1442931156-5877-3-git-send-email-jszhang@marvell.com>
On 09/22, Jisheng Zhang wrote:
> +
> +static u8 clk_div[] = {1, 2, 4, 6, 8, 12, 1, 1};
> +
> +static unsigned long berlin_clk_recalc_rate(struct clk_hw *hw,
> + unsigned long parent_rate)
> +{
> + u32 val, divider;
> + struct berlin_clk *clk = to_berlin_clk(hw);
> +
> + val = readl_relaxed(clk->base);
> + if (val & CLKD3SWITCH)
> + divider = 3;
> + else {
> + if (val & CLKSWITCH) {
> + val >>= CLKSEL_SHIFT;
> + val &= CLKSEL_MASK;
> + divider = clk_div[val];
> + } else
> + divider = 1;
> + }
How about we drop the clk_div array and use code?
if (val & CLKSWITCH) {
val >>= CLKSEL_SHIFT;
val &= CLKSEL_MASK;
}
divider = 1
if (val < 6)
divider <<= val;
> +
> + return parent_rate / divider;
> +}
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
WARNING: multiple messages have this Message-ID (diff)
From: sboyd@codeaurora.org (Stephen Boyd)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 2/5] clk: berlin: add common clk driver for newer SoCs
Date: Thu, 1 Oct 2015 15:38:36 -0700 [thread overview]
Message-ID: <20151001223836.GR19319@codeaurora.org> (raw)
In-Reply-To: <1442931156-5877-3-git-send-email-jszhang@marvell.com>
On 09/22, Jisheng Zhang wrote:
> +
> +static u8 clk_div[] = {1, 2, 4, 6, 8, 12, 1, 1};
> +
> +static unsigned long berlin_clk_recalc_rate(struct clk_hw *hw,
> + unsigned long parent_rate)
> +{
> + u32 val, divider;
> + struct berlin_clk *clk = to_berlin_clk(hw);
> +
> + val = readl_relaxed(clk->base);
> + if (val & CLKD3SWITCH)
> + divider = 3;
> + else {
> + if (val & CLKSWITCH) {
> + val >>= CLKSEL_SHIFT;
> + val &= CLKSEL_MASK;
> + divider = clk_div[val];
> + } else
> + divider = 1;
> + }
How about we drop the clk_div array and use code?
if (val & CLKSWITCH) {
val >>= CLKSEL_SHIFT;
val &= CLKSEL_MASK;
}
divider = 1
if (val < 6)
divider <<= val;
> +
> + return parent_rate / divider;
> +}
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
next prev parent reply other threads:[~2015-10-01 22:38 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-09-22 14:12 [PATCH 0/5] Add Marvell berlin4ct clk support Jisheng Zhang
2015-09-22 14:12 ` Jisheng Zhang
2015-09-22 14:12 ` Jisheng Zhang
2015-09-22 14:12 ` [PATCH 1/5] clk: berlin: add common pll driver Jisheng Zhang
2015-09-22 14:12 ` Jisheng Zhang
2015-09-22 14:12 ` Jisheng Zhang
2015-10-01 22:32 ` Stephen Boyd
2015-10-01 22:32 ` Stephen Boyd
2015-10-08 10:52 ` Jisheng Zhang
2015-10-08 10:52 ` Jisheng Zhang
2015-10-08 10:52 ` Jisheng Zhang
2015-09-22 14:12 ` [PATCH 2/5] clk: berlin: add common clk driver for newer SoCs Jisheng Zhang
2015-09-22 14:12 ` Jisheng Zhang
2015-09-22 14:12 ` Jisheng Zhang
2015-10-01 22:38 ` Stephen Boyd [this message]
2015-10-01 22:38 ` Stephen Boyd
2015-09-22 14:12 ` [PATCH 3/5] clk: berlin: add clk support for berlin4ct Jisheng Zhang
2015-09-22 14:12 ` Jisheng Zhang
2015-09-22 14:12 ` Jisheng Zhang
2015-10-01 22:42 ` Stephen Boyd
2015-10-01 22:42 ` Stephen Boyd
2015-09-22 14:12 ` [PATCH 4/5] dt-bindings: add binding for marvell berlin4ct SoC Jisheng Zhang
2015-09-22 14:12 ` Jisheng Zhang
2015-09-22 14:12 ` Jisheng Zhang
2015-10-01 22:50 ` Stephen Boyd
2015-10-01 22:50 ` Stephen Boyd
2015-10-08 11:13 ` Jisheng Zhang
2015-10-08 11:13 ` Jisheng Zhang
2015-10-08 11:13 ` Jisheng Zhang
2015-09-22 14:12 ` [PATCH 5/5] arm64: dts: berlin4ct: add pll and clock nodes Jisheng Zhang
2015-09-22 14:12 ` Jisheng Zhang
2015-09-22 14:12 ` Jisheng Zhang
2015-09-23 1:55 ` [PATCH 0/5] Add Marvell berlin4ct clk support Jisheng Zhang
2015-09-23 1:55 ` Jisheng Zhang
2015-09-23 1:55 ` Jisheng Zhang
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20151001223836.GR19319@codeaurora.org \
--to=sboyd@codeaurora.org \
--cc=catalin.marinas@arm.com \
--cc=devicetree@vger.kernel.org \
--cc=galak@codeaurora.org \
--cc=ijc+devicetree@hellion.org.uk \
--cc=jszhang@marvell.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-clk@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=mark.rutland@arm.com \
--cc=pawel.moll@arm.com \
--cc=robh+dt@kernel.org \
--cc=sebastian.hesselbarth@gmail.com \
--cc=will.deacon@arm.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.