From: Beniamino Galvani <b.galvani@gmail.com>
To: Peter Crosthwaite <crosthwaitepeter@gmail.com>
Cc: Peter Maydell <peter.maydell@linaro.org>,
Rob Herring <rob.herring@linaro.org>,
Igor Mitsyanko <i.mitsyanko@gmail.com>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
Nathan Rossi <nathan@nathanrossi.com>,
Sai Pavan Boddu <saipava@xilinx.com>,
Richard Purdie <richard.purdie@linuxfoundation.org>,
Alistair Francis <alistair.francis@xilinx.com>,
John Snow <jsnow@redhat.com>, Guenter Roeck <linux@roeck-us.net>
Subject: Re: [Qemu-devel] QEMU+Linux ARMv7A current state
Date: Sun, 4 Oct 2015 21:56:57 +0200 [thread overview]
Message-ID: <20151004195627.GA17883@gmail.com> (raw)
In-Reply-To: <CAPokK=pD2cTb=4w1QtJA+CCTmjHL-NAvCXxAJNh5iB37GwacJA@mail.gmail.com>
On Sat, Oct 03, 2015 at 02:31:08PM -0700, Peter Crosthwaite wrote:
> QEMU cubieboard has no usable storage media, but the real hardware
> does have AHCI sata. I added sysbus-ahci at the right place but turns
> out the SATA controller has some custom power/clock (not really
> sure??) registers specific to this SoC. It sets/clears bits then polls
> them back expecting them to change to the other value asynchronously.
> The kernel device probe then times-out. So I subclassed sysbus-ahci
> and added the missing registers and forced the polled registers to the
> "I'm done" state. It works.
Cool, are you going to submit patches for this?
> I am using meta-sunxi Yocto-layer to build out the allwinner custom
> kernel/rootfs etc, and with the clock and Sata changes I get a boot.
> But when I change to the unedited kernel+dtb+rootfs I get stuck. RTC
> messages are around the point of failure which is not modelled in
> QEMU, so that is suspect.
I don't know, this needs some investigation; on my side a recent
multi_v7_defconfig kernel, unmodified sun4i-a10-cubieboard.dtb and a
rootfs built with buildroot mounted through NFS work just fine, with
the mentioned warnings regarding clk registers and also these:
Ignoring attempt to switch CPSR_A flag from non-secure world with SCR.AW bit clear
Ignoring attempt to switch CPSR_F flag from non-secure world with SCR.FW bit clear
which probably would be solved by setting the property 'has_el3' of
the CPU to false before realization.
Beniamino
next prev parent reply other threads:[~2015-10-04 19:57 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-10-03 21:31 [Qemu-devel] QEMU+Linux ARMv7A current state Peter Crosthwaite
2015-10-03 21:51 ` Peter Maydell
2015-10-03 22:14 ` Peter Crosthwaite
2015-10-03 23:19 ` Peter Crosthwaite
2015-10-04 10:42 ` Peter Maydell
2015-10-04 0:21 ` Guenter Roeck
2015-10-04 1:48 ` Peter Crosthwaite
2015-10-04 19:56 ` Beniamino Galvani [this message]
2015-10-04 21:11 ` Guenter Roeck
2015-10-04 21:38 ` Beniamino Galvani
2015-10-05 1:08 ` Guenter Roeck
2015-10-05 2:21 ` Peter Crosthwaite
2015-10-05 4:09 ` Guenter Roeck
2015-10-11 16:33 ` Peter Crosthwaite
2015-10-04 21:39 ` Peter Crosthwaite
2015-10-04 22:08 ` Peter Maydell
2015-10-11 16:37 ` Peter Crosthwaite
2015-10-05 15:13 ` John Snow
2015-10-05 20:44 ` Beniamino Galvani
2015-10-05 21:28 ` John Snow
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