From: Stephen Boyd <sboyd@codeaurora.org>
To: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Mike Turquette <mturquette@baylibre.com>,
Emilio Lopez <emilio@elopez.com.ar>,
linux-arm-kernel@lists.infradead.org,
Chen-Yu Tsai <wens@csie.org>, Hans de Goede <hdegoede@redhat.com>,
linux-clk@vger.kernel.org, linux-sunxi@googlegroups.com
Subject: Re: [PATCH v3 1/5] clk: Add a basic multiplier clock
Date: Mon, 5 Oct 2015 11:09:29 -0700 [thread overview]
Message-ID: <20151005180929.GB12338@codeaurora.org> (raw)
In-Reply-To: <20151005101932.GH2696@lukather>
On 10/05, Maxime Ripard wrote:
> Hi,
>
> On Fri, Oct 02, 2015 at 01:43:08PM -0700, Stephen Boyd wrote:
> > On 09/29, Maxime Ripard wrote:
> > > +
> > > + if (!val && mult->flags & CLK_MULTIPLIER_ZERO_BYPASS)
> > > + val = 1;
> > > +
> > > + return parent_rate * val;
> > > +}
> > > +
> > > +static bool __is_best_rate(unsigned long rate, unsigned long new,
> > > + unsigned long best, unsigned long flags)
> > > +{
> > > + if (flags & CLK_MULTIPLIER_ROUND_CLOSEST)
> >
> > Is the only difference in this function vs the divider one that
> > flag? Maybe we should make this function generic to the framework
> > and pass a flag indicating closest or not.
>
> Actually, the logic is also reversed.
>
> The divider driver will always try to find some rate that is higher
> than the one we already have, without going above than the one
> requested.
>
> Here, we're tring to be lower than the best rate, without going below
> the requested rate.
So then a tri-state flag that indicates, closest, less than,
greater than?
>
> >
> > > + unsigned long val;
> > > +
> > > + if (mult->lock)
> > > + spin_lock_irqsave(mult->lock, flags);
> >
> > This needs the same "trick" that we did in the generic clock
> > types to avoid sparse warnings.
>
> The __acquire call ?
Yes.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
WARNING: multiple messages have this Message-ID (diff)
From: sboyd@codeaurora.org (Stephen Boyd)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 1/5] clk: Add a basic multiplier clock
Date: Mon, 5 Oct 2015 11:09:29 -0700 [thread overview]
Message-ID: <20151005180929.GB12338@codeaurora.org> (raw)
In-Reply-To: <20151005101932.GH2696@lukather>
On 10/05, Maxime Ripard wrote:
> Hi,
>
> On Fri, Oct 02, 2015 at 01:43:08PM -0700, Stephen Boyd wrote:
> > On 09/29, Maxime Ripard wrote:
> > > +
> > > + if (!val && mult->flags & CLK_MULTIPLIER_ZERO_BYPASS)
> > > + val = 1;
> > > +
> > > + return parent_rate * val;
> > > +}
> > > +
> > > +static bool __is_best_rate(unsigned long rate, unsigned long new,
> > > + unsigned long best, unsigned long flags)
> > > +{
> > > + if (flags & CLK_MULTIPLIER_ROUND_CLOSEST)
> >
> > Is the only difference in this function vs the divider one that
> > flag? Maybe we should make this function generic to the framework
> > and pass a flag indicating closest or not.
>
> Actually, the logic is also reversed.
>
> The divider driver will always try to find some rate that is higher
> than the one we already have, without going above than the one
> requested.
>
> Here, we're tring to be lower than the best rate, without going below
> the requested rate.
So then a tri-state flag that indicates, closest, less than,
greater than?
>
> >
> > > + unsigned long val;
> > > +
> > > + if (mult->lock)
> > > + spin_lock_irqsave(mult->lock, flags);
> >
> > This needs the same "trick" that we did in the generic clock
> > types to avoid sparse warnings.
>
> The __acquire call ?
Yes.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
next prev parent reply other threads:[~2015-10-05 18:09 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-09-29 7:39 [PATCH v3 0/5] clk: sunxi: Add support for the Audio PLL Maxime Ripard
2015-09-29 7:39 ` Maxime Ripard
2015-09-29 7:39 ` [PATCH v3 1/5] clk: Add a basic multiplier clock Maxime Ripard
2015-09-29 7:39 ` Maxime Ripard
2015-10-02 20:43 ` Stephen Boyd
2015-10-02 20:43 ` Stephen Boyd
2015-10-05 10:19 ` Maxime Ripard
2015-10-05 10:19 ` Maxime Ripard
2015-10-05 18:09 ` Stephen Boyd [this message]
2015-10-05 18:09 ` Stephen Boyd
2015-10-07 11:04 ` Maxime Ripard
2015-10-07 11:04 ` Maxime Ripard
2015-10-07 19:17 ` Stephen Boyd
2015-10-07 19:17 ` Stephen Boyd
2015-09-29 7:39 ` [PATCH v3 2/5] clk: sunxi: Add a driver for the PLL2 Maxime Ripard
2015-09-29 7:39 ` Maxime Ripard
2015-09-29 7:39 ` [PATCH v3 3/5] clk: sunxi: pll2: Add A13 support Maxime Ripard
2015-09-29 7:39 ` Maxime Ripard
2015-09-29 7:39 ` [PATCH v3 4/5] clk: sunxi: codec clock support Maxime Ripard
2015-09-29 7:39 ` Maxime Ripard
2015-10-02 20:44 ` Stephen Boyd
2015-10-02 20:44 ` Stephen Boyd
2015-10-05 9:05 ` Maxime Ripard
2015-10-05 9:05 ` Maxime Ripard
2015-09-29 7:39 ` [PATCH v3 5/5] clk: sunxi: mod1 " Maxime Ripard
2015-09-29 7:39 ` Maxime Ripard
2015-10-02 20:45 ` Stephen Boyd
2015-10-02 20:45 ` Stephen Boyd
2015-10-05 9:44 ` Maxime Ripard
2015-10-05 9:44 ` Maxime Ripard
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