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From: "Sean O. Stalley" <sean.stalley-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
To: Yinghai Lu <yinghai-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Cc: "David Daney"
	<ddaney.cavm-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
	"Bjorn Helgaas"
	<bhelgaas-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org>,
	"Linux Kernel Mailing List"
	<linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
	"linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org"
	<linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
	"Michael S. Tsirkin"
	<mst-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>,
	"Rafał Miłecki" <zajec5-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
	linux-api-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	"Rajat Jain" <rajatxjain-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
	"gong.chen-VuQAYsv1563Yd54FQh9/CA@public.gmane.org"
	<gong.chen-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>,
	"David Daney"
	<david.daney-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org>
Subject: Re: [PATCH v4 0/5] PCI: Add support for PCI Enhanced Allocation "BARs"
Date: Mon, 5 Oct 2015 16:05:05 -0700	[thread overview]
Message-ID: <20151005230505.GD4821@sean.stalley.intel.com> (raw)
In-Reply-To: <CAE9FiQXT0ux42gQ+DhpVv2K=BR4jC++LmNdCSLiK4Wy0BhL=HQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>

On Fri, Oct 02, 2015 at 08:16:48PM -0700, Yinghai Lu wrote:
> On Fri, Oct 2, 2015 at 3:37 PM, David Daney <ddaney.cavm-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
> > From: David Daney <david.daney-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org>
> >
> > PCI Enhanced Allocation is a new method of allocating MMIO & IO
> > resources for PCI devices & bridges. It can be used instead
> > of the traditional PCI method of using BARs.
> >
> > EA entries are hardware-initialized to a fixed address.
> > Unlike BARs, regions described by EA are cannot be moved.
> > Because of this, only devices which are permanently connected to
> > the PCI bus can use EA. A removable PCI card must not use EA.
> >
> > The Enhanced Allocation ECN is publicly available here:
> > https://www.pcisig.com/specifications/conventional/ECN_Enhanced_Allocation_23_Oct_2014_Final.pdf
> 
> Looks like the EA will support more than just fixed address later.
> 
> "Enhanced Allocation is an optional Conventional PCI Capability that
> may be implemented by
> Functions to indicate fixed (non reprogrammable) I/O and memory ranges
> assigned to the
> Function, as well as supporting new resource “type” definitions and
> future extensibility to also
> support reprogrammable allocations."
> 
> so I would prefer to think more to make frame configurable to leave
> space for that.
> 
> Bjorn,
> 
> I wonder if we need to revive the add-on resource support patchset
> that i suggested couple years ago,
> so we can extend it to support EA features.
> 
> URL: https://lkml.org/lkml/2012/3/19/86
> 
> Thanks
> 
> Yinghai

This might be useful for fixed resources as well.

For some BEI values, EA allows for an arbitrary number of EA entries.
For PF & VF resource ranges, it allows 2 ranges.
(one below the 4GB boundry, and one above).
I don't think the current pci_dev struct can handle that many resources.

-Sean

WARNING: multiple messages have this Message-ID (diff)
From: "Sean O. Stalley" <sean.stalley@intel.com>
To: Yinghai Lu <yinghai@kernel.org>
Cc: "David Daney" <ddaney.cavm@gmail.com>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Linux Kernel Mailing List" <linux-kernel@vger.kernel.org>,
	"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
	"Michael S. Tsirkin" <mst@redhat.com>,
	"Rafał Miłecki" <zajec5@gmail.com>,
	linux-api@vger.kernel.org, "Rajat Jain" <rajatxjain@gmail.com>,
	"gong.chen@linux.intel.com" <gong.chen@linux.intel.com>,
	"David Daney" <david.daney@cavium.com>
Subject: Re: [PATCH v4 0/5] PCI: Add support for PCI Enhanced Allocation "BARs"
Date: Mon, 5 Oct 2015 16:05:05 -0700	[thread overview]
Message-ID: <20151005230505.GD4821@sean.stalley.intel.com> (raw)
In-Reply-To: <CAE9FiQXT0ux42gQ+DhpVv2K=BR4jC++LmNdCSLiK4Wy0BhL=HQ@mail.gmail.com>

On Fri, Oct 02, 2015 at 08:16:48PM -0700, Yinghai Lu wrote:
> On Fri, Oct 2, 2015 at 3:37 PM, David Daney <ddaney.cavm@gmail.com> wrote:
> > From: David Daney <david.daney@cavium.com>
> >
> > PCI Enhanced Allocation is a new method of allocating MMIO & IO
> > resources for PCI devices & bridges. It can be used instead
> > of the traditional PCI method of using BARs.
> >
> > EA entries are hardware-initialized to a fixed address.
> > Unlike BARs, regions described by EA are cannot be moved.
> > Because of this, only devices which are permanently connected to
> > the PCI bus can use EA. A removable PCI card must not use EA.
> >
> > The Enhanced Allocation ECN is publicly available here:
> > https://www.pcisig.com/specifications/conventional/ECN_Enhanced_Allocation_23_Oct_2014_Final.pdf
> 
> Looks like the EA will support more than just fixed address later.
> 
> "Enhanced Allocation is an optional Conventional PCI Capability that
> may be implemented by
> Functions to indicate fixed (non reprogrammable) I/O and memory ranges
> assigned to the
> Function, as well as supporting new resource “type” definitions and
> future extensibility to also
> support reprogrammable allocations."
> 
> so I would prefer to think more to make frame configurable to leave
> space for that.
> 
> Bjorn,
> 
> I wonder if we need to revive the add-on resource support patchset
> that i suggested couple years ago,
> so we can extend it to support EA features.
> 
> URL: https://lkml.org/lkml/2012/3/19/86
> 
> Thanks
> 
> Yinghai

This might be useful for fixed resources as well.

For some BEI values, EA allows for an arbitrary number of EA entries.
For PF & VF resource ranges, it allows 2 ranges.
(one below the 4GB boundry, and one above).
I don't think the current pci_dev struct can handle that many resources.

-Sean

  parent reply	other threads:[~2015-10-05 23:05 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-10-02 22:37 [PATCH v4 0/5] PCI: Add support for PCI Enhanced Allocation "BARs" David Daney
2015-10-02 22:37 ` [PATCH v4 1/5] PCI: Add Enhanced Allocation register entries David Daney
2015-10-02 22:37 ` [PATCH v4 2/5] PCI: Add support for Enhanced Allocation devices David Daney
2015-10-02 22:37 ` [PATCH v4 4/5] PCI: Handle Enhanced Allocation (EA) capability for SRIOV devices David Daney
2015-10-02 22:37 ` [PATCH v4 5/5] PCI: Handle Enhanced Allocation (EA) capability for bridges David Daney
     [not found]   ` <1443825476-26880-6-git-send-email-ddaney.cavm-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2015-10-05 22:54     ` Sean O. Stalley
2015-10-05 22:54       ` Sean O. Stalley
2015-10-05 23:01       ` David Daney
     [not found] ` <1443825476-26880-1-git-send-email-ddaney.cavm-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2015-10-02 22:37   ` [PATCH v4 3/5] PCI: Handle IORESOURCE_PCI_FIXED when sizing and assigning resources David Daney
2015-10-02 22:37     ` David Daney
2015-10-02 23:14     ` Yinghai Lu
2015-10-02 23:38       ` David Daney
2015-10-03  3:00         ` Yinghai Lu
2015-10-05 22:44           ` Sean O. Stalley
     [not found]     ` <1443825476-26880-4-git-send-email-ddaney.cavm-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2015-10-05 22:23       ` Sean O. Stalley
2015-10-05 22:23         ` Sean O. Stalley
     [not found]         ` <20151005222351.GA4821-KQ5zpJUXklQTH34CoL1+91DQ4js95KgL@public.gmane.org>
2015-10-06 20:58           ` David Daney
2015-10-06 20:58             ` David Daney
2015-10-02 23:47   ` [PATCH v4 0/5] PCI: Add support for PCI Enhanced Allocation "BARs" Sean O. Stalley
2015-10-02 23:47     ` Sean O. Stalley
2015-10-03  3:16   ` Yinghai Lu
2015-10-03  3:16     ` Yinghai Lu
     [not found]     ` <CAE9FiQXT0ux42gQ+DhpVv2K=BR4jC++LmNdCSLiK4Wy0BhL=HQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2015-10-05 16:49       ` David Daney
2015-10-05 16:49         ` David Daney
2015-10-05 23:05       ` Sean O. Stalley [this message]
2015-10-05 23:05         ` Sean O. Stalley
2015-10-06  1:17         ` David Daney
2015-10-06 15:47           ` Sean O. Stalley
2015-10-06 15:47             ` Sean O. Stalley

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