From: Stephen Boyd <sboyd@codeaurora.org>
To: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Cc: Maxime Coquelin <maxime.coquelin@st.com>,
Michael Turquette <mturquette@baylibre.com>,
Peter Griffin <peter.griffin@linaro.org>,
Pankaj Dev <pankaj.dev@st.com>,
Olivier Bideau <olivier.bideau@st.com>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Fabian Frederick <fabf@skynet.be>,
Rob Herring <robh+dt@kernel.org>, Pawel Moll <pawel.moll@arm.com>,
Mark Rutland <mark.rutland@arm.com>,
Ian Campbell <ijc+devicetree@hellion.org.uk>,
Kumar Gala <galak@codeaurora.org>,
Srinivas Kandagatla <srinivas.kandagatla@gmail.com>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, kernel@stlinux.com,
linux-clk@vger.kernel.org
Subject: Re: [PATCH v4 2/4] drivers: clk: st: PLL rate change implementation for DVFS
Date: Wed, 7 Oct 2015 12:14:59 -0700 [thread overview]
Message-ID: <20151007191459.GB12345@codeaurora.org> (raw)
In-Reply-To: <1444208939-10233-3-git-send-email-gabriel.fernandez@linaro.org>
On 10/07, Gabriel Fernandez wrote:
> Change A9 PLL rate, as per requirement from the cpufreq framework,
> for DVFS. For rate change, the A9 clock needs to be temporarily sourced
> from PLL external to A9 and then sourced back to A9-PLL
>
> Signed-off-by: Pankaj Dev <pankaj.dev@st.com>
> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
> ---
Applied to clk-next
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
WARNING: multiple messages have this Message-ID (diff)
From: sboyd@codeaurora.org (Stephen Boyd)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v4 2/4] drivers: clk: st: PLL rate change implementation for DVFS
Date: Wed, 7 Oct 2015 12:14:59 -0700 [thread overview]
Message-ID: <20151007191459.GB12345@codeaurora.org> (raw)
In-Reply-To: <1444208939-10233-3-git-send-email-gabriel.fernandez@linaro.org>
On 10/07, Gabriel Fernandez wrote:
> Change A9 PLL rate, as per requirement from the cpufreq framework,
> for DVFS. For rate change, the A9 clock needs to be temporarily sourced
> from PLL external to A9 and then sourced back to A9-PLL
>
> Signed-off-by: Pankaj Dev <pankaj.dev@st.com>
> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
> ---
Applied to clk-next
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
next prev parent reply other threads:[~2015-10-07 19:14 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-10-07 9:08 [PATCH v4 0/4] ST PLL improvement Gabriel Fernandez
2015-10-07 9:08 ` Gabriel Fernandez
2015-10-07 9:08 ` [PATCH v4 1/4] drivers: clk: st: Support for enable/disable in Clockgen PLLs Gabriel Fernandez
2015-10-07 9:08 ` Gabriel Fernandez
2015-10-07 9:08 ` Gabriel Fernandez
2015-10-07 19:14 ` Stephen Boyd
2015-10-07 19:14 ` Stephen Boyd
2015-10-07 9:08 ` [PATCH v4 2/4] drivers: clk: st: PLL rate change implementation for DVFS Gabriel Fernandez
2015-10-07 9:08 ` Gabriel Fernandez
2015-10-07 19:14 ` Stephen Boyd [this message]
2015-10-07 19:14 ` Stephen Boyd
2015-10-07 9:08 ` [PATCH v4 3/4] drivers: clk: st: Correct the pll-type for A9 for stih418 Gabriel Fernandez
2015-10-07 9:08 ` Gabriel Fernandez
2015-10-07 19:15 ` Stephen Boyd
2015-10-07 19:15 ` Stephen Boyd
2015-10-07 9:08 ` [PATCH v4 4/4] ARM: STi: DT: Add support for stih418 A9 pll Gabriel Fernandez
2015-10-07 9:08 ` Gabriel Fernandez
2015-10-07 9:08 ` Gabriel Fernandez
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