Re: Re: Re: Re: Re: [PATCH v3] arm: Adding support for atomic half word exchange

Re: Re: Re: Re: Re: [PATCH v3] arm: Adding support for atomic half word exchange

[Sarbojit Ganguly]

[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset=windows-1252, Size: 3956 bytes --]

Hello Russell,

Please have a look at this patch, please let me know if any modification is required.
I have also submitted the same in your patch system.

v2 -> v3: Removed the comment related to Qspinlock, changed !defined to #ifndef.
v1 -> v2: Extended the guard code to cover the byte exchange case as
well following opinion of Will Deacon. Checkpatch has been run and issues were
taken care of.

Since support for half-word atomic exchange was not there and Qspinlock on ARM
requires it, modified __xchg() to add support for that as well. ARMv6 and lower
does not support ldrex{b,h} so, added a guard code to prevent build breaks.

Signed-off-by: Sarbojit Ganguly <ganguly.s@samsung.com>
---
 arch/arm/include/asm/cmpxchg.h | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/include/asm/cmpxchg.h b/arch/arm/include/asm/cmpxchg.h
index 916a274..97882f9 100644
--- a/arch/arm/include/asm/cmpxchg.h
+++ b/arch/arm/include/asm/cmpxchg.h
@@ -39,6 +39,7 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size
 
 	switch (size) {
 #if __LINUX_ARM_ARCH__ >= 6
+#ifndef CONFIG_CPU_V6 /* MIN ARCH >= V6K */
 	case 1:
 		asm volatile("@	__xchg1\n"
 		"1:	ldrexb	%0, [%3]\n"
@@ -49,6 +50,17 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size
 			: "r" (x), "r" (ptr)
 			: "memory", "cc");
 		break;
+	case 2:
+		asm volatile("@	__xchg2\n"
+		"1:	ldrexh	%0, [%3]\n"
+		"	strexh	%1, %2, [%3]\n"
+		"	teq	%1, #0\n"
+		"	bne	1b"
+			: "=&r" (ret), "=&r" (tmp)
+			: "r" (x), "r" (ptr)
+			: "memory", "cc");
+		break;
+#endif
 	case 4:
 		asm volatile("@	__xchg4\n"
 		"1:	ldrex	%0, [%3]\n"
-- 
1.9.1


Regards,
Sarbojit

------- Original Message -------
Sender : Will Deacon<will.deacon@arm.com>
Date : Oct 06, 2015 20:24 (GMT+05:30)
Title : Re: Re: Re: Re: [PATCH v3] arm: Adding support for atomic half word exchange

On Tue, Oct 06, 2015 at 08:03:02AM +0000, Sarbojit Ganguly wrote:
> Here is the version 3 of the patch correcting earlier issues.

This looks good to me now:

  Acked-by: Will Deacon 

> v2 -> v3 : Removed the comment related to Qspinlock, changed !defined to
> #ifndef.
> v1 -> v2 : Extended the guard code to cover the byte exchange case as 
> well following opinion of Will Deacon.
> Checkpatch has been run and issues were taken care of.

The part of your text up until here doesn't belong in the commit message.
You'll also need to send this to Russell's patch system.

Will

> Since support for half-word atomic exchange was not there and Qspinlock
> on ARM requires it, modified __xchg() to add support for that as well.
> ARMv6 and lower does not support ldrex{b,h} so, added a guard code
> to prevent build breaks.
> 
> Signed-off-by: Sarbojit Ganguly 
> ---
>  arch/arm/include/asm/cmpxchg.h | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/arch/arm/include/asm/cmpxchg.h b/arch/arm/include/asm/cmpxchg.h
> index 916a274..c6436c1 100644
> --- a/arch/arm/include/asm/cmpxchg.h
> +++ b/arch/arm/include/asm/cmpxchg.h
> @@ -39,6 +39,7 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size
>  
>   switch (size) {
>  #if __LINUX_ARM_ARCH__ >= 6
> +#ifndef CONFIG_CPU_V6 /* MIN ARCH >= V6K */
>   case 1:
>   asm volatile("@ __xchg1\n"
>   "1: ldrexb %0, [%3]\n"
> @@ -49,6 +50,17 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size
>   : "r" (x), "r" (ptr)
>   : "memory", "cc");
>   break;
> + case 2:
> + asm volatile("@ __xchg2\n"
> + "1: ldrexh %0, [%3]\n"
> + " strexh %1, %2, [%3]\n"
> + " teq %1, #0\n"
> + " bne 1b"
> + : "=&r" (ret), "=&r" (tmp)
> + : "r" (x), "r" (ptr)
> + : "memory", "cc");
> + break;
> +#endif
>   case 4:
>   asm volatile("@ __xchg4\n"
>   "1: ldrex %0, [%3]\n"
> -- 
> 1.9.1
ÿôèº{.nÇ+‰·Ÿ®‰­†+%ŠËÿ±éݶ\x17¥Šwÿº{.nÇ+‰·¥Š{±þG«éÿŠ{ayº\x1dʇڙë,j\a­¢f£¢·hšïêÿ‘êçz_è®\x03(­éšŽŠÝ¢j"ú\x1a¶^[m§ÿÿ¾\a«þG«éÿ¢¸?™¨è­Ú&£ø§~á¶iO•æ¬z·švØ^\x14\x04\x1a¶^[m§ÿÿÃ\fÿ¶ìÿ¢¸?–I¥

[PATCH v3] arm: Adding support for atomic half word exchange

[Will Deacon]

On Wed, Oct 07, 2015 at 02:36:41PM +0000, Sarbojit Ganguly wrote:
> Please have a look at this patch, please let me know if any modification
> is required.
> I have also submitted the same in your patch system.

There are some problems with the version in the patch system[1]:

  (1) You still have the changelog in the commit message (I asked you to
      remove this last time).

  (2) The commit message isn't line-wrapper appropriately

  (3) Your Signed-off-by line is truncated

The patch system does actually support git, so you can add:

  KernelVersion: 4.3-rc4

or whatever kernel you based your patch on somewhere after your SoB but
before the diff and then mail it to patchesATarm.linux.org.uk. You
probably also want to move the current patch to "superseded" so Russell
doesn't end up with two copies.

Will

[1] http://www.arm.linux.org.uk/developer/patches/viewpatch.php?id=8442/1

Re: Re: Re: Re: Re: [PATCH v3] arm: Adding support for atomic half word exchange

[Will Deacon]

On Wed, Oct 07, 2015 at 02:36:41PM +0000, Sarbojit Ganguly wrote:
> Please have a look at this patch, please let me know if any modification
> is required.
> I have also submitted the same in your patch system.

There are some problems with the version in the patch system[1]:

  (1) You still have the changelog in the commit message (I asked you to
      remove this last time).

  (2) The commit message isn't line-wrapper appropriately

  (3) Your Signed-off-by line is truncated

The patch system does actually support git, so you can add:

  KernelVersion: 4.3-rc4

or whatever kernel you based your patch on somewhere after your SoB but
before the diff and then mail it to patchesATarm.linux.org.uk. You
probably also want to move the current patch to "superseded" so Russell
doesn't end up with two copies.

Will

[1] http://www.arm.linux.org.uk/developer/patches/viewpatch.php?id=8442/1

[PATCH v3] arm: Adding support for atomic half word exchange

[Sarbojit Ganguly]

[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset=windows-1252, Size: 2907 bytes --]

Hello Will,

Thank you so much for your patience. My sincere apologies with the issues with
formatting. I have taken care of them and hope now things are ok.

- Included patchesATarm.linux.org.uk.
- Removed the changelog from commit message.
- Moved the patch to "superseded" in patch system.
- Corrected the truncated Signed-off line.

KernelVersion: 4.3-rc4

Since support for half-word atomic exchange was not there and Qspinlock on ARM
requires it, modified __xchg() to add support for that as well. ARMv6 and lower
does not support ldrex{b,h} so, added a guard code to prevent build breaks.

Signed-off-by: Sarbojit Ganguly <ganguly.s@samsung.com>
---
 arch/arm/include/asm/cmpxchg.h | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/include/asm/cmpxchg.h b/arch/arm/include/asm/cmpxchg.h
index 916a274..97882f9 100644
--- a/arch/arm/include/asm/cmpxchg.h
+++ b/arch/arm/include/asm/cmpxchg.h
@@ -39,6 +39,7 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size
 
 	switch (size) {
 #if __LINUX_ARM_ARCH__ >= 6
+#ifndef CONFIG_CPU_V6 /* MIN ARCH >= V6K */
 	case 1:
 		asm volatile("@	__xchg1\n"
 		"1:	ldrexb	%0, [%3]\n"
@@ -49,6 +50,17 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size
 			: "r" (x), "r" (ptr)
 			: "memory", "cc");
 		break;
+	case 2:
+		asm volatile("@	__xchg2\n"
+		"1:	ldrexh	%0, [%3]\n"
+		"	strexh	%1, %2, [%3]\n"
+		"	teq	%1, #0\n"
+		"	bne	1b"
+			: "=&r" (ret), "=&r" (tmp)
+			: "r" (x), "r" (ptr)
+			: "memory", "cc");
+		break;
+#endif
 	case 4:
 		asm volatile("@	__xchg4\n"
 		"1:	ldrex	%0, [%3]\n"
-- 
1.9.1

Sarbojit

------- Original Message -------
Sender : Will Deacon<will.deacon@arm.com>
Date : Oct 08, 2015 22:26 (GMT+05:30)
Title : Re: Re: Re: Re: Re: [PATCH v3] arm: Adding support for atomic half word exchange

On Wed, Oct 07, 2015 at 02:36:41PM +0000, Sarbojit Ganguly wrote:
> Please have a look at this patch, please let me know if any modification
> is required.
> I have also submitted the same in your patch system.

There are some problems with the version in the patch system[1]:

  (1) You still have the changelog in the commit message (I asked you to
      remove this last time).

  (2) The commit message isn't line-wrapper appropriately

  (3) Your Signed-off-by line is truncated

The patch system does actually support git, so you can add:

  KernelVersion: 4.3-rc4

or whatever kernel you based your patch on somewhere after your SoB but
before the diff and then mail it to patchesATarm.linux.org.uk. You
probably also want to move the current patch to "superseded" so Russell
doesn't end up with two copies.

Will

[1] http://www.arm.linux.org.uk/developer/patches/viewpatch.php?id=8442/1ÿôèº{.nÇ+‰·Ÿ®‰­†+%ŠËÿ±éݶ\x17¥Šwÿº{.nÇ+‰·¥Š{±þG«éÿŠ{ayº\x1dʇڙë,j\a­¢f£¢·hšïêÿ‘êçz_è®\x03(­éšŽŠÝ¢j"ú\x1a¶^[m§ÿÿ¾\a«þG«éÿ¢¸?™¨è­Ú&£ø§~á¶iO•æ¬z·švØ^\x14\x04\x1a¶^[m§ÿÿÃ\fÿ¶ìÿ¢¸?–I¥

[PATCH v3] arm: Adding support for atomic half word exchange

[Sarbojit Ganguly]

Hello Will,

Thank you so much for your patience. My sincere apologies with the issues with
formatting. I have taken care of them and hope now things are ok.

- Included patchesATarm.linux.org.uk.
- Removed the changelog from commit message.
- Moved the patch to "superseded" in patch system.
- Corrected the truncated Signed-off line.

KernelVersion: 4.3-rc4

Since support for half-word atomic exchange was not there and Qspinlock on ARM
requires it, modified __xchg() to add support for that as well. ARMv6 and lower
does not support ldrex{b,h} so, added a guard code to prevent build breaks.

Signed-off-by: Sarbojit Ganguly <ganguly.s@samsung.com>
---
 arch/arm/include/asm/cmpxchg.h | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/include/asm/cmpxchg.h b/arch/arm/include/asm/cmpxchg.h
index 916a274..97882f9 100644
--- a/arch/arm/include/asm/cmpxchg.h
+++ b/arch/arm/include/asm/cmpxchg.h
@@ -39,6 +39,7 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size
 
 	switch (size) {
 #if __LINUX_ARM_ARCH__ >= 6
+#ifndef CONFIG_CPU_V6 /* MIN ARCH >= V6K */
 	case 1:
 		asm volatile("@	__xchg1\n"
 		"1:	ldrexb	%0, [%3]\n"
@@ -49,6 +50,17 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size
 			: "r" (x), "r" (ptr)
 			: "memory", "cc");
 		break;
+	case 2:
+		asm volatile("@	__xchg2\n"
+		"1:	ldrexh	%0, [%3]\n"
+		"	strexh	%1, %2, [%3]\n"
+		"	teq	%1, #0\n"
+		"	bne	1b"
+			: "=&r" (ret), "=&r" (tmp)
+			: "r" (x), "r" (ptr)
+			: "memory", "cc");
+		break;
+#endif
 	case 4:
 		asm volatile("@	__xchg4\n"
 		"1:	ldrex	%0, [%3]\n"
-- 
1.9.1

Sarbojit

------- Original Message -------
Sender : Will Deacon<will.deacon@arm.com>
Date : Oct 08, 2015 22:26 (GMT+05:30)
Title : Re: Re: Re: Re: Re: [PATCH v3] arm: Adding support for atomic half word exchange

On Wed, Oct 07, 2015 at 02:36:41PM +0000, Sarbojit Ganguly wrote:
> Please have a look at this patch, please let me know if any modification
> is required.
> I have also submitted the same in your patch system.

There are some problems with the version in the patch system[1]:

  (1) You still have the changelog in the commit message (I asked you to
      remove this last time).

  (2) The commit message isn't line-wrapper appropriately

  (3) Your Signed-off-by line is truncated

The patch system does actually support git, so you can add:

  KernelVersion: 4.3-rc4

or whatever kernel you based your patch on somewhere after your SoB but
before the diff and then mail it to patchesATarm.linux.org.uk. You
probably also want to move the current patch to "superseded" so Russell
doesn't end up with two copies.

Will

[1] http://www.arm.linux.org.uk/developer/patches/viewpatch.php?id=8442/1

[PATCH v3] arm: Adding support for atomic half word exchange

[Russell King - ARM Linux]

On Fri, Oct 09, 2015 at 11:10:02AM +0000, Sarbojit Ganguly wrote:
> Hello Will,
> 
> Thank you so much for your patience. My sincere apologies with the issues with
> formatting. I have taken care of them and hope now things are ok.
> 
> - Included patchesATarm.linux.org.uk.
> - Removed the changelog from commit message.
> - Moved the patch to "superseded" in patch system.
> - Corrected the truncated Signed-off line.
> 
> KernelVersion: 4.3-rc4
> 
> Since support for half-word atomic exchange was not there and Qspinlock on ARM
> requires it, modified __xchg() to add support for that as well. ARMv6 and lower
> does not support ldrex{b,h} so, added a guard code to prevent build breaks.
> 
> Signed-off-by: Sarbojit Ganguly <ganguly.s@samsung.com>
> ---

The commit message is everything above the "---" line.  It starts
with the subject line, a blank line, and then "Hello Will,".

I'll fix up the commit message this time, but please take note for
future patches.

You're also the first one to send a patch where the body _inside_ the
base64 container has CRLF line endings...

>  arch/arm/include/asm/cmpxchg.h | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/arch/arm/include/asm/cmpxchg.h b/arch/arm/include/asm/cmpxchg.h
> index 916a274..97882f9 100644
> --- a/arch/arm/include/asm/cmpxchg.h
> +++ b/arch/arm/include/asm/cmpxchg.h
> @@ -39,6 +39,7 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size
>  
>  	switch (size) {
>  #if __LINUX_ARM_ARCH__ >= 6
> +#ifndef CONFIG_CPU_V6 /* MIN ARCH >= V6K */
>  	case 1:
>  		asm volatile("@	__xchg1\n"
>  		"1:	ldrexb	%0, [%3]\n"
> @@ -49,6 +50,17 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size
>  			: "r" (x), "r" (ptr)
>  			: "memory", "cc");
>  		break;
> +	case 2:
> +		asm volatile("@	__xchg2\n"
> +		"1:	ldrexh	%0, [%3]\n"
> +		"	strexh	%1, %2, [%3]\n"
> +		"	teq	%1, #0\n"
> +		"	bne	1b"
> +			: "=&r" (ret), "=&r" (tmp)
> +			: "r" (x), "r" (ptr)
> +			: "memory", "cc");
> +		break;
> +#endif
>  	case 4:
>  		asm volatile("@	__xchg4\n"
>  		"1:	ldrex	%0, [%3]\n"
> -- 
> 1.9.1
> 
> Sarbojit
> 
> ------- Original Message -------
> Sender : Will Deacon<will.deacon@arm.com>
> Date : Oct 08, 2015 22:26 (GMT+05:30)
> Title : Re: Re: Re: Re: Re: [PATCH v3] arm: Adding support for atomic half word exchange
> 
> On Wed, Oct 07, 2015 at 02:36:41PM +0000, Sarbojit Ganguly wrote:
> > Please have a look at this patch, please let me know if any modification
> > is required.
> > I have also submitted the same in your patch system.
> 
> There are some problems with the version in the patch system[1]:
> 
>   (1) You still have the changelog in the commit message (I asked you to
>       remove this last time).
> 
>   (2) The commit message isn't line-wrapper appropriately
> 
>   (3) Your Signed-off-by line is truncated
> 
> The patch system does actually support git, so you can add:
> 
>   KernelVersion: 4.3-rc4
> 
> or whatever kernel you based your patch on somewhere after your SoB but
> before the diff and then mail it to patchesATarm.linux.org.uk. You
> probably also want to move the current patch to "superseded" so Russell
> doesn't end up with two copies.
> 
> Will
> 
> [1] http://www.arm.linux.org.uk/developer/patches/viewpatch.php?id=8442/1

-- 
FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up
according to speedtest.net.

Re: [PATCH v3] arm: Adding support for atomic half word exchange

[Russell King - ARM Linux]

On Fri, Oct 09, 2015 at 11:10:02AM +0000, Sarbojit Ganguly wrote:
> Hello Will,
> 
> Thank you so much for your patience. My sincere apologies with the issues with
> formatting. I have taken care of them and hope now things are ok.
> 
> - Included patchesATarm.linux.org.uk.
> - Removed the changelog from commit message.
> - Moved the patch to "superseded" in patch system.
> - Corrected the truncated Signed-off line.
> 
> KernelVersion: 4.3-rc4
> 
> Since support for half-word atomic exchange was not there and Qspinlock on ARM
> requires it, modified __xchg() to add support for that as well. ARMv6 and lower
> does not support ldrex{b,h} so, added a guard code to prevent build breaks.
> 
> Signed-off-by: Sarbojit Ganguly <ganguly.s@samsung.com>
> ---

The commit message is everything above the "---" line.  It starts
with the subject line, a blank line, and then "Hello Will,".

I'll fix up the commit message this time, but please take note for
future patches.

You're also the first one to send a patch where the body _inside_ the
base64 container has CRLF line endings...

>  arch/arm/include/asm/cmpxchg.h | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/arch/arm/include/asm/cmpxchg.h b/arch/arm/include/asm/cmpxchg.h
> index 916a274..97882f9 100644
> --- a/arch/arm/include/asm/cmpxchg.h
> +++ b/arch/arm/include/asm/cmpxchg.h
> @@ -39,6 +39,7 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size
>  
>  	switch (size) {
>  #if __LINUX_ARM_ARCH__ >= 6
> +#ifndef CONFIG_CPU_V6 /* MIN ARCH >= V6K */
>  	case 1:
>  		asm volatile("@	__xchg1\n"
>  		"1:	ldrexb	%0, [%3]\n"
> @@ -49,6 +50,17 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size
>  			: "r" (x), "r" (ptr)
>  			: "memory", "cc");
>  		break;
> +	case 2:
> +		asm volatile("@	__xchg2\n"
> +		"1:	ldrexh	%0, [%3]\n"
> +		"	strexh	%1, %2, [%3]\n"
> +		"	teq	%1, #0\n"
> +		"	bne	1b"
> +			: "=&r" (ret), "=&r" (tmp)
> +			: "r" (x), "r" (ptr)
> +			: "memory", "cc");
> +		break;
> +#endif
>  	case 4:
>  		asm volatile("@	__xchg4\n"
>  		"1:	ldrex	%0, [%3]\n"
> -- 
> 1.9.1
> 
> Sarbojit
> 
> ------- Original Message -------
> Sender : Will Deacon<will.deacon@arm.com>
> Date : Oct 08, 2015 22:26 (GMT+05:30)
> Title : Re: Re: Re: Re: Re: [PATCH v3] arm: Adding support for atomic half word exchange
> 
> On Wed, Oct 07, 2015 at 02:36:41PM +0000, Sarbojit Ganguly wrote:
> > Please have a look at this patch, please let me know if any modification
> > is required.
> > I have also submitted the same in your patch system.
> 
> There are some problems with the version in the patch system[1]:
> 
>   (1) You still have the changelog in the commit message (I asked you to
>       remove this last time).
> 
>   (2) The commit message isn't line-wrapper appropriately
> 
>   (3) Your Signed-off-by line is truncated
> 
> The patch system does actually support git, so you can add:
> 
>   KernelVersion: 4.3-rc4
> 
> or whatever kernel you based your patch on somewhere after your SoB but
> before the diff and then mail it to patchesATarm.linux.org.uk. You
> probably also want to move the current patch to "superseded" so Russell
> doesn't end up with two copies.
> 
> Will
> 
> [1] http://www.arm.linux.org.uk/developer/patches/viewpatch.php?id=8442/1

-- 
FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up
according to speedtest.net.

Re: Re: Re: Re: Re: Re: [PATCH v3] arm: Adding support for atomic half word exchange

[Sarbojit Ganguly]

[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset=windows-1252, Size: 1971 bytes --]

Thank you Will, I will make the required corrections and mail it to
patchesAtarm.linux.co.uk and mark [1] as "superseded".

Sarbojit

[1] http://www.arm.linux.org.uk/developer/patches/viewpatch.php?id=8442/1
------- Original Message -------
Sender : Will Deacon<will.deacon@arm.com>
Date : Oct 08, 2015 22:26 (GMT+05:30)
Title : Re: Re: Re: Re: Re: [PATCH v3] arm: Adding support for atomic half word exchange

On Wed, Oct 07, 2015 at 02:36:41PM +0000, Sarbojit Ganguly wrote:
> Please have a look at this patch, please let me know if any modification
> is required.
> I have also submitted the same in your patch system.

There are some problems with the version in the patch system[1]:

  (1) You still have the changelog in the commit message (I asked you to
      remove this last time).

  (2) The commit message isn't line-wrapper appropriately

  (3) Your Signed-off-by line is truncated

The patch system does actually support git, so you can add:

  KernelVersion: 4.3-rc4

or whatever kernel you based your patch on somewhere after your SoB but
before the diff and then mail it to patchesATarm.linux.org.uk. You
probably also want to move the current patch to "superseded" so Russell
doesn't end up with two copies.

Will

[1] http://www.arm.linux.org.uk/developer/patches/viewpatch.php?id=8442/1


?????
???   ??   ?? ??
----------------------------------------------------------------------+
The Tao lies beyond Yin and Yang. It is silent and still as a pool of water.      |
It does not seek fame, therefore nobody knows its presence.                       |
It does not seek fortune, for it is complete within itself.                       |
It exists beyond space and time.                                                  |
----------------------------------------------------------------------+ÿôèº{.nÇ+‰·Ÿ®‰­†+%ŠËÿ±éݶ\x17¥Šwÿº{.nÇ+‰·¥Š{±þG«éÿŠ{ayº\x1dʇڙë,j\a­¢f£¢·hšïêÿ‘êçz_è®\x03(­éšŽŠÝ¢j"ú\x1a¶^[m§ÿÿ¾\a«þG«éÿ¢¸?™¨è­Ú&£ø§~á¶iO•æ¬z·švØ^\x14\x04\x1a¶^[m§ÿÿÃ\fÿ¶ìÿ¢¸?–I¥

[PATCH v3] arm: Adding support for atomic half word exchange

[Will Deacon]

On Fri, Oct 09, 2015 at 02:41:54AM +0000, Sarbojit Ganguly wrote:
> Thank you Will, I will make the required corrections and mail it to
> patchesAtarm.linux.co.uk and mark [1] as "superseded".

Thanks. Also, you don't need to continually prepend "Re: " to your mail
subject every time you reply and/or update the patch. Doing so breaks
the email threading for everybody else.

Will

Re: Re: Re: Re: [PATCH v3] arm: Adding support for atomic half word exchange

[Sarbojit Ganguly]

[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset=windows-1252, Size: 4082 bytes --]


Hello Will
Here is the version 3 of the patch correcting earlier issues.

v2 -> v3 : Removed the comment related to Qspinlock, changed !defined to
#ifndef.
v1 -> v2 : Extended the guard code to cover the byte exchange case as 
well following opinion of Will Deacon.
Checkpatch has been run and issues were taken care of.

Since support for half-word atomic exchange was not there and Qspinlock
on ARM requires it, modified __xchg() to add support for that as well.
ARMv6 and lower does not support ldrex{b,h} so, added a guard code
to prevent build breaks.

Signed-off-by: Sarbojit Ganguly <ganguly.s@samsung.com>
---
 arch/arm/include/asm/cmpxchg.h | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/include/asm/cmpxchg.h b/arch/arm/include/asm/cmpxchg.h
index 916a274..c6436c1 100644
--- a/arch/arm/include/asm/cmpxchg.h
+++ b/arch/arm/include/asm/cmpxchg.h
@@ -39,6 +39,7 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size
 
 	switch (size) {
 #if __LINUX_ARM_ARCH__ >= 6
+#ifndef CONFIG_CPU_V6 /* MIN ARCH >= V6K */
 	case 1:
 		asm volatile("@	__xchg1\n"
 		"1:	ldrexb	%0, [%3]\n"
@@ -49,6 +50,17 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size
 			: "r" (x), "r" (ptr)
 			: "memory", "cc");
 		break;
+	case 2:
+		asm volatile("@	__xchg2\n"
+		"1:	ldrexh	%0, [%3]\n"
+		"	strexh	%1, %2, [%3]\n"
+		"	teq	%1, #0\n"
+		"	bne	1b"
+			: "=&r" (ret), "=&r" (tmp)
+			: "r" (x), "r" (ptr)
+			: "memory", "cc");
+		break;
+#endif
 	case 4:
 		asm volatile("@	__xchg4\n"
 		"1:	ldrex	%0, [%3]\n"
-- 
1.9.1


------- Original Message -------
Sender : Sarbojit Ganguly<ganguly.s@samsung.com> Technical Lead/SRI-Bangalore-AP Systems 1/Samsung Electronics
Date : Oct 06, 2015 08:38 (GMT+05:30)
Title : Re: Re: Re: [PATCH v2] arm: Adding support for atomic half word exchange

Hello Will,

Thank you so much for the review. I have thought it over and it makes
sense not to have that comment in cmpxchg.h, I will also change !defined to
#ifndef and quickly post a v3.

Regards,
Sarbojit

------- Original Message -------
Sender : Will Deacon
Date : Oct 05, 2015 21:30 (GMT+05:30)
Title : Re: Re: [PATCH v2] arm: Adding support for atomic half word exchange

On Mon, Oct 05, 2015 at 01:10:53PM +0000, Sarbojit Ganguly wrote:
> My sincere apologies for the format issue. This was due to the e-mail editor
> which reformats the text.
> I am reposting the patch, please let me know if it is ok this time.
> 
> 
> v1-->v2 : Extended the guard code to cover the byte exchange case as 
> well following opinion of Will Deacon.
> Checkpatch has been run and issues were taken care of.
> 
> Since support for half-word atomic exchange was not there and Qspinlock
> on ARM requires it, modified __xchg() to add support for that as well.
> ARMv6 and lower does not support ldrex{b,h} so, added a guard code
> to prevent build breaks.
> 
> Signed-off-by: Sarbojit Ganguly 
> ---
>  arch/arm/include/asm/cmpxchg.h | 17 +++++++++++++++++
>  1 file changed, 17 insertions(+)
> 
> diff --git a/arch/arm/include/asm/cmpxchg.h b/arch/arm/include/asm/cmpxchg.h
> index 916a274..a53cbeb 100644
> --- a/arch/arm/include/asm/cmpxchg.h
> +++ b/arch/arm/include/asm/cmpxchg.h
> @@ -39,6 +39,7 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size
>  
>   switch (size) {
>  #if __LINUX_ARM_ARCH__ >= 6
> +#if !defined(CONFIG_CPU_V6)

#ifndef ? (to match the __cmpxchg code).

>   case 1:
>   asm volatile("@ __xchg1\n"
>   "1: ldrexb %0, [%3]\n"
> @@ -49,6 +50,22 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size
>   : "r" (x), "r" (ptr)
>   : "memory", "cc");
>   break;
> +
> + /*
> + * Half-word atomic exchange, required
> + * for Qspinlock support on ARM.
> + */

I think I said it before, but I don't think this comment is of any real
value.

Other than those, this looks ok to me.

Willÿôèº{.nÇ+‰·Ÿ®‰­†+%ŠËÿ±éݶ\x17¥Šwÿº{.nÇ+‰·¥Š{±þG«éÿŠ{ayº\x1dʇڙë,j\a­¢f£¢·hšïêÿ‘êçz_è®\x03(­éšŽŠÝ¢j"ú\x1a¶^[m§ÿÿ¾\a«þG«éÿ¢¸?™¨è­Ú&£ø§~á¶iO•æ¬z·švØ^\x14\x04\x1a¶^[m§ÿÿÃ\fÿ¶ìÿ¢¸?–I¥

[PATCH v3] arm: Adding support for atomic half word exchange

[Will Deacon]

On Tue, Oct 06, 2015 at 08:03:02AM +0000, Sarbojit Ganguly wrote:
> Here is the version 3 of the patch correcting earlier issues.

This looks good to me now:

  Acked-by: Will Deacon <will.deacon@arm.com>

> v2 -> v3 : Removed the comment related to Qspinlock, changed !defined to
> #ifndef.
> v1 -> v2 : Extended the guard code to cover the byte exchange case as 
> well following opinion of Will Deacon.
> Checkpatch has been run and issues were taken care of.

The part of your text up until here doesn't belong in the commit message.
You'll also need to send this to Russell's patch system.

Will

> Since support for half-word atomic exchange was not there and Qspinlock
> on ARM requires it, modified __xchg() to add support for that as well.
> ARMv6 and lower does not support ldrex{b,h} so, added a guard code
> to prevent build breaks.
> 
> Signed-off-by: Sarbojit Ganguly <ganguly.s@samsung.com>
> ---
>  arch/arm/include/asm/cmpxchg.h | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/arch/arm/include/asm/cmpxchg.h b/arch/arm/include/asm/cmpxchg.h
> index 916a274..c6436c1 100644
> --- a/arch/arm/include/asm/cmpxchg.h
> +++ b/arch/arm/include/asm/cmpxchg.h
> @@ -39,6 +39,7 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size
>  
>  	switch (size) {
>  #if __LINUX_ARM_ARCH__ >= 6
> +#ifndef CONFIG_CPU_V6 /* MIN ARCH >= V6K */
>  	case 1:
>  		asm volatile("@	__xchg1\n"
>  		"1:	ldrexb	%0, [%3]\n"
> @@ -49,6 +50,17 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size
>  			: "r" (x), "r" (ptr)
>  			: "memory", "cc");
>  		break;
> +	case 2:
> +		asm volatile("@	__xchg2\n"
> +		"1:	ldrexh	%0, [%3]\n"
> +		"	strexh	%1, %2, [%3]\n"
> +		"	teq	%1, #0\n"
> +		"	bne	1b"
> +			: "=&r" (ret), "=&r" (tmp)
> +			: "r" (x), "r" (ptr)
> +			: "memory", "cc");
> +		break;
> +#endif
>  	case 4:
>  		asm volatile("@	__xchg4\n"
>  		"1:	ldrex	%0, [%3]\n"
> -- 
> 1.9.1