[PATCH V3 0/2] Add SPDIF_GCLK clock in clock tree for imx6

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* [PATCH V3 0/2] Add SPDIF_GCLK clock in clock tree for imx6
@ 2015-10-10 10:15 ` Shengjiu Wang
  0 siblings, 0 replies; 19+ messages in thread
From: Shengjiu Wang @ 2015-10-10 10:15 UTC (permalink / raw)
  To: linux-arm-kernel

Add SPDIF_GCLK clock in clock tree

Shengjiu Wang (2):
  clk: imx6: Add SPDIF_GCLK clock in clock tree
  ARM: dts: imx6: change the core clock of spdif

Changes in v3:
- refine the commit logs.

 arch/arm/boot/dts/imx6qdl.dtsi            | 12 ++++++------
 arch/arm/boot/dts/imx6sl.dtsi             | 16 ++++++++++++++++
 arch/arm/boot/dts/imx6sx.dtsi             |  2 +-
 drivers/clk/imx/clk-imx6q.c               |  4 +++-
 drivers/clk/imx/clk-imx6sl.c              |  4 +++-
 drivers/clk/imx/clk-imx6sx.c              |  1 +
 include/dt-bindings/clock/imx6qdl-clock.h |  3 ++-
 include/dt-bindings/clock/imx6sl-clock.h  |  3 ++-
 include/dt-bindings/clock/imx6sx-clock.h  |  3 ++-
 9 files changed, 36 insertions(+), 12 deletions(-)

-- 
1.9.1

^ permalink raw reply	[flat|nested] 19+ messages in thread

* [PATCH V3 0/2] Add SPDIF_GCLK clock in clock tree for imx6
@ 2015-10-10 10:15 ` Shengjiu Wang
  0 siblings, 0 replies; 19+ messages in thread
From: Shengjiu Wang @ 2015-10-10 10:15 UTC (permalink / raw)
  To: shawnguo, kernel, robh+dt, pawel.moll, mark.rutland,
	ijc+devicetree, galak, linux, mturquette
  Cc: linux-arm-kernel, devicetree, linux-kernel

Add SPDIF_GCLK clock in clock tree

Shengjiu Wang (2):
  clk: imx6: Add SPDIF_GCLK clock in clock tree
  ARM: dts: imx6: change the core clock of spdif

Changes in v3:
- refine the commit logs.

 arch/arm/boot/dts/imx6qdl.dtsi            | 12 ++++++------
 arch/arm/boot/dts/imx6sl.dtsi             | 16 ++++++++++++++++
 arch/arm/boot/dts/imx6sx.dtsi             |  2 +-
 drivers/clk/imx/clk-imx6q.c               |  4 +++-
 drivers/clk/imx/clk-imx6sl.c              |  4 +++-
 drivers/clk/imx/clk-imx6sx.c              |  1 +
 include/dt-bindings/clock/imx6qdl-clock.h |  3 ++-
 include/dt-bindings/clock/imx6sl-clock.h  |  3 ++-
 include/dt-bindings/clock/imx6sx-clock.h  |  3 ++-
 9 files changed, 36 insertions(+), 12 deletions(-)

-- 
1.9.1


^ permalink raw reply	[flat|nested] 19+ messages in thread

* [PATCH V3 0/2] Add SPDIF_GCLK clock in clock tree for imx6
@ 2015-10-10 10:15 ` Shengjiu Wang
  0 siblings, 0 replies; 19+ messages in thread
From: Shengjiu Wang @ 2015-10-10 10:15 UTC (permalink / raw)
  To: shawnguo-DgEjT+Ai2ygdnm+yROfE0A, kernel-bIcnvbaLZ9MEGnE8C9+IrQ,
	robh+dt-DgEjT+Ai2ygdnm+yROfE0A, pawel.moll-5wv7dgnIgG8,
	mark.rutland-5wv7dgnIgG8, ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
	galak-sgV2jX0FEOL9JmXXK+q4OQ, linux-lFZ/pmaqli7XmaaqVzeoHQ,
	mturquette-rdvid1DuHRBWk0Htik3J/w
  Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	devicetree-u79uwXL29TY76Z2rM5mHXA,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA

Add SPDIF_GCLK clock in clock tree

Shengjiu Wang (2):
  clk: imx6: Add SPDIF_GCLK clock in clock tree
  ARM: dts: imx6: change the core clock of spdif

Changes in v3:
- refine the commit logs.

 arch/arm/boot/dts/imx6qdl.dtsi            | 12 ++++++------
 arch/arm/boot/dts/imx6sl.dtsi             | 16 ++++++++++++++++
 arch/arm/boot/dts/imx6sx.dtsi             |  2 +-
 drivers/clk/imx/clk-imx6q.c               |  4 +++-
 drivers/clk/imx/clk-imx6sl.c              |  4 +++-
 drivers/clk/imx/clk-imx6sx.c              |  1 +
 include/dt-bindings/clock/imx6qdl-clock.h |  3 ++-
 include/dt-bindings/clock/imx6sl-clock.h  |  3 ++-
 include/dt-bindings/clock/imx6sx-clock.h  |  3 ++-
 9 files changed, 36 insertions(+), 12 deletions(-)

-- 
1.9.1

--
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^ permalink raw reply	[flat|nested] 19+ messages in thread

* [PATCH V3 1/2] clk: imx6: Add SPDIF_GCLK clock in clock tree
  2015-10-10 10:15 ` Shengjiu Wang
  (?)
@ 2015-10-10 10:15   ` Shengjiu Wang
  -1 siblings, 0 replies; 19+ messages in thread
From: Shengjiu Wang @ 2015-10-10 10:15 UTC (permalink / raw)
  To: linux-arm-kernel

Correct SPDIF clock setting issue in clock tree, the SPDIF_GCLK is also
one clock of SPDIF, which is missed before.

We found an issue that imx can't enter low power mode with spdif
if IMX6x_CLK_SPDIF is used as the core clock of spdif. Because
spdif driver will register IMX6x_CLK_SPDIF clock to regmap, regmap will do
clk_prepare in init function, then IMX6x_CLK_SPDIF clock is prepared in probe,
so its parent clock (PLL clock) is prepared, the prepare operation of
PLL clock is to enable the clock. But I.MX needs all PLL clock is disabled,
then it can enter low power mode.

So we can't use IMX6x_CLK_SPDIF as the core clock of spdif, the correct spdif
core clock is SPDIF_GCLK, which share same gate bit with IMX6x_CLK_SPDIF clock.
SPDIF_GCLK's parent clock is ipg clock.

Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
---
 drivers/clk/imx/clk-imx6q.c               | 4 +++-
 drivers/clk/imx/clk-imx6sl.c              | 4 +++-
 drivers/clk/imx/clk-imx6sx.c              | 1 +
 include/dt-bindings/clock/imx6qdl-clock.h | 3 ++-
 include/dt-bindings/clock/imx6sl-clock.h  | 3 ++-
 include/dt-bindings/clock/imx6sx-clock.h  | 3 ++-
 6 files changed, 13 insertions(+), 5 deletions(-)

diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c
index e9ba018..c193508 100644
--- a/drivers/clk/imx/clk-imx6q.c
+++ b/drivers/clk/imx/clk-imx6q.c
@@ -119,6 +119,7 @@ static unsigned int share_count_ssi1;
 static unsigned int share_count_ssi2;
 static unsigned int share_count_ssi3;
 static unsigned int share_count_mipi_core_cfg;
+static unsigned int share_count_spdif;
 
 static inline int clk_on_imx6q(void)
 {
@@ -462,7 +463,8 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
 	clk[IMX6QDL_CLK_SATA]         = imx_clk_gate2("sata",          "ahb",               base + 0x7c, 4);
 	clk[IMX6QDL_CLK_SDMA]         = imx_clk_gate2("sdma",          "ahb",               base + 0x7c, 6);
 	clk[IMX6QDL_CLK_SPBA]         = imx_clk_gate2("spba",          "ipg",               base + 0x7c, 12);
-	clk[IMX6QDL_CLK_SPDIF]        = imx_clk_gate2("spdif",         "spdif_podf",        base + 0x7c, 14);
+	clk[IMX6QDL_CLK_SPDIF]        = imx_clk_gate2_shared("spdif",     "spdif_podf",     base + 0x7c, 14, &share_count_spdif);
+	clk[IMX6QDL_CLK_SPDIF_GCLK]   = imx_clk_gate2_shared("spdif_gclk", "ipg",           base + 0x7c, 14, &share_count_spdif);
 	clk[IMX6QDL_CLK_SSI1_IPG]     = imx_clk_gate2_shared("ssi1_ipg",      "ipg",        base + 0x7c, 18, &share_count_ssi1);
 	clk[IMX6QDL_CLK_SSI2_IPG]     = imx_clk_gate2_shared("ssi2_ipg",      "ipg",        base + 0x7c, 20, &share_count_ssi2);
 	clk[IMX6QDL_CLK_SSI3_IPG]     = imx_clk_gate2_shared("ssi3_ipg",      "ipg",        base + 0x7c, 22, &share_count_ssi3);
diff --git a/drivers/clk/imx/clk-imx6sl.c b/drivers/clk/imx/clk-imx6sl.c
index 3c3333f..1be6230 100644
--- a/drivers/clk/imx/clk-imx6sl.c
+++ b/drivers/clk/imx/clk-imx6sl.c
@@ -97,6 +97,7 @@ static struct clk_div_table video_div_table[] = {
 static unsigned int share_count_ssi1;
 static unsigned int share_count_ssi2;
 static unsigned int share_count_ssi3;
+static unsigned int share_count_spdif;
 
 static struct clk *clks[IMX6SL_CLK_END];
 static struct clk_onecell_data clk_data;
@@ -397,7 +398,8 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
 	clks[IMX6SL_CLK_PWM4]         = imx_clk_gate2("pwm4",         "perclk",            base + 0x78, 22);
 	clks[IMX6SL_CLK_SDMA]         = imx_clk_gate2("sdma",         "ipg",               base + 0x7c, 6);
 	clks[IMX6SL_CLK_SPBA]         = imx_clk_gate2("spba",         "ipg",               base + 0x7c, 12);
-	clks[IMX6SL_CLK_SPDIF]        = imx_clk_gate2("spdif",        "spdif0_podf",       base + 0x7c, 14);
+	clks[IMX6SL_CLK_SPDIF]        = imx_clk_gate2_shared("spdif",     "spdif0_podf",   base + 0x7c, 14, &share_count_spdif);
+	clks[IMX6SL_CLK_SPDIF_GCLK]   = imx_clk_gate2_shared("spdif_gclk",  "ipg",         base + 0x7c, 14, &share_count_spdif);
 	clks[IMX6SL_CLK_SSI1_IPG]     = imx_clk_gate2_shared("ssi1_ipg",     "ipg",        base + 0x7c, 18, &share_count_ssi1);
 	clks[IMX6SL_CLK_SSI2_IPG]     = imx_clk_gate2_shared("ssi2_ipg",     "ipg",        base + 0x7c, 20, &share_count_ssi2);
 	clks[IMX6SL_CLK_SSI3_IPG]     = imx_clk_gate2_shared("ssi3_ipg",     "ipg",        base + 0x7c, 22, &share_count_ssi3);
diff --git a/drivers/clk/imx/clk-imx6sx.c b/drivers/clk/imx/clk-imx6sx.c
index f0ad8bb..fea125e 100644
--- a/drivers/clk/imx/clk-imx6sx.c
+++ b/drivers/clk/imx/clk-imx6sx.c
@@ -460,6 +460,7 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
 	clks[IMX6SX_CLK_SPBA]         = imx_clk_gate2("spba",          "ipg",               base + 0x7c, 12);
 	clks[IMX6SX_CLK_AUDIO]        = imx_clk_gate2_shared("audio",  "audio_podf",        base + 0x7c, 14, &share_count_audio);
 	clks[IMX6SX_CLK_SPDIF]        = imx_clk_gate2_shared("spdif",  "spdif_podf",        base + 0x7c, 14, &share_count_audio);
+	clks[IMX6SX_CLK_SPDIF_GCLK]   = imx_clk_gate2_shared("spdif_gclk",    "ipg",        base + 0x7c, 14, &share_count_audio);
 	clks[IMX6SX_CLK_SSI1_IPG]     = imx_clk_gate2_shared("ssi1_ipg",      "ipg",        base + 0x7c, 18, &share_count_ssi1);
 	clks[IMX6SX_CLK_SSI2_IPG]     = imx_clk_gate2_shared("ssi2_ipg",      "ipg",        base + 0x7c, 20, &share_count_ssi2);
 	clks[IMX6SX_CLK_SSI3_IPG]     = imx_clk_gate2_shared("ssi3_ipg",      "ipg",        base + 0x7c, 22, &share_count_ssi3);
diff --git a/include/dt-bindings/clock/imx6qdl-clock.h b/include/dt-bindings/clock/imx6qdl-clock.h
index 8de173f..77985cc 100644
--- a/include/dt-bindings/clock/imx6qdl-clock.h
+++ b/include/dt-bindings/clock/imx6qdl-clock.h
@@ -254,6 +254,7 @@
 #define IMX6QDL_CLK_CAAM_MEM			241
 #define IMX6QDL_CLK_CAAM_ACLK			242
 #define IMX6QDL_CLK_CAAM_IPG			243
-#define IMX6QDL_CLK_END				244
+#define IMX6QDL_CLK_SPDIF_GCLK			244
+#define IMX6QDL_CLK_END				245
 
 #endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */
diff --git a/include/dt-bindings/clock/imx6sl-clock.h b/include/dt-bindings/clock/imx6sl-clock.h
index 9ce4e42..e14573e 100644
--- a/include/dt-bindings/clock/imx6sl-clock.h
+++ b/include/dt-bindings/clock/imx6sl-clock.h
@@ -174,6 +174,7 @@
 #define IMX6SL_CLK_SSI1_IPG		161
 #define IMX6SL_CLK_SSI2_IPG		162
 #define IMX6SL_CLK_SSI3_IPG		163
-#define IMX6SL_CLK_END			164
+#define IMX6SL_CLK_SPDIF_GCLK		164
+#define IMX6SL_CLK_END			165
 
 #endif /* __DT_BINDINGS_CLOCK_IMX6SL_H */
diff --git a/include/dt-bindings/clock/imx6sx-clock.h b/include/dt-bindings/clock/imx6sx-clock.h
index 9957091..36f0324 100644
--- a/include/dt-bindings/clock/imx6sx-clock.h
+++ b/include/dt-bindings/clock/imx6sx-clock.h
@@ -274,6 +274,7 @@
 #define IMX6SX_PLL5_BYPASS		261
 #define IMX6SX_PLL6_BYPASS		262
 #define IMX6SX_PLL7_BYPASS		263
-#define IMX6SX_CLK_CLK_END		264
+#define IMX6SX_CLK_SPDIF_GCLK		264
+#define IMX6SX_CLK_CLK_END		265
 
 #endif /* __DT_BINDINGS_CLOCK_IMX6SX_H */
-- 
1.9.1

^ permalink raw reply related	[flat|nested] 19+ messages in thread

* [PATCH V3 1/2] clk: imx6: Add SPDIF_GCLK clock in clock tree
@ 2015-10-10 10:15   ` Shengjiu Wang
  0 siblings, 0 replies; 19+ messages in thread
From: Shengjiu Wang @ 2015-10-10 10:15 UTC (permalink / raw)
  To: shawnguo, kernel, robh+dt, pawel.moll, mark.rutland,
	ijc+devicetree, galak, linux, mturquette
  Cc: linux-arm-kernel, devicetree, linux-kernel

Correct SPDIF clock setting issue in clock tree, the SPDIF_GCLK is also
one clock of SPDIF, which is missed before.

We found an issue that imx can't enter low power mode with spdif
if IMX6x_CLK_SPDIF is used as the core clock of spdif. Because
spdif driver will register IMX6x_CLK_SPDIF clock to regmap, regmap will do
clk_prepare in init function, then IMX6x_CLK_SPDIF clock is prepared in probe,
so its parent clock (PLL clock) is prepared, the prepare operation of
PLL clock is to enable the clock. But I.MX needs all PLL clock is disabled,
then it can enter low power mode.

So we can't use IMX6x_CLK_SPDIF as the core clock of spdif, the correct spdif
core clock is SPDIF_GCLK, which share same gate bit with IMX6x_CLK_SPDIF clock.
SPDIF_GCLK's parent clock is ipg clock.

Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
---
 drivers/clk/imx/clk-imx6q.c               | 4 +++-
 drivers/clk/imx/clk-imx6sl.c              | 4 +++-
 drivers/clk/imx/clk-imx6sx.c              | 1 +
 include/dt-bindings/clock/imx6qdl-clock.h | 3 ++-
 include/dt-bindings/clock/imx6sl-clock.h  | 3 ++-
 include/dt-bindings/clock/imx6sx-clock.h  | 3 ++-
 6 files changed, 13 insertions(+), 5 deletions(-)

diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c
index e9ba018..c193508 100644
--- a/drivers/clk/imx/clk-imx6q.c
+++ b/drivers/clk/imx/clk-imx6q.c
@@ -119,6 +119,7 @@ static unsigned int share_count_ssi1;
 static unsigned int share_count_ssi2;
 static unsigned int share_count_ssi3;
 static unsigned int share_count_mipi_core_cfg;
+static unsigned int share_count_spdif;
 
 static inline int clk_on_imx6q(void)
 {
@@ -462,7 +463,8 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
 	clk[IMX6QDL_CLK_SATA]         = imx_clk_gate2("sata",          "ahb",               base + 0x7c, 4);
 	clk[IMX6QDL_CLK_SDMA]         = imx_clk_gate2("sdma",          "ahb",               base + 0x7c, 6);
 	clk[IMX6QDL_CLK_SPBA]         = imx_clk_gate2("spba",          "ipg",               base + 0x7c, 12);
-	clk[IMX6QDL_CLK_SPDIF]        = imx_clk_gate2("spdif",         "spdif_podf",        base + 0x7c, 14);
+	clk[IMX6QDL_CLK_SPDIF]        = imx_clk_gate2_shared("spdif",     "spdif_podf",     base + 0x7c, 14, &share_count_spdif);
+	clk[IMX6QDL_CLK_SPDIF_GCLK]   = imx_clk_gate2_shared("spdif_gclk", "ipg",           base + 0x7c, 14, &share_count_spdif);
 	clk[IMX6QDL_CLK_SSI1_IPG]     = imx_clk_gate2_shared("ssi1_ipg",      "ipg",        base + 0x7c, 18, &share_count_ssi1);
 	clk[IMX6QDL_CLK_SSI2_IPG]     = imx_clk_gate2_shared("ssi2_ipg",      "ipg",        base + 0x7c, 20, &share_count_ssi2);
 	clk[IMX6QDL_CLK_SSI3_IPG]     = imx_clk_gate2_shared("ssi3_ipg",      "ipg",        base + 0x7c, 22, &share_count_ssi3);
diff --git a/drivers/clk/imx/clk-imx6sl.c b/drivers/clk/imx/clk-imx6sl.c
index 3c3333f..1be6230 100644
--- a/drivers/clk/imx/clk-imx6sl.c
+++ b/drivers/clk/imx/clk-imx6sl.c
@@ -97,6 +97,7 @@ static struct clk_div_table video_div_table[] = {
 static unsigned int share_count_ssi1;
 static unsigned int share_count_ssi2;
 static unsigned int share_count_ssi3;
+static unsigned int share_count_spdif;
 
 static struct clk *clks[IMX6SL_CLK_END];
 static struct clk_onecell_data clk_data;
@@ -397,7 +398,8 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
 	clks[IMX6SL_CLK_PWM4]         = imx_clk_gate2("pwm4",         "perclk",            base + 0x78, 22);
 	clks[IMX6SL_CLK_SDMA]         = imx_clk_gate2("sdma",         "ipg",               base + 0x7c, 6);
 	clks[IMX6SL_CLK_SPBA]         = imx_clk_gate2("spba",         "ipg",               base + 0x7c, 12);
-	clks[IMX6SL_CLK_SPDIF]        = imx_clk_gate2("spdif",        "spdif0_podf",       base + 0x7c, 14);
+	clks[IMX6SL_CLK_SPDIF]        = imx_clk_gate2_shared("spdif",     "spdif0_podf",   base + 0x7c, 14, &share_count_spdif);
+	clks[IMX6SL_CLK_SPDIF_GCLK]   = imx_clk_gate2_shared("spdif_gclk",  "ipg",         base + 0x7c, 14, &share_count_spdif);
 	clks[IMX6SL_CLK_SSI1_IPG]     = imx_clk_gate2_shared("ssi1_ipg",     "ipg",        base + 0x7c, 18, &share_count_ssi1);
 	clks[IMX6SL_CLK_SSI2_IPG]     = imx_clk_gate2_shared("ssi2_ipg",     "ipg",        base + 0x7c, 20, &share_count_ssi2);
 	clks[IMX6SL_CLK_SSI3_IPG]     = imx_clk_gate2_shared("ssi3_ipg",     "ipg",        base + 0x7c, 22, &share_count_ssi3);
diff --git a/drivers/clk/imx/clk-imx6sx.c b/drivers/clk/imx/clk-imx6sx.c
index f0ad8bb..fea125e 100644
--- a/drivers/clk/imx/clk-imx6sx.c
+++ b/drivers/clk/imx/clk-imx6sx.c
@@ -460,6 +460,7 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
 	clks[IMX6SX_CLK_SPBA]         = imx_clk_gate2("spba",          "ipg",               base + 0x7c, 12);
 	clks[IMX6SX_CLK_AUDIO]        = imx_clk_gate2_shared("audio",  "audio_podf",        base + 0x7c, 14, &share_count_audio);
 	clks[IMX6SX_CLK_SPDIF]        = imx_clk_gate2_shared("spdif",  "spdif_podf",        base + 0x7c, 14, &share_count_audio);
+	clks[IMX6SX_CLK_SPDIF_GCLK]   = imx_clk_gate2_shared("spdif_gclk",    "ipg",        base + 0x7c, 14, &share_count_audio);
 	clks[IMX6SX_CLK_SSI1_IPG]     = imx_clk_gate2_shared("ssi1_ipg",      "ipg",        base + 0x7c, 18, &share_count_ssi1);
 	clks[IMX6SX_CLK_SSI2_IPG]     = imx_clk_gate2_shared("ssi2_ipg",      "ipg",        base + 0x7c, 20, &share_count_ssi2);
 	clks[IMX6SX_CLK_SSI3_IPG]     = imx_clk_gate2_shared("ssi3_ipg",      "ipg",        base + 0x7c, 22, &share_count_ssi3);
diff --git a/include/dt-bindings/clock/imx6qdl-clock.h b/include/dt-bindings/clock/imx6qdl-clock.h
index 8de173f..77985cc 100644
--- a/include/dt-bindings/clock/imx6qdl-clock.h
+++ b/include/dt-bindings/clock/imx6qdl-clock.h
@@ -254,6 +254,7 @@
 #define IMX6QDL_CLK_CAAM_MEM			241
 #define IMX6QDL_CLK_CAAM_ACLK			242
 #define IMX6QDL_CLK_CAAM_IPG			243
-#define IMX6QDL_CLK_END				244
+#define IMX6QDL_CLK_SPDIF_GCLK			244
+#define IMX6QDL_CLK_END				245
 
 #endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */
diff --git a/include/dt-bindings/clock/imx6sl-clock.h b/include/dt-bindings/clock/imx6sl-clock.h
index 9ce4e42..e14573e 100644
--- a/include/dt-bindings/clock/imx6sl-clock.h
+++ b/include/dt-bindings/clock/imx6sl-clock.h
@@ -174,6 +174,7 @@
 #define IMX6SL_CLK_SSI1_IPG		161
 #define IMX6SL_CLK_SSI2_IPG		162
 #define IMX6SL_CLK_SSI3_IPG		163
-#define IMX6SL_CLK_END			164
+#define IMX6SL_CLK_SPDIF_GCLK		164
+#define IMX6SL_CLK_END			165
 
 #endif /* __DT_BINDINGS_CLOCK_IMX6SL_H */
diff --git a/include/dt-bindings/clock/imx6sx-clock.h b/include/dt-bindings/clock/imx6sx-clock.h
index 9957091..36f0324 100644
--- a/include/dt-bindings/clock/imx6sx-clock.h
+++ b/include/dt-bindings/clock/imx6sx-clock.h
@@ -274,6 +274,7 @@
 #define IMX6SX_PLL5_BYPASS		261
 #define IMX6SX_PLL6_BYPASS		262
 #define IMX6SX_PLL7_BYPASS		263
-#define IMX6SX_CLK_CLK_END		264
+#define IMX6SX_CLK_SPDIF_GCLK		264
+#define IMX6SX_CLK_CLK_END		265
 
 #endif /* __DT_BINDINGS_CLOCK_IMX6SX_H */
-- 
1.9.1


^ permalink raw reply related	[flat|nested] 19+ messages in thread

* [PATCH V3 1/2] clk: imx6: Add SPDIF_GCLK clock in clock tree
@ 2015-10-10 10:15   ` Shengjiu Wang
  0 siblings, 0 replies; 19+ messages in thread
From: Shengjiu Wang @ 2015-10-10 10:15 UTC (permalink / raw)
  To: shawnguo, kernel, robh+dt, pawel.moll, mark.rutland,
	ijc+devicetree, galak, linux, mturquette
  Cc: devicetree, linux-kernel, linux-arm-kernel

Correct SPDIF clock setting issue in clock tree, the SPDIF_GCLK is also
one clock of SPDIF, which is missed before.

We found an issue that imx can't enter low power mode with spdif
if IMX6x_CLK_SPDIF is used as the core clock of spdif. Because
spdif driver will register IMX6x_CLK_SPDIF clock to regmap, regmap will do
clk_prepare in init function, then IMX6x_CLK_SPDIF clock is prepared in probe,
so its parent clock (PLL clock) is prepared, the prepare operation of
PLL clock is to enable the clock. But I.MX needs all PLL clock is disabled,
then it can enter low power mode.

So we can't use IMX6x_CLK_SPDIF as the core clock of spdif, the correct spdif
core clock is SPDIF_GCLK, which share same gate bit with IMX6x_CLK_SPDIF clock.
SPDIF_GCLK's parent clock is ipg clock.

Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
---
 drivers/clk/imx/clk-imx6q.c               | 4 +++-
 drivers/clk/imx/clk-imx6sl.c              | 4 +++-
 drivers/clk/imx/clk-imx6sx.c              | 1 +
 include/dt-bindings/clock/imx6qdl-clock.h | 3 ++-
 include/dt-bindings/clock/imx6sl-clock.h  | 3 ++-
 include/dt-bindings/clock/imx6sx-clock.h  | 3 ++-
 6 files changed, 13 insertions(+), 5 deletions(-)

diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c
index e9ba018..c193508 100644
--- a/drivers/clk/imx/clk-imx6q.c
+++ b/drivers/clk/imx/clk-imx6q.c
@@ -119,6 +119,7 @@ static unsigned int share_count_ssi1;
 static unsigned int share_count_ssi2;
 static unsigned int share_count_ssi3;
 static unsigned int share_count_mipi_core_cfg;
+static unsigned int share_count_spdif;
 
 static inline int clk_on_imx6q(void)
 {
@@ -462,7 +463,8 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
 	clk[IMX6QDL_CLK_SATA]         = imx_clk_gate2("sata",          "ahb",               base + 0x7c, 4);
 	clk[IMX6QDL_CLK_SDMA]         = imx_clk_gate2("sdma",          "ahb",               base + 0x7c, 6);
 	clk[IMX6QDL_CLK_SPBA]         = imx_clk_gate2("spba",          "ipg",               base + 0x7c, 12);
-	clk[IMX6QDL_CLK_SPDIF]        = imx_clk_gate2("spdif",         "spdif_podf",        base + 0x7c, 14);
+	clk[IMX6QDL_CLK_SPDIF]        = imx_clk_gate2_shared("spdif",     "spdif_podf",     base + 0x7c, 14, &share_count_spdif);
+	clk[IMX6QDL_CLK_SPDIF_GCLK]   = imx_clk_gate2_shared("spdif_gclk", "ipg",           base + 0x7c, 14, &share_count_spdif);
 	clk[IMX6QDL_CLK_SSI1_IPG]     = imx_clk_gate2_shared("ssi1_ipg",      "ipg",        base + 0x7c, 18, &share_count_ssi1);
 	clk[IMX6QDL_CLK_SSI2_IPG]     = imx_clk_gate2_shared("ssi2_ipg",      "ipg",        base + 0x7c, 20, &share_count_ssi2);
 	clk[IMX6QDL_CLK_SSI3_IPG]     = imx_clk_gate2_shared("ssi3_ipg",      "ipg",        base + 0x7c, 22, &share_count_ssi3);
diff --git a/drivers/clk/imx/clk-imx6sl.c b/drivers/clk/imx/clk-imx6sl.c
index 3c3333f..1be6230 100644
--- a/drivers/clk/imx/clk-imx6sl.c
+++ b/drivers/clk/imx/clk-imx6sl.c
@@ -97,6 +97,7 @@ static struct clk_div_table video_div_table[] = {
 static unsigned int share_count_ssi1;
 static unsigned int share_count_ssi2;
 static unsigned int share_count_ssi3;
+static unsigned int share_count_spdif;
 
 static struct clk *clks[IMX6SL_CLK_END];
 static struct clk_onecell_data clk_data;
@@ -397,7 +398,8 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
 	clks[IMX6SL_CLK_PWM4]         = imx_clk_gate2("pwm4",         "perclk",            base + 0x78, 22);
 	clks[IMX6SL_CLK_SDMA]         = imx_clk_gate2("sdma",         "ipg",               base + 0x7c, 6);
 	clks[IMX6SL_CLK_SPBA]         = imx_clk_gate2("spba",         "ipg",               base + 0x7c, 12);
-	clks[IMX6SL_CLK_SPDIF]        = imx_clk_gate2("spdif",        "spdif0_podf",       base + 0x7c, 14);
+	clks[IMX6SL_CLK_SPDIF]        = imx_clk_gate2_shared("spdif",     "spdif0_podf",   base + 0x7c, 14, &share_count_spdif);
+	clks[IMX6SL_CLK_SPDIF_GCLK]   = imx_clk_gate2_shared("spdif_gclk",  "ipg",         base + 0x7c, 14, &share_count_spdif);
 	clks[IMX6SL_CLK_SSI1_IPG]     = imx_clk_gate2_shared("ssi1_ipg",     "ipg",        base + 0x7c, 18, &share_count_ssi1);
 	clks[IMX6SL_CLK_SSI2_IPG]     = imx_clk_gate2_shared("ssi2_ipg",     "ipg",        base + 0x7c, 20, &share_count_ssi2);
 	clks[IMX6SL_CLK_SSI3_IPG]     = imx_clk_gate2_shared("ssi3_ipg",     "ipg",        base + 0x7c, 22, &share_count_ssi3);
diff --git a/drivers/clk/imx/clk-imx6sx.c b/drivers/clk/imx/clk-imx6sx.c
index f0ad8bb..fea125e 100644
--- a/drivers/clk/imx/clk-imx6sx.c
+++ b/drivers/clk/imx/clk-imx6sx.c
@@ -460,6 +460,7 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
 	clks[IMX6SX_CLK_SPBA]         = imx_clk_gate2("spba",          "ipg",               base + 0x7c, 12);
 	clks[IMX6SX_CLK_AUDIO]        = imx_clk_gate2_shared("audio",  "audio_podf",        base + 0x7c, 14, &share_count_audio);
 	clks[IMX6SX_CLK_SPDIF]        = imx_clk_gate2_shared("spdif",  "spdif_podf",        base + 0x7c, 14, &share_count_audio);
+	clks[IMX6SX_CLK_SPDIF_GCLK]   = imx_clk_gate2_shared("spdif_gclk",    "ipg",        base + 0x7c, 14, &share_count_audio);
 	clks[IMX6SX_CLK_SSI1_IPG]     = imx_clk_gate2_shared("ssi1_ipg",      "ipg",        base + 0x7c, 18, &share_count_ssi1);
 	clks[IMX6SX_CLK_SSI2_IPG]     = imx_clk_gate2_shared("ssi2_ipg",      "ipg",        base + 0x7c, 20, &share_count_ssi2);
 	clks[IMX6SX_CLK_SSI3_IPG]     = imx_clk_gate2_shared("ssi3_ipg",      "ipg",        base + 0x7c, 22, &share_count_ssi3);
diff --git a/include/dt-bindings/clock/imx6qdl-clock.h b/include/dt-bindings/clock/imx6qdl-clock.h
index 8de173f..77985cc 100644
--- a/include/dt-bindings/clock/imx6qdl-clock.h
+++ b/include/dt-bindings/clock/imx6qdl-clock.h
@@ -254,6 +254,7 @@
 #define IMX6QDL_CLK_CAAM_MEM			241
 #define IMX6QDL_CLK_CAAM_ACLK			242
 #define IMX6QDL_CLK_CAAM_IPG			243
-#define IMX6QDL_CLK_END				244
+#define IMX6QDL_CLK_SPDIF_GCLK			244
+#define IMX6QDL_CLK_END				245
 
 #endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */
diff --git a/include/dt-bindings/clock/imx6sl-clock.h b/include/dt-bindings/clock/imx6sl-clock.h
index 9ce4e42..e14573e 100644
--- a/include/dt-bindings/clock/imx6sl-clock.h
+++ b/include/dt-bindings/clock/imx6sl-clock.h
@@ -174,6 +174,7 @@
 #define IMX6SL_CLK_SSI1_IPG		161
 #define IMX6SL_CLK_SSI2_IPG		162
 #define IMX6SL_CLK_SSI3_IPG		163
-#define IMX6SL_CLK_END			164
+#define IMX6SL_CLK_SPDIF_GCLK		164
+#define IMX6SL_CLK_END			165
 
 #endif /* __DT_BINDINGS_CLOCK_IMX6SL_H */
diff --git a/include/dt-bindings/clock/imx6sx-clock.h b/include/dt-bindings/clock/imx6sx-clock.h
index 9957091..36f0324 100644
--- a/include/dt-bindings/clock/imx6sx-clock.h
+++ b/include/dt-bindings/clock/imx6sx-clock.h
@@ -274,6 +274,7 @@
 #define IMX6SX_PLL5_BYPASS		261
 #define IMX6SX_PLL6_BYPASS		262
 #define IMX6SX_PLL7_BYPASS		263
-#define IMX6SX_CLK_CLK_END		264
+#define IMX6SX_CLK_SPDIF_GCLK		264
+#define IMX6SX_CLK_CLK_END		265
 
 #endif /* __DT_BINDINGS_CLOCK_IMX6SX_H */
-- 
1.9.1

^ permalink raw reply related	[flat|nested] 19+ messages in thread

* [PATCH V3 1/2] clk: imx6: Add SPDIF_GCLK clock in clock tree
@ 2015-10-19 15:28     ` Michael Turquette
  0 siblings, 0 replies; 19+ messages in thread
From: Michael Turquette @ 2015-10-19 15:28 UTC (permalink / raw)
  To: linux-arm-kernel

Quoting Shengjiu Wang (2015-10-10 03:15:06)
> Correct SPDIF clock setting issue in clock tree, the SPDIF_GCLK is also
> one clock of SPDIF, which is missed before.
> 
> We found an issue that imx can't enter low power mode with spdif
> if IMX6x_CLK_SPDIF is used as the core clock of spdif. Because
> spdif driver will register IMX6x_CLK_SPDIF clock to regmap, regmap will do
> clk_prepare in init function, then IMX6x_CLK_SPDIF clock is prepared in probe,
> so its parent clock (PLL clock) is prepared, the prepare operation of
> PLL clock is to enable the clock. But I.MX needs all PLL clock is disabled,
> then it can enter low power mode.
> 
> So we can't use IMX6x_CLK_SPDIF as the core clock of spdif, the correct spdif
> core clock is SPDIF_GCLK, which share same gate bit with IMX6x_CLK_SPDIF clock.
> SPDIF_GCLK's parent clock is ipg clock.

I'm confused by this. Is there really a new clock signal to be added, or
this just to workaround some reference counting problems with regmap?

> 
> Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>

Please Cc the linux-clk at vger.kernel.org mailing list for future clock
driver patches.

Regards,
Mike

> ---
>  drivers/clk/imx/clk-imx6q.c               | 4 +++-
>  drivers/clk/imx/clk-imx6sl.c              | 4 +++-
>  drivers/clk/imx/clk-imx6sx.c              | 1 +
>  include/dt-bindings/clock/imx6qdl-clock.h | 3 ++-
>  include/dt-bindings/clock/imx6sl-clock.h  | 3 ++-
>  include/dt-bindings/clock/imx6sx-clock.h  | 3 ++-
>  6 files changed, 13 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c
> index e9ba018..c193508 100644
> --- a/drivers/clk/imx/clk-imx6q.c
> +++ b/drivers/clk/imx/clk-imx6q.c
> @@ -119,6 +119,7 @@ static unsigned int share_count_ssi1;
>  static unsigned int share_count_ssi2;
>  static unsigned int share_count_ssi3;
>  static unsigned int share_count_mipi_core_cfg;
> +static unsigned int share_count_spdif;
>  
>  static inline int clk_on_imx6q(void)
>  {
> @@ -462,7 +463,8 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
>         clk[IMX6QDL_CLK_SATA]         = imx_clk_gate2("sata",          "ahb",               base + 0x7c, 4);
>         clk[IMX6QDL_CLK_SDMA]         = imx_clk_gate2("sdma",          "ahb",               base + 0x7c, 6);
>         clk[IMX6QDL_CLK_SPBA]         = imx_clk_gate2("spba",          "ipg",               base + 0x7c, 12);
> -       clk[IMX6QDL_CLK_SPDIF]        = imx_clk_gate2("spdif",         "spdif_podf",        base + 0x7c, 14);
> +       clk[IMX6QDL_CLK_SPDIF]        = imx_clk_gate2_shared("spdif",     "spdif_podf",     base + 0x7c, 14, &share_count_spdif);
> +       clk[IMX6QDL_CLK_SPDIF_GCLK]   = imx_clk_gate2_shared("spdif_gclk", "ipg",           base + 0x7c, 14, &share_count_spdif);
>         clk[IMX6QDL_CLK_SSI1_IPG]     = imx_clk_gate2_shared("ssi1_ipg",      "ipg",        base + 0x7c, 18, &share_count_ssi1);
>         clk[IMX6QDL_CLK_SSI2_IPG]     = imx_clk_gate2_shared("ssi2_ipg",      "ipg",        base + 0x7c, 20, &share_count_ssi2);
>         clk[IMX6QDL_CLK_SSI3_IPG]     = imx_clk_gate2_shared("ssi3_ipg",      "ipg",        base + 0x7c, 22, &share_count_ssi3);
> diff --git a/drivers/clk/imx/clk-imx6sl.c b/drivers/clk/imx/clk-imx6sl.c
> index 3c3333f..1be6230 100644
> --- a/drivers/clk/imx/clk-imx6sl.c
> +++ b/drivers/clk/imx/clk-imx6sl.c
> @@ -97,6 +97,7 @@ static struct clk_div_table video_div_table[] = {
>  static unsigned int share_count_ssi1;
>  static unsigned int share_count_ssi2;
>  static unsigned int share_count_ssi3;
> +static unsigned int share_count_spdif;
>  
>  static struct clk *clks[IMX6SL_CLK_END];
>  static struct clk_onecell_data clk_data;
> @@ -397,7 +398,8 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
>         clks[IMX6SL_CLK_PWM4]         = imx_clk_gate2("pwm4",         "perclk",            base + 0x78, 22);
>         clks[IMX6SL_CLK_SDMA]         = imx_clk_gate2("sdma",         "ipg",               base + 0x7c, 6);
>         clks[IMX6SL_CLK_SPBA]         = imx_clk_gate2("spba",         "ipg",               base + 0x7c, 12);
> -       clks[IMX6SL_CLK_SPDIF]        = imx_clk_gate2("spdif",        "spdif0_podf",       base + 0x7c, 14);
> +       clks[IMX6SL_CLK_SPDIF]        = imx_clk_gate2_shared("spdif",     "spdif0_podf",   base + 0x7c, 14, &share_count_spdif);
> +       clks[IMX6SL_CLK_SPDIF_GCLK]   = imx_clk_gate2_shared("spdif_gclk",  "ipg",         base + 0x7c, 14, &share_count_spdif);
>         clks[IMX6SL_CLK_SSI1_IPG]     = imx_clk_gate2_shared("ssi1_ipg",     "ipg",        base + 0x7c, 18, &share_count_ssi1);
>         clks[IMX6SL_CLK_SSI2_IPG]     = imx_clk_gate2_shared("ssi2_ipg",     "ipg",        base + 0x7c, 20, &share_count_ssi2);
>         clks[IMX6SL_CLK_SSI3_IPG]     = imx_clk_gate2_shared("ssi3_ipg",     "ipg",        base + 0x7c, 22, &share_count_ssi3);
> diff --git a/drivers/clk/imx/clk-imx6sx.c b/drivers/clk/imx/clk-imx6sx.c
> index f0ad8bb..fea125e 100644
> --- a/drivers/clk/imx/clk-imx6sx.c
> +++ b/drivers/clk/imx/clk-imx6sx.c
> @@ -460,6 +460,7 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
>         clks[IMX6SX_CLK_SPBA]         = imx_clk_gate2("spba",          "ipg",               base + 0x7c, 12);
>         clks[IMX6SX_CLK_AUDIO]        = imx_clk_gate2_shared("audio",  "audio_podf",        base + 0x7c, 14, &share_count_audio);
>         clks[IMX6SX_CLK_SPDIF]        = imx_clk_gate2_shared("spdif",  "spdif_podf",        base + 0x7c, 14, &share_count_audio);
> +       clks[IMX6SX_CLK_SPDIF_GCLK]   = imx_clk_gate2_shared("spdif_gclk",    "ipg",        base + 0x7c, 14, &share_count_audio);
>         clks[IMX6SX_CLK_SSI1_IPG]     = imx_clk_gate2_shared("ssi1_ipg",      "ipg",        base + 0x7c, 18, &share_count_ssi1);
>         clks[IMX6SX_CLK_SSI2_IPG]     = imx_clk_gate2_shared("ssi2_ipg",      "ipg",        base + 0x7c, 20, &share_count_ssi2);
>         clks[IMX6SX_CLK_SSI3_IPG]     = imx_clk_gate2_shared("ssi3_ipg",      "ipg",        base + 0x7c, 22, &share_count_ssi3);
> diff --git a/include/dt-bindings/clock/imx6qdl-clock.h b/include/dt-bindings/clock/imx6qdl-clock.h
> index 8de173f..77985cc 100644
> --- a/include/dt-bindings/clock/imx6qdl-clock.h
> +++ b/include/dt-bindings/clock/imx6qdl-clock.h
> @@ -254,6 +254,7 @@
>  #define IMX6QDL_CLK_CAAM_MEM                   241
>  #define IMX6QDL_CLK_CAAM_ACLK                  242
>  #define IMX6QDL_CLK_CAAM_IPG                   243
> -#define IMX6QDL_CLK_END                                244
> +#define IMX6QDL_CLK_SPDIF_GCLK                 244
> +#define IMX6QDL_CLK_END                                245
>  
>  #endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */
> diff --git a/include/dt-bindings/clock/imx6sl-clock.h b/include/dt-bindings/clock/imx6sl-clock.h
> index 9ce4e42..e14573e 100644
> --- a/include/dt-bindings/clock/imx6sl-clock.h
> +++ b/include/dt-bindings/clock/imx6sl-clock.h
> @@ -174,6 +174,7 @@
>  #define IMX6SL_CLK_SSI1_IPG            161
>  #define IMX6SL_CLK_SSI2_IPG            162
>  #define IMX6SL_CLK_SSI3_IPG            163
> -#define IMX6SL_CLK_END                 164
> +#define IMX6SL_CLK_SPDIF_GCLK          164
> +#define IMX6SL_CLK_END                 165
>  
>  #endif /* __DT_BINDINGS_CLOCK_IMX6SL_H */
> diff --git a/include/dt-bindings/clock/imx6sx-clock.h b/include/dt-bindings/clock/imx6sx-clock.h
> index 9957091..36f0324 100644
> --- a/include/dt-bindings/clock/imx6sx-clock.h
> +++ b/include/dt-bindings/clock/imx6sx-clock.h
> @@ -274,6 +274,7 @@
>  #define IMX6SX_PLL5_BYPASS             261
>  #define IMX6SX_PLL6_BYPASS             262
>  #define IMX6SX_PLL7_BYPASS             263
> -#define IMX6SX_CLK_CLK_END             264
> +#define IMX6SX_CLK_SPDIF_GCLK          264
> +#define IMX6SX_CLK_CLK_END             265
>  
>  #endif /* __DT_BINDINGS_CLOCK_IMX6SX_H */
> -- 
> 1.9.1
> 

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH V3 1/2] clk: imx6: Add SPDIF_GCLK clock in clock tree
@ 2015-10-19 15:28     ` Michael Turquette
  0 siblings, 0 replies; 19+ messages in thread
From: Michael Turquette @ 2015-10-19 15:28 UTC (permalink / raw)
  To: Shengjiu Wang, shawnguo, kernel, robh+dt, pawel.moll,
	mark.rutland, ijc+devicetree, galak, linux
  Cc: linux-arm-kernel, devicetree, linux-kernel

Quoting Shengjiu Wang (2015-10-10 03:15:06)
> Correct SPDIF clock setting issue in clock tree, the SPDIF_GCLK is also
> one clock of SPDIF, which is missed before.
> 
> We found an issue that imx can't enter low power mode with spdif
> if IMX6x_CLK_SPDIF is used as the core clock of spdif. Because
> spdif driver will register IMX6x_CLK_SPDIF clock to regmap, regmap will do
> clk_prepare in init function, then IMX6x_CLK_SPDIF clock is prepared in probe,
> so its parent clock (PLL clock) is prepared, the prepare operation of
> PLL clock is to enable the clock. But I.MX needs all PLL clock is disabled,
> then it can enter low power mode.
> 
> So we can't use IMX6x_CLK_SPDIF as the core clock of spdif, the correct spdif
> core clock is SPDIF_GCLK, which share same gate bit with IMX6x_CLK_SPDIF clock.
> SPDIF_GCLK's parent clock is ipg clock.

I'm confused by this. Is there really a new clock signal to be added, or
this just to workaround some reference counting problems with regmap?

> 
> Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>

Please Cc the linux-clk@vger.kernel.org mailing list for future clock
driver patches.

Regards,
Mike

> ---
>  drivers/clk/imx/clk-imx6q.c               | 4 +++-
>  drivers/clk/imx/clk-imx6sl.c              | 4 +++-
>  drivers/clk/imx/clk-imx6sx.c              | 1 +
>  include/dt-bindings/clock/imx6qdl-clock.h | 3 ++-
>  include/dt-bindings/clock/imx6sl-clock.h  | 3 ++-
>  include/dt-bindings/clock/imx6sx-clock.h  | 3 ++-
>  6 files changed, 13 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c
> index e9ba018..c193508 100644
> --- a/drivers/clk/imx/clk-imx6q.c
> +++ b/drivers/clk/imx/clk-imx6q.c
> @@ -119,6 +119,7 @@ static unsigned int share_count_ssi1;
>  static unsigned int share_count_ssi2;
>  static unsigned int share_count_ssi3;
>  static unsigned int share_count_mipi_core_cfg;
> +static unsigned int share_count_spdif;
>  
>  static inline int clk_on_imx6q(void)
>  {
> @@ -462,7 +463,8 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
>         clk[IMX6QDL_CLK_SATA]         = imx_clk_gate2("sata",          "ahb",               base + 0x7c, 4);
>         clk[IMX6QDL_CLK_SDMA]         = imx_clk_gate2("sdma",          "ahb",               base + 0x7c, 6);
>         clk[IMX6QDL_CLK_SPBA]         = imx_clk_gate2("spba",          "ipg",               base + 0x7c, 12);
> -       clk[IMX6QDL_CLK_SPDIF]        = imx_clk_gate2("spdif",         "spdif_podf",        base + 0x7c, 14);
> +       clk[IMX6QDL_CLK_SPDIF]        = imx_clk_gate2_shared("spdif",     "spdif_podf",     base + 0x7c, 14, &share_count_spdif);
> +       clk[IMX6QDL_CLK_SPDIF_GCLK]   = imx_clk_gate2_shared("spdif_gclk", "ipg",           base + 0x7c, 14, &share_count_spdif);
>         clk[IMX6QDL_CLK_SSI1_IPG]     = imx_clk_gate2_shared("ssi1_ipg",      "ipg",        base + 0x7c, 18, &share_count_ssi1);
>         clk[IMX6QDL_CLK_SSI2_IPG]     = imx_clk_gate2_shared("ssi2_ipg",      "ipg",        base + 0x7c, 20, &share_count_ssi2);
>         clk[IMX6QDL_CLK_SSI3_IPG]     = imx_clk_gate2_shared("ssi3_ipg",      "ipg",        base + 0x7c, 22, &share_count_ssi3);
> diff --git a/drivers/clk/imx/clk-imx6sl.c b/drivers/clk/imx/clk-imx6sl.c
> index 3c3333f..1be6230 100644
> --- a/drivers/clk/imx/clk-imx6sl.c
> +++ b/drivers/clk/imx/clk-imx6sl.c
> @@ -97,6 +97,7 @@ static struct clk_div_table video_div_table[] = {
>  static unsigned int share_count_ssi1;
>  static unsigned int share_count_ssi2;
>  static unsigned int share_count_ssi3;
> +static unsigned int share_count_spdif;
>  
>  static struct clk *clks[IMX6SL_CLK_END];
>  static struct clk_onecell_data clk_data;
> @@ -397,7 +398,8 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
>         clks[IMX6SL_CLK_PWM4]         = imx_clk_gate2("pwm4",         "perclk",            base + 0x78, 22);
>         clks[IMX6SL_CLK_SDMA]         = imx_clk_gate2("sdma",         "ipg",               base + 0x7c, 6);
>         clks[IMX6SL_CLK_SPBA]         = imx_clk_gate2("spba",         "ipg",               base + 0x7c, 12);
> -       clks[IMX6SL_CLK_SPDIF]        = imx_clk_gate2("spdif",        "spdif0_podf",       base + 0x7c, 14);
> +       clks[IMX6SL_CLK_SPDIF]        = imx_clk_gate2_shared("spdif",     "spdif0_podf",   base + 0x7c, 14, &share_count_spdif);
> +       clks[IMX6SL_CLK_SPDIF_GCLK]   = imx_clk_gate2_shared("spdif_gclk",  "ipg",         base + 0x7c, 14, &share_count_spdif);
>         clks[IMX6SL_CLK_SSI1_IPG]     = imx_clk_gate2_shared("ssi1_ipg",     "ipg",        base + 0x7c, 18, &share_count_ssi1);
>         clks[IMX6SL_CLK_SSI2_IPG]     = imx_clk_gate2_shared("ssi2_ipg",     "ipg",        base + 0x7c, 20, &share_count_ssi2);
>         clks[IMX6SL_CLK_SSI3_IPG]     = imx_clk_gate2_shared("ssi3_ipg",     "ipg",        base + 0x7c, 22, &share_count_ssi3);
> diff --git a/drivers/clk/imx/clk-imx6sx.c b/drivers/clk/imx/clk-imx6sx.c
> index f0ad8bb..fea125e 100644
> --- a/drivers/clk/imx/clk-imx6sx.c
> +++ b/drivers/clk/imx/clk-imx6sx.c
> @@ -460,6 +460,7 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
>         clks[IMX6SX_CLK_SPBA]         = imx_clk_gate2("spba",          "ipg",               base + 0x7c, 12);
>         clks[IMX6SX_CLK_AUDIO]        = imx_clk_gate2_shared("audio",  "audio_podf",        base + 0x7c, 14, &share_count_audio);
>         clks[IMX6SX_CLK_SPDIF]        = imx_clk_gate2_shared("spdif",  "spdif_podf",        base + 0x7c, 14, &share_count_audio);
> +       clks[IMX6SX_CLK_SPDIF_GCLK]   = imx_clk_gate2_shared("spdif_gclk",    "ipg",        base + 0x7c, 14, &share_count_audio);
>         clks[IMX6SX_CLK_SSI1_IPG]     = imx_clk_gate2_shared("ssi1_ipg",      "ipg",        base + 0x7c, 18, &share_count_ssi1);
>         clks[IMX6SX_CLK_SSI2_IPG]     = imx_clk_gate2_shared("ssi2_ipg",      "ipg",        base + 0x7c, 20, &share_count_ssi2);
>         clks[IMX6SX_CLK_SSI3_IPG]     = imx_clk_gate2_shared("ssi3_ipg",      "ipg",        base + 0x7c, 22, &share_count_ssi3);
> diff --git a/include/dt-bindings/clock/imx6qdl-clock.h b/include/dt-bindings/clock/imx6qdl-clock.h
> index 8de173f..77985cc 100644
> --- a/include/dt-bindings/clock/imx6qdl-clock.h
> +++ b/include/dt-bindings/clock/imx6qdl-clock.h
> @@ -254,6 +254,7 @@
>  #define IMX6QDL_CLK_CAAM_MEM                   241
>  #define IMX6QDL_CLK_CAAM_ACLK                  242
>  #define IMX6QDL_CLK_CAAM_IPG                   243
> -#define IMX6QDL_CLK_END                                244
> +#define IMX6QDL_CLK_SPDIF_GCLK                 244
> +#define IMX6QDL_CLK_END                                245
>  
>  #endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */
> diff --git a/include/dt-bindings/clock/imx6sl-clock.h b/include/dt-bindings/clock/imx6sl-clock.h
> index 9ce4e42..e14573e 100644
> --- a/include/dt-bindings/clock/imx6sl-clock.h
> +++ b/include/dt-bindings/clock/imx6sl-clock.h
> @@ -174,6 +174,7 @@
>  #define IMX6SL_CLK_SSI1_IPG            161
>  #define IMX6SL_CLK_SSI2_IPG            162
>  #define IMX6SL_CLK_SSI3_IPG            163
> -#define IMX6SL_CLK_END                 164
> +#define IMX6SL_CLK_SPDIF_GCLK          164
> +#define IMX6SL_CLK_END                 165
>  
>  #endif /* __DT_BINDINGS_CLOCK_IMX6SL_H */
> diff --git a/include/dt-bindings/clock/imx6sx-clock.h b/include/dt-bindings/clock/imx6sx-clock.h
> index 9957091..36f0324 100644
> --- a/include/dt-bindings/clock/imx6sx-clock.h
> +++ b/include/dt-bindings/clock/imx6sx-clock.h
> @@ -274,6 +274,7 @@
>  #define IMX6SX_PLL5_BYPASS             261
>  #define IMX6SX_PLL6_BYPASS             262
>  #define IMX6SX_PLL7_BYPASS             263
> -#define IMX6SX_CLK_CLK_END             264
> +#define IMX6SX_CLK_SPDIF_GCLK          264
> +#define IMX6SX_CLK_CLK_END             265
>  
>  #endif /* __DT_BINDINGS_CLOCK_IMX6SX_H */
> -- 
> 1.9.1
> 

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH V3 1/2] clk: imx6: Add SPDIF_GCLK clock in clock tree
@ 2015-10-19 15:28     ` Michael Turquette
  0 siblings, 0 replies; 19+ messages in thread
From: Michael Turquette @ 2015-10-19 15:28 UTC (permalink / raw)
  To: Shengjiu Wang, shawnguo-DgEjT+Ai2ygdnm+yROfE0A,
	kernel-bIcnvbaLZ9MEGnE8C9+IrQ, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
	pawel.moll-5wv7dgnIgG8, mark.rutland-5wv7dgnIgG8,
	ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
	galak-sgV2jX0FEOL9JmXXK+q4OQ, linux-lFZ/pmaqli7XmaaqVzeoHQ
  Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	devicetree-u79uwXL29TY76Z2rM5mHXA,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA

Quoting Shengjiu Wang (2015-10-10 03:15:06)
> Correct SPDIF clock setting issue in clock tree, the SPDIF_GCLK is also
> one clock of SPDIF, which is missed before.
> 
> We found an issue that imx can't enter low power mode with spdif
> if IMX6x_CLK_SPDIF is used as the core clock of spdif. Because
> spdif driver will register IMX6x_CLK_SPDIF clock to regmap, regmap will do
> clk_prepare in init function, then IMX6x_CLK_SPDIF clock is prepared in probe,
> so its parent clock (PLL clock) is prepared, the prepare operation of
> PLL clock is to enable the clock. But I.MX needs all PLL clock is disabled,
> then it can enter low power mode.
> 
> So we can't use IMX6x_CLK_SPDIF as the core clock of spdif, the correct spdif
> core clock is SPDIF_GCLK, which share same gate bit with IMX6x_CLK_SPDIF clock.
> SPDIF_GCLK's parent clock is ipg clock.

I'm confused by this. Is there really a new clock signal to be added, or
this just to workaround some reference counting problems with regmap?

> 
> Signed-off-by: Shengjiu Wang <shengjiu.wang-KZfg59tc24xl57MIdRCFDg@public.gmane.org>

Please Cc the linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org mailing list for future clock
driver patches.

Regards,
Mike

> ---
>  drivers/clk/imx/clk-imx6q.c               | 4 +++-
>  drivers/clk/imx/clk-imx6sl.c              | 4 +++-
>  drivers/clk/imx/clk-imx6sx.c              | 1 +
>  include/dt-bindings/clock/imx6qdl-clock.h | 3 ++-
>  include/dt-bindings/clock/imx6sl-clock.h  | 3 ++-
>  include/dt-bindings/clock/imx6sx-clock.h  | 3 ++-
>  6 files changed, 13 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c
> index e9ba018..c193508 100644
> --- a/drivers/clk/imx/clk-imx6q.c
> +++ b/drivers/clk/imx/clk-imx6q.c
> @@ -119,6 +119,7 @@ static unsigned int share_count_ssi1;
>  static unsigned int share_count_ssi2;
>  static unsigned int share_count_ssi3;
>  static unsigned int share_count_mipi_core_cfg;
> +static unsigned int share_count_spdif;
>  
>  static inline int clk_on_imx6q(void)
>  {
> @@ -462,7 +463,8 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
>         clk[IMX6QDL_CLK_SATA]         = imx_clk_gate2("sata",          "ahb",               base + 0x7c, 4);
>         clk[IMX6QDL_CLK_SDMA]         = imx_clk_gate2("sdma",          "ahb",               base + 0x7c, 6);
>         clk[IMX6QDL_CLK_SPBA]         = imx_clk_gate2("spba",          "ipg",               base + 0x7c, 12);
> -       clk[IMX6QDL_CLK_SPDIF]        = imx_clk_gate2("spdif",         "spdif_podf",        base + 0x7c, 14);
> +       clk[IMX6QDL_CLK_SPDIF]        = imx_clk_gate2_shared("spdif",     "spdif_podf",     base + 0x7c, 14, &share_count_spdif);
> +       clk[IMX6QDL_CLK_SPDIF_GCLK]   = imx_clk_gate2_shared("spdif_gclk", "ipg",           base + 0x7c, 14, &share_count_spdif);
>         clk[IMX6QDL_CLK_SSI1_IPG]     = imx_clk_gate2_shared("ssi1_ipg",      "ipg",        base + 0x7c, 18, &share_count_ssi1);
>         clk[IMX6QDL_CLK_SSI2_IPG]     = imx_clk_gate2_shared("ssi2_ipg",      "ipg",        base + 0x7c, 20, &share_count_ssi2);
>         clk[IMX6QDL_CLK_SSI3_IPG]     = imx_clk_gate2_shared("ssi3_ipg",      "ipg",        base + 0x7c, 22, &share_count_ssi3);
> diff --git a/drivers/clk/imx/clk-imx6sl.c b/drivers/clk/imx/clk-imx6sl.c
> index 3c3333f..1be6230 100644
> --- a/drivers/clk/imx/clk-imx6sl.c
> +++ b/drivers/clk/imx/clk-imx6sl.c
> @@ -97,6 +97,7 @@ static struct clk_div_table video_div_table[] = {
>  static unsigned int share_count_ssi1;
>  static unsigned int share_count_ssi2;
>  static unsigned int share_count_ssi3;
> +static unsigned int share_count_spdif;
>  
>  static struct clk *clks[IMX6SL_CLK_END];
>  static struct clk_onecell_data clk_data;
> @@ -397,7 +398,8 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
>         clks[IMX6SL_CLK_PWM4]         = imx_clk_gate2("pwm4",         "perclk",            base + 0x78, 22);
>         clks[IMX6SL_CLK_SDMA]         = imx_clk_gate2("sdma",         "ipg",               base + 0x7c, 6);
>         clks[IMX6SL_CLK_SPBA]         = imx_clk_gate2("spba",         "ipg",               base + 0x7c, 12);
> -       clks[IMX6SL_CLK_SPDIF]        = imx_clk_gate2("spdif",        "spdif0_podf",       base + 0x7c, 14);
> +       clks[IMX6SL_CLK_SPDIF]        = imx_clk_gate2_shared("spdif",     "spdif0_podf",   base + 0x7c, 14, &share_count_spdif);
> +       clks[IMX6SL_CLK_SPDIF_GCLK]   = imx_clk_gate2_shared("spdif_gclk",  "ipg",         base + 0x7c, 14, &share_count_spdif);
>         clks[IMX6SL_CLK_SSI1_IPG]     = imx_clk_gate2_shared("ssi1_ipg",     "ipg",        base + 0x7c, 18, &share_count_ssi1);
>         clks[IMX6SL_CLK_SSI2_IPG]     = imx_clk_gate2_shared("ssi2_ipg",     "ipg",        base + 0x7c, 20, &share_count_ssi2);
>         clks[IMX6SL_CLK_SSI3_IPG]     = imx_clk_gate2_shared("ssi3_ipg",     "ipg",        base + 0x7c, 22, &share_count_ssi3);
> diff --git a/drivers/clk/imx/clk-imx6sx.c b/drivers/clk/imx/clk-imx6sx.c
> index f0ad8bb..fea125e 100644
> --- a/drivers/clk/imx/clk-imx6sx.c
> +++ b/drivers/clk/imx/clk-imx6sx.c
> @@ -460,6 +460,7 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
>         clks[IMX6SX_CLK_SPBA]         = imx_clk_gate2("spba",          "ipg",               base + 0x7c, 12);
>         clks[IMX6SX_CLK_AUDIO]        = imx_clk_gate2_shared("audio",  "audio_podf",        base + 0x7c, 14, &share_count_audio);
>         clks[IMX6SX_CLK_SPDIF]        = imx_clk_gate2_shared("spdif",  "spdif_podf",        base + 0x7c, 14, &share_count_audio);
> +       clks[IMX6SX_CLK_SPDIF_GCLK]   = imx_clk_gate2_shared("spdif_gclk",    "ipg",        base + 0x7c, 14, &share_count_audio);
>         clks[IMX6SX_CLK_SSI1_IPG]     = imx_clk_gate2_shared("ssi1_ipg",      "ipg",        base + 0x7c, 18, &share_count_ssi1);
>         clks[IMX6SX_CLK_SSI2_IPG]     = imx_clk_gate2_shared("ssi2_ipg",      "ipg",        base + 0x7c, 20, &share_count_ssi2);
>         clks[IMX6SX_CLK_SSI3_IPG]     = imx_clk_gate2_shared("ssi3_ipg",      "ipg",        base + 0x7c, 22, &share_count_ssi3);
> diff --git a/include/dt-bindings/clock/imx6qdl-clock.h b/include/dt-bindings/clock/imx6qdl-clock.h
> index 8de173f..77985cc 100644
> --- a/include/dt-bindings/clock/imx6qdl-clock.h
> +++ b/include/dt-bindings/clock/imx6qdl-clock.h
> @@ -254,6 +254,7 @@
>  #define IMX6QDL_CLK_CAAM_MEM                   241
>  #define IMX6QDL_CLK_CAAM_ACLK                  242
>  #define IMX6QDL_CLK_CAAM_IPG                   243
> -#define IMX6QDL_CLK_END                                244
> +#define IMX6QDL_CLK_SPDIF_GCLK                 244
> +#define IMX6QDL_CLK_END                                245
>  
>  #endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */
> diff --git a/include/dt-bindings/clock/imx6sl-clock.h b/include/dt-bindings/clock/imx6sl-clock.h
> index 9ce4e42..e14573e 100644
> --- a/include/dt-bindings/clock/imx6sl-clock.h
> +++ b/include/dt-bindings/clock/imx6sl-clock.h
> @@ -174,6 +174,7 @@
>  #define IMX6SL_CLK_SSI1_IPG            161
>  #define IMX6SL_CLK_SSI2_IPG            162
>  #define IMX6SL_CLK_SSI3_IPG            163
> -#define IMX6SL_CLK_END                 164
> +#define IMX6SL_CLK_SPDIF_GCLK          164
> +#define IMX6SL_CLK_END                 165
>  
>  #endif /* __DT_BINDINGS_CLOCK_IMX6SL_H */
> diff --git a/include/dt-bindings/clock/imx6sx-clock.h b/include/dt-bindings/clock/imx6sx-clock.h
> index 9957091..36f0324 100644
> --- a/include/dt-bindings/clock/imx6sx-clock.h
> +++ b/include/dt-bindings/clock/imx6sx-clock.h
> @@ -274,6 +274,7 @@
>  #define IMX6SX_PLL5_BYPASS             261
>  #define IMX6SX_PLL6_BYPASS             262
>  #define IMX6SX_PLL7_BYPASS             263
> -#define IMX6SX_CLK_CLK_END             264
> +#define IMX6SX_CLK_SPDIF_GCLK          264
> +#define IMX6SX_CLK_CLK_END             265
>  
>  #endif /* __DT_BINDINGS_CLOCK_IMX6SX_H */
> -- 
> 1.9.1
> 
--
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^ permalink raw reply	[flat|nested] 19+ messages in thread

* [PATCH V3 1/2] clk: imx6: Add SPDIF_GCLK clock in clock tree
  2015-10-19 15:28     ` Michael Turquette
  (?)
@ 2015-10-19 15:36       ` Shawn Guo
  -1 siblings, 0 replies; 19+ messages in thread
From: Shawn Guo @ 2015-10-19 15:36 UTC (permalink / raw)
  To: linux-arm-kernel

Hi Mike,

On Mon, Oct 19, 2015 at 08:28:07AM -0700, Michael Turquette wrote:
> Quoting Shengjiu Wang (2015-10-10 03:15:06)
> > Correct SPDIF clock setting issue in clock tree, the SPDIF_GCLK is also
> > one clock of SPDIF, which is missed before.
> > 
> > We found an issue that imx can't enter low power mode with spdif
> > if IMX6x_CLK_SPDIF is used as the core clock of spdif. Because
> > spdif driver will register IMX6x_CLK_SPDIF clock to regmap, regmap will do
> > clk_prepare in init function, then IMX6x_CLK_SPDIF clock is prepared in probe,
> > so its parent clock (PLL clock) is prepared, the prepare operation of
> > PLL clock is to enable the clock. But I.MX needs all PLL clock is disabled,
> > then it can enter low power mode.
> > 
> > So we can't use IMX6x_CLK_SPDIF as the core clock of spdif, the correct spdif
> > core clock is SPDIF_GCLK, which share same gate bit with IMX6x_CLK_SPDIF clock.
> > SPDIF_GCLK's parent clock is ipg clock.
> 
> I'm confused by this. Is there really a new clock signal to be added, or
> this just to workaround some reference counting problems with regmap?

I was confused by the previous version of the patch, and asked Shengjiu
to improve the commit log, which seems still not so good.  In short, the
patch does add a missing clock, and the missing of the clock is
discovered by a low-power-mode issue when SPDIF driver is enabled.

> 
> > 
> > Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
> 
> Please Cc the linux-clk at vger.kernel.org mailing list for future clock
> driver patches.

Right, should have reminded him.  I will keep my eyes more closely on
this.

Shawn

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH V3 1/2] clk: imx6: Add SPDIF_GCLK clock in clock tree
@ 2015-10-19 15:36       ` Shawn Guo
  0 siblings, 0 replies; 19+ messages in thread
From: Shawn Guo @ 2015-10-19 15:36 UTC (permalink / raw)
  To: Michael Turquette
  Cc: Shengjiu Wang, kernel, robh+dt, pawel.moll, mark.rutland,
	ijc+devicetree, galak, linux, linux-arm-kernel, devicetree,
	linux-kernel

Hi Mike,

On Mon, Oct 19, 2015 at 08:28:07AM -0700, Michael Turquette wrote:
> Quoting Shengjiu Wang (2015-10-10 03:15:06)
> > Correct SPDIF clock setting issue in clock tree, the SPDIF_GCLK is also
> > one clock of SPDIF, which is missed before.
> > 
> > We found an issue that imx can't enter low power mode with spdif
> > if IMX6x_CLK_SPDIF is used as the core clock of spdif. Because
> > spdif driver will register IMX6x_CLK_SPDIF clock to regmap, regmap will do
> > clk_prepare in init function, then IMX6x_CLK_SPDIF clock is prepared in probe,
> > so its parent clock (PLL clock) is prepared, the prepare operation of
> > PLL clock is to enable the clock. But I.MX needs all PLL clock is disabled,
> > then it can enter low power mode.
> > 
> > So we can't use IMX6x_CLK_SPDIF as the core clock of spdif, the correct spdif
> > core clock is SPDIF_GCLK, which share same gate bit with IMX6x_CLK_SPDIF clock.
> > SPDIF_GCLK's parent clock is ipg clock.
> 
> I'm confused by this. Is there really a new clock signal to be added, or
> this just to workaround some reference counting problems with regmap?

I was confused by the previous version of the patch, and asked Shengjiu
to improve the commit log, which seems still not so good.  In short, the
patch does add a missing clock, and the missing of the clock is
discovered by a low-power-mode issue when SPDIF driver is enabled.

> 
> > 
> > Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
> 
> Please Cc the linux-clk@vger.kernel.org mailing list for future clock
> driver patches.

Right, should have reminded him.  I will keep my eyes more closely on
this.

Shawn

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH V3 1/2] clk: imx6: Add SPDIF_GCLK clock in clock tree
@ 2015-10-19 15:36       ` Shawn Guo
  0 siblings, 0 replies; 19+ messages in thread
From: Shawn Guo @ 2015-10-19 15:36 UTC (permalink / raw)
  To: Michael Turquette
  Cc: mark.rutland, devicetree, Shengjiu Wang, linux, pawel.moll,
	ijc+devicetree, linux-kernel, robh+dt, kernel, galak,
	linux-arm-kernel

Hi Mike,

On Mon, Oct 19, 2015 at 08:28:07AM -0700, Michael Turquette wrote:
> Quoting Shengjiu Wang (2015-10-10 03:15:06)
> > Correct SPDIF clock setting issue in clock tree, the SPDIF_GCLK is also
> > one clock of SPDIF, which is missed before.
> > 
> > We found an issue that imx can't enter low power mode with spdif
> > if IMX6x_CLK_SPDIF is used as the core clock of spdif. Because
> > spdif driver will register IMX6x_CLK_SPDIF clock to regmap, regmap will do
> > clk_prepare in init function, then IMX6x_CLK_SPDIF clock is prepared in probe,
> > so its parent clock (PLL clock) is prepared, the prepare operation of
> > PLL clock is to enable the clock. But I.MX needs all PLL clock is disabled,
> > then it can enter low power mode.
> > 
> > So we can't use IMX6x_CLK_SPDIF as the core clock of spdif, the correct spdif
> > core clock is SPDIF_GCLK, which share same gate bit with IMX6x_CLK_SPDIF clock.
> > SPDIF_GCLK's parent clock is ipg clock.
> 
> I'm confused by this. Is there really a new clock signal to be added, or
> this just to workaround some reference counting problems with regmap?

I was confused by the previous version of the patch, and asked Shengjiu
to improve the commit log, which seems still not so good.  In short, the
patch does add a missing clock, and the missing of the clock is
discovered by a low-power-mode issue when SPDIF driver is enabled.

> 
> > 
> > Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
> 
> Please Cc the linux-clk@vger.kernel.org mailing list for future clock
> driver patches.

Right, should have reminded him.  I will keep my eyes more closely on
this.

Shawn

^ permalink raw reply	[flat|nested] 19+ messages in thread

* [PATCH V3 1/2] clk: imx6: Add SPDIF_GCLK clock in clock tree
  2015-10-19 15:36       ` Shawn Guo
@ 2015-10-20 10:23         ` Michael Turquette
  -1 siblings, 0 replies; 19+ messages in thread
From: Michael Turquette @ 2015-10-20 10:23 UTC (permalink / raw)
  To: linux-arm-kernel

Hi Shawn,

Quoting Shawn Guo (2015-10-19 08:36:18)
> Hi Mike,
> 
> On Mon, Oct 19, 2015 at 08:28:07AM -0700, Michael Turquette wrote:
> > Quoting Shengjiu Wang (2015-10-10 03:15:06)
> > > Correct SPDIF clock setting issue in clock tree, the SPDIF_GCLK is also
> > > one clock of SPDIF, which is missed before.
> > > 
> > > We found an issue that imx can't enter low power mode with spdif
> > > if IMX6x_CLK_SPDIF is used as the core clock of spdif. Because
> > > spdif driver will register IMX6x_CLK_SPDIF clock to regmap, regmap will do
> > > clk_prepare in init function, then IMX6x_CLK_SPDIF clock is prepared in probe,
> > > so its parent clock (PLL clock) is prepared, the prepare operation of
> > > PLL clock is to enable the clock. But I.MX needs all PLL clock is disabled,
> > > then it can enter low power mode.
> > > 
> > > So we can't use IMX6x_CLK_SPDIF as the core clock of spdif, the correct spdif
> > > core clock is SPDIF_GCLK, which share same gate bit with IMX6x_CLK_SPDIF clock.
> > > SPDIF_GCLK's parent clock is ipg clock.
> > 
> > I'm confused by this. Is there really a new clock signal to be added, or
> > this just to workaround some reference counting problems with regmap?
> 
> I was confused by the previous version of the patch, and asked Shengjiu
> to improve the commit log, which seems still not so good.  In short, the
> patch does add a missing clock, and the missing of the clock is
> discovered by a low-power-mode issue when SPDIF driver is enabled.

Thank you for the explanation. Sounds good to me.

Regards,
Mike

> 
> > 
> > > 
> > > Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
> > 
> > Please Cc the linux-clk at vger.kernel.org mailing list for future clock
> > driver patches.
> 
> Right, should have reminded him.  I will keep my eyes more closely on
> this.
> 
> Shawn

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH V3 1/2] clk: imx6: Add SPDIF_GCLK clock in clock tree
@ 2015-10-20 10:23         ` Michael Turquette
  0 siblings, 0 replies; 19+ messages in thread
From: Michael Turquette @ 2015-10-20 10:23 UTC (permalink / raw)
  To: Shawn Guo
  Cc: mark.rutland, devicetree, Shengjiu Wang, linux, pawel.moll,
	ijc+devicetree, linux-kernel, robh+dt, kernel, galak,
	linux-arm-kernel

Hi Shawn,

Quoting Shawn Guo (2015-10-19 08:36:18)
> Hi Mike,
> 
> On Mon, Oct 19, 2015 at 08:28:07AM -0700, Michael Turquette wrote:
> > Quoting Shengjiu Wang (2015-10-10 03:15:06)
> > > Correct SPDIF clock setting issue in clock tree, the SPDIF_GCLK is also
> > > one clock of SPDIF, which is missed before.
> > > 
> > > We found an issue that imx can't enter low power mode with spdif
> > > if IMX6x_CLK_SPDIF is used as the core clock of spdif. Because
> > > spdif driver will register IMX6x_CLK_SPDIF clock to regmap, regmap will do
> > > clk_prepare in init function, then IMX6x_CLK_SPDIF clock is prepared in probe,
> > > so its parent clock (PLL clock) is prepared, the prepare operation of
> > > PLL clock is to enable the clock. But I.MX needs all PLL clock is disabled,
> > > then it can enter low power mode.
> > > 
> > > So we can't use IMX6x_CLK_SPDIF as the core clock of spdif, the correct spdif
> > > core clock is SPDIF_GCLK, which share same gate bit with IMX6x_CLK_SPDIF clock.
> > > SPDIF_GCLK's parent clock is ipg clock.
> > 
> > I'm confused by this. Is there really a new clock signal to be added, or
> > this just to workaround some reference counting problems with regmap?
> 
> I was confused by the previous version of the patch, and asked Shengjiu
> to improve the commit log, which seems still not so good.  In short, the
> patch does add a missing clock, and the missing of the clock is
> discovered by a low-power-mode issue when SPDIF driver is enabled.

Thank you for the explanation. Sounds good to me.

Regards,
Mike

> 
> > 
> > > 
> > > Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
> > 
> > Please Cc the linux-clk@vger.kernel.org mailing list for future clock
> > driver patches.
> 
> Right, should have reminded him.  I will keep my eyes more closely on
> this.
> 
> Shawn

^ permalink raw reply	[flat|nested] 19+ messages in thread

* [PATCH V3 2/2] ARM: dts: imx6: change the core clock of spdif
  2015-10-10 10:15 ` Shengjiu Wang
  (?)
@ 2015-10-10 10:15   ` Shengjiu Wang
  -1 siblings, 0 replies; 19+ messages in thread
From: Shengjiu Wang @ 2015-10-10 10:15 UTC (permalink / raw)
  To: linux-arm-kernel

The correct core clock of spdif is SPDIF_GCLK, which is added to
clock tree. So the dts also need to be updated.

Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
---
 arch/arm/boot/dts/imx6qdl.dtsi | 12 ++++++------
 arch/arm/boot/dts/imx6sl.dtsi  | 16 ++++++++++++++++
 arch/arm/boot/dts/imx6sx.dtsi  |  2 +-
 3 files changed, 23 insertions(+), 7 deletions(-)

diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index e716e6f..2b6cc8b 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -218,16 +218,16 @@
 					dmas = <&sdma 14 18 0>,
 					       <&sdma 15 18 0>;
 					dma-names = "rx", "tx";
-					clocks = <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_OSC>,
-						 <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_DUMMY>,
-						 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_DUMMY>,
-						 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_DUMMY>,
-						 <&clks IMX6QDL_CLK_DUMMY>;
+					clocks = <&clks IMX6QDL_CLK_SPDIF_GCLK>, <&clks IMX6QDL_CLK_OSC>,
+						 <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_ASRC>,
+						 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_ESAI_EXTAL>,
+						 <&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_MLB>,
+						 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_SPBA>;
 					clock-names = "core",  "rxtx0",
 						      "rxtx1", "rxtx2",
 						      "rxtx3", "rxtx4",
 						      "rxtx5", "rxtx6",
-						      "rxtx7";
+						      "rxtx7", "dma";
 					status = "disabled";
 				};
 
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index ebe8670..d8ba99f 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -135,8 +135,24 @@
 				ranges;
 
 				spdif: spdif at 02004000 {
+					compatible = "fsl,imx6sl-spdif",
+						"fsl,imx35-spdif";
 					reg = <0x02004000 0x4000>;
 					interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&sdma 14 18 0>,
+						<&sdma 15 18 0>;
+					dma-names = "rx", "tx";
+					clocks = <&clks IMX6SL_CLK_SPDIF_GCLK>, <&clks IMX6SL_CLK_OSC>,
+						 <&clks IMX6SL_CLK_SPDIF>, <&clks IMX6SL_CLK_DUMMY>,
+						 <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_DUMMY>,
+						 <&clks IMX6SL_CLK_IPG>, <&clks IMX6SL_CLK_DUMMY>,
+						 <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_SPBA>;
+					clock-names = "core", "rxtx0",
+						"rxtx1", "rxtx2",
+						"rxtx3", "rxtx4",
+						"rxtx5", "rxtx6",
+						"rxtx7", "dma";
+					status = "disabled";
 				};
 
 				ecspi1: ecspi at 02008000 {
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index c94f2ea..167f77b 100644
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -211,7 +211,7 @@
 					dmas = <&sdma 14 18 0>,
 					       <&sdma 15 18 0>;
 					dma-names = "rx", "tx";
-					clocks = <&clks IMX6SX_CLK_SPDIF>,
+					clocks = <&clks IMX6SX_CLK_SPDIF_GCLK>,
 						 <&clks IMX6SX_CLK_OSC>,
 						 <&clks IMX6SX_CLK_SPDIF>,
 						 <&clks 0>, <&clks 0>, <&clks 0>,
-- 
1.9.1

^ permalink raw reply related	[flat|nested] 19+ messages in thread

* [PATCH V3 2/2] ARM: dts: imx6: change the core clock of spdif
@ 2015-10-10 10:15   ` Shengjiu Wang
  0 siblings, 0 replies; 19+ messages in thread
From: Shengjiu Wang @ 2015-10-10 10:15 UTC (permalink / raw)
  To: shawnguo, kernel, robh+dt, pawel.moll, mark.rutland,
	ijc+devicetree, galak, linux, mturquette
  Cc: linux-arm-kernel, devicetree, linux-kernel

The correct core clock of spdif is SPDIF_GCLK, which is added to
clock tree. So the dts also need to be updated.

Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
---
 arch/arm/boot/dts/imx6qdl.dtsi | 12 ++++++------
 arch/arm/boot/dts/imx6sl.dtsi  | 16 ++++++++++++++++
 arch/arm/boot/dts/imx6sx.dtsi  |  2 +-
 3 files changed, 23 insertions(+), 7 deletions(-)

diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index e716e6f..2b6cc8b 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -218,16 +218,16 @@
 					dmas = <&sdma 14 18 0>,
 					       <&sdma 15 18 0>;
 					dma-names = "rx", "tx";
-					clocks = <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_OSC>,
-						 <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_DUMMY>,
-						 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_DUMMY>,
-						 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_DUMMY>,
-						 <&clks IMX6QDL_CLK_DUMMY>;
+					clocks = <&clks IMX6QDL_CLK_SPDIF_GCLK>, <&clks IMX6QDL_CLK_OSC>,
+						 <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_ASRC>,
+						 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_ESAI_EXTAL>,
+						 <&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_MLB>,
+						 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_SPBA>;
 					clock-names = "core",  "rxtx0",
 						      "rxtx1", "rxtx2",
 						      "rxtx3", "rxtx4",
 						      "rxtx5", "rxtx6",
-						      "rxtx7";
+						      "rxtx7", "dma";
 					status = "disabled";
 				};
 
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index ebe8670..d8ba99f 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -135,8 +135,24 @@
 				ranges;
 
 				spdif: spdif@02004000 {
+					compatible = "fsl,imx6sl-spdif",
+						"fsl,imx35-spdif";
 					reg = <0x02004000 0x4000>;
 					interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&sdma 14 18 0>,
+						<&sdma 15 18 0>;
+					dma-names = "rx", "tx";
+					clocks = <&clks IMX6SL_CLK_SPDIF_GCLK>, <&clks IMX6SL_CLK_OSC>,
+						 <&clks IMX6SL_CLK_SPDIF>, <&clks IMX6SL_CLK_DUMMY>,
+						 <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_DUMMY>,
+						 <&clks IMX6SL_CLK_IPG>, <&clks IMX6SL_CLK_DUMMY>,
+						 <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_SPBA>;
+					clock-names = "core", "rxtx0",
+						"rxtx1", "rxtx2",
+						"rxtx3", "rxtx4",
+						"rxtx5", "rxtx6",
+						"rxtx7", "dma";
+					status = "disabled";
 				};
 
 				ecspi1: ecspi@02008000 {
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index c94f2ea..167f77b 100644
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -211,7 +211,7 @@
 					dmas = <&sdma 14 18 0>,
 					       <&sdma 15 18 0>;
 					dma-names = "rx", "tx";
-					clocks = <&clks IMX6SX_CLK_SPDIF>,
+					clocks = <&clks IMX6SX_CLK_SPDIF_GCLK>,
 						 <&clks IMX6SX_CLK_OSC>,
 						 <&clks IMX6SX_CLK_SPDIF>,
 						 <&clks 0>, <&clks 0>, <&clks 0>,
-- 
1.9.1


^ permalink raw reply related	[flat|nested] 19+ messages in thread

* [PATCH V3 2/2] ARM: dts: imx6: change the core clock of spdif
@ 2015-10-10 10:15   ` Shengjiu Wang
  0 siblings, 0 replies; 19+ messages in thread
From: Shengjiu Wang @ 2015-10-10 10:15 UTC (permalink / raw)
  To: shawnguo, kernel, robh+dt, pawel.moll, mark.rutland,
	ijc+devicetree, galak, linux, mturquette
  Cc: linux-arm-kernel, devicetree, linux-kernel

The correct core clock of spdif is SPDIF_GCLK, which is added to
clock tree. So the dts also need to be updated.

Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
---
 arch/arm/boot/dts/imx6qdl.dtsi | 12 ++++++------
 arch/arm/boot/dts/imx6sl.dtsi  | 16 ++++++++++++++++
 arch/arm/boot/dts/imx6sx.dtsi  |  2 +-
 3 files changed, 23 insertions(+), 7 deletions(-)

diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index e716e6f..2b6cc8b 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -218,16 +218,16 @@
 					dmas = <&sdma 14 18 0>,
 					       <&sdma 15 18 0>;
 					dma-names = "rx", "tx";
-					clocks = <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_OSC>,
-						 <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_DUMMY>,
-						 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_DUMMY>,
-						 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_DUMMY>,
-						 <&clks IMX6QDL_CLK_DUMMY>;
+					clocks = <&clks IMX6QDL_CLK_SPDIF_GCLK>, <&clks IMX6QDL_CLK_OSC>,
+						 <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_ASRC>,
+						 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_ESAI_EXTAL>,
+						 <&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_MLB>,
+						 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_SPBA>;
 					clock-names = "core",  "rxtx0",
 						      "rxtx1", "rxtx2",
 						      "rxtx3", "rxtx4",
 						      "rxtx5", "rxtx6",
-						      "rxtx7";
+						      "rxtx7", "dma";
 					status = "disabled";
 				};
 
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index ebe8670..d8ba99f 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -135,8 +135,24 @@
 				ranges;
 
 				spdif: spdif@02004000 {
+					compatible = "fsl,imx6sl-spdif",
+						"fsl,imx35-spdif";
 					reg = <0x02004000 0x4000>;
 					interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&sdma 14 18 0>,
+						<&sdma 15 18 0>;
+					dma-names = "rx", "tx";
+					clocks = <&clks IMX6SL_CLK_SPDIF_GCLK>, <&clks IMX6SL_CLK_OSC>,
+						 <&clks IMX6SL_CLK_SPDIF>, <&clks IMX6SL_CLK_DUMMY>,
+						 <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_DUMMY>,
+						 <&clks IMX6SL_CLK_IPG>, <&clks IMX6SL_CLK_DUMMY>,
+						 <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_SPBA>;
+					clock-names = "core", "rxtx0",
+						"rxtx1", "rxtx2",
+						"rxtx3", "rxtx4",
+						"rxtx5", "rxtx6",
+						"rxtx7", "dma";
+					status = "disabled";
 				};
 
 				ecspi1: ecspi@02008000 {
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index c94f2ea..167f77b 100644
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -211,7 +211,7 @@
 					dmas = <&sdma 14 18 0>,
 					       <&sdma 15 18 0>;
 					dma-names = "rx", "tx";
-					clocks = <&clks IMX6SX_CLK_SPDIF>,
+					clocks = <&clks IMX6SX_CLK_SPDIF_GCLK>,
 						 <&clks IMX6SX_CLK_OSC>,
 						 <&clks IMX6SX_CLK_SPDIF>,
 						 <&clks 0>, <&clks 0>, <&clks 0>,
-- 
1.9.1

^ permalink raw reply related	[flat|nested] 19+ messages in thread

* [PATCH V3 0/2] Add SPDIF_GCLK clock in clock tree for imx6
  2015-10-10 10:15 ` Shengjiu Wang
@ 2015-10-12 14:01   ` Shawn Guo
  -1 siblings, 0 replies; 19+ messages in thread
From: Shawn Guo @ 2015-10-12 14:01 UTC (permalink / raw)
  To: linux-arm-kernel

On Sat, Oct 10, 2015 at 06:15:05PM +0800, Shengjiu Wang wrote:
> Shengjiu Wang (2):
>   clk: imx6: Add SPDIF_GCLK clock in clock tree
>   ARM: dts: imx6: change the core clock of spdif

Applied both, thanks.

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH V3 0/2] Add SPDIF_GCLK clock in clock tree for imx6
@ 2015-10-12 14:01   ` Shawn Guo
  0 siblings, 0 replies; 19+ messages in thread
From: Shawn Guo @ 2015-10-12 14:01 UTC (permalink / raw)
  To: Shengjiu Wang
  Cc: kernel, robh+dt, pawel.moll, mark.rutland, ijc+devicetree, galak,
	linux, mturquette, linux-arm-kernel, devicetree, linux-kernel

On Sat, Oct 10, 2015 at 06:15:05PM +0800, Shengjiu Wang wrote:
> Shengjiu Wang (2):
>   clk: imx6: Add SPDIF_GCLK clock in clock tree
>   ARM: dts: imx6: change the core clock of spdif

Applied both, thanks.

^ permalink raw reply	[flat|nested] 19+ messages in thread

end of thread, other threads:[~2015-10-20 10:23 UTC | newest]

Thread overview: 19+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2015-10-10 10:15 [PATCH V3 0/2] Add SPDIF_GCLK clock in clock tree for imx6 Shengjiu Wang
2015-10-10 10:15 ` Shengjiu Wang
2015-10-10 10:15 ` Shengjiu Wang
2015-10-10 10:15 ` [PATCH V3 1/2] clk: imx6: Add SPDIF_GCLK clock in clock tree Shengjiu Wang
2015-10-10 10:15   ` Shengjiu Wang
2015-10-10 10:15   ` Shengjiu Wang
2015-10-19 15:28   ` Michael Turquette
2015-10-19 15:28     ` Michael Turquette
2015-10-19 15:28     ` Michael Turquette
2015-10-19 15:36     ` Shawn Guo
2015-10-19 15:36       ` Shawn Guo
2015-10-19 15:36       ` Shawn Guo
2015-10-20 10:23       ` Michael Turquette
2015-10-20 10:23         ` Michael Turquette
2015-10-10 10:15 ` [PATCH V3 2/2] ARM: dts: imx6: change the core clock of spdif Shengjiu Wang
2015-10-10 10:15   ` Shengjiu Wang
2015-10-10 10:15   ` Shengjiu Wang
2015-10-12 14:01 ` [PATCH V3 0/2] Add SPDIF_GCLK clock in clock tree for imx6 Shawn Guo
2015-10-12 14:01   ` Shawn Guo

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