diff for duplicates of <20151015093146.7777.781@quantum> diff --git a/a/1.txt b/N1/1.txt index b973438..72852c8 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,25 +1,21 @@ Quoting Wenyou Yang (2015-10-14 20:41:07) > The Ultra Low-power mode 1(ULP1) is introduced by SAMA5D2. -> = - +> > In the ULP1 mode, all the clocks are shut off, inclusive the embedded > 12MHz RC oscillator, so as to achieve the lowest power consumption > with the system in retention mode and able to resume on the wake up > events. As soon as the wake up event is asserted, the embedded 12MHz > RC oscillator restarts automatically. -> = - +> > The number of wake up sources for the ULP1 mode is limited, the wake > up sources should be configured via the PMC_FSMR and PMC_FSPR > registers. -> = - +> > In this patch, the following wake up sources are enabled, > - WKUP0 pin > - WKUP1 pin to WKUP8 pin (shared with PIOBU0 to PIOBU7) > - RTC alarm -> = - +> > Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> For the changes to the clk header: @@ -27,16 +23,13 @@ For the changes to the clk header: Acked-by: Michael Turquette <mturquette@baylibre.com> > --- -> = - +> > arch/arm/mach-at91/pm.c | 29 ++++++++++ > arch/arm/mach-at91/pm.h | 7 +++ -> arch/arm/mach-at91/pm_suspend.S | 111 +++++++++++++++++++++++++++++++++= -++++++ +> arch/arm/mach-at91/pm_suspend.S | 111 +++++++++++++++++++++++++++++++++++++++ > include/linux/clk/at91_pmc.h | 36 +++++++++++++ > 4 files changed, 183 insertions(+) -> = - +> > diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c > index 80e277c..49443d9 100644 > --- a/arch/arm/mach-at91/pm.c @@ -44,8 +37,7 @@ Acked-by: Michael Turquette <mturquette@baylibre.com> > @@ -35,6 +35,11 @@ > #include "generic.h" > #include "pm.h" -> = - +> > +#define ULP0_MODE 0x00 > +#define ULP1_MODE 0x11 > + @@ -57,11 +49,10 @@ Acked-by: Michael Turquette <mturquette@baylibre.com> > @@ -64,6 +69,23 @@ static int at91_pm_valid_state(suspend_state_t state) > } > } -> = - +> > +static void at91_config_ulp1_wkup_source(void) > +{ -> + if (at91_pmc_read(AT91_PMC_VERSION) >=3D SAMA5D2_PMC_VERSION) { +> + if (at91_pmc_read(AT91_PMC_VERSION) >= SAMA5D2_PMC_VERSION) { > + at91_pmc_write(AT91_PMC_FSMR, AT91_PMC_RTCAL | > + AT91_PMC_FSTT9 | > + AT91_PMC_FSTT8 | @@ -76,64 +67,53 @@ Acked-by: Michael Turquette <mturquette@baylibre.com> > + at91_pmc_write(AT91_PMC_FSPR, 0); > + } > +} -> = - +> > static suspend_state_t target_state; -> = - +> > @@ -73,6 +95,9 @@ static suspend_state_t target_state; > static int at91_pm_begin(suspend_state_t state) > { -> target_state =3D state; +> target_state = state; > + > + at91_config_ulp1_wkup_source(); > + > return 0; > } -> = - +> > @@ -140,6 +165,10 @@ static void at91_pm_suspend(suspend_state_t state) -> pm_data |=3D (state =3D=3D PM_SUSPEND_MEM) ? +> pm_data |= (state == PM_SUSPEND_MEM) ? > AT91_PM_MODE(AT91_PM_SLOW_CLOCK) : 0; -> = - -> + pm_data |=3D ((state =3D=3D PM_SUSPEND_MEM) && -> + (at91_pmc_read(AT91_PMC_VERSION) >=3D SAMA5D2_PMC_VER= -SION)) ? +> +> + pm_data |= ((state == PM_SUSPEND_MEM) && +> + (at91_pmc_read(AT91_PMC_VERSION) >= SAMA5D2_PMC_VERSION)) ? > + AT91_PM_ULP(AT91_PM_ULP1_MODE) : 0; > + > flush_cache_all(); > outer_disable(); -> = - +> > diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h > index 3fcf881..2e76745 100644 > --- a/arch/arm/mach-at91/pm.h > +++ b/arch/arm/mach-at91/pm.h > @@ -39,4 +39,11 @@ extern void __iomem *at91_ramc_base[]; -> = - +> > #define AT91_PM_SLOW_CLOCK 0x01 -> = - +> > +#define AT91_PM_ULP_OFFSET 5 > +#define AT91_PM_ULP_MASK 0x03 -> +#define AT91_PM_ULP(x) (((x) & AT91_PM_ULP_MASK) << AT91_PM_ULP_= -OFFSET) +> +#define AT91_PM_ULP(x) (((x) & AT91_PM_ULP_MASK) << AT91_PM_ULP_OFFSET) > + > +#define AT91_PM_ULP0_MODE 0x00 > +#define AT91_PM_ULP1_MODE 0x01 > + > #endif -> diff --git a/arch/arm/mach-at91/pm_suspend.S b/arch/arm/mach-at91/pm_susp= -end.S +> diff --git a/arch/arm/mach-at91/pm_suspend.S b/arch/arm/mach-at91/pm_suspend.S > index 825347b..543c430 100644 > --- a/arch/arm/mach-at91/pm_suspend.S > +++ b/arch/arm/mach-at91/pm_suspend.S > @@ -41,6 +41,15 @@ tmp2 .req r5 > .endm -> = - +> > /* > + * Wait for main oscillator selection is done > + */ @@ -150,8 +130,7 @@ end.S > @@ -99,6 +108,10 @@ ENTRY(at91_pm_suspend_in_sram) > and r0, r0, #AT91_PM_MODE_MASK > str r0, .pm_mode -> = - +> > + lsr r0, r3, #AT91_PM_ULP_OFFSET > + and r0, r0, #AT91_PM_ULP_MASK > + str r0, .ulp_mode @@ -162,8 +141,7 @@ end.S > @@ -107,6 +120,14 @@ ENTRY(at91_pm_suspend_in_sram) > tst r0, #AT91_PM_SLOW_CLOCK > beq standby_mode -> = - +> > + ldr r0, .ulp_mode > + tst r0, #AT91_PM_ULP1_MODE > + beq ulp0_mode @@ -178,8 +156,7 @@ end.S > @@ -313,6 +334,94 @@ ENTRY(at91_pm_ulp0_mode) > mov pc, lr > ENDPROC(at91_pm_ulp0_mode) -> = - +> > +/* > + * void at91_pm_ulp1_mode(void) > + * @@ -285,116 +262,64 @@ end.S > --- a/include/linux/clk/at91_pmc.h > +++ b/include/linux/clk/at91_pmc.h > @@ -59,8 +59,10 @@ extern void __iomem *at91_pmc_base; -> #define AT91_CKGR_MOR 0x20 /* Main O= -scillator Register [not on SAM9RL] */ -> #define AT91_PMC_MOSCEN (1 << 0) /= -* Main Oscillator Enable */ -> #define AT91_PMC_OSCBYPASS (1 << 1) /= -* Oscillator Bypass */ -> +#define AT91_PMC_WAITMODE (1 << 2) /= -* Wait Mode Command */ -> #define AT91_PMC_MOSCRCEN (1 << 3) /= -* Main On-Chip RC Oscillator Enable [some SAM9] */ -> #define AT91_PMC_OSCOUNT (0xff << 8) /= -* Main Oscillator Start-up Time */ +> #define AT91_CKGR_MOR 0x20 /* Main Oscillator Register [not on SAM9RL] */ +> #define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */ +> #define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass */ +> +#define AT91_PMC_WAITMODE (1 << 2) /* Wait Mode Command */ +> #define AT91_PMC_MOSCRCEN (1 << 3) /* Main On-Chip RC Oscillator Enable [some SAM9] */ +> #define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */ > +#define AT91_PMC_KEY_MASK (0xff << 16) -> #define AT91_PMC_KEY (0x37 << 16) /= -* MOR Writing Key */ -> #define AT91_PMC_MOSCSEL (1 << 24) /= -* Main Oscillator Selection [some SAM9] */ -> #define AT91_PMC_CFDEN (1 << 25) /= -* Clock Failure Detector Enable [some SAM9] */ +> #define AT91_PMC_KEY (0x37 << 16) /* MOR Writing Key */ +> #define AT91_PMC_MOSCSEL (1 << 24) /* Main Oscillator Selection [some SAM9] */ +> #define AT91_PMC_CFDEN (1 << 25) /* Clock Failure Detector Enable [some SAM9] */ > @@ -166,6 +168,38 @@ extern void __iomem *at91_pmc_base; -> #define AT91_PMC_CFDEV (1 << 18) /= -* Clock Failure Detector Event [some SAM9] */ -> #define AT91_PMC_IMR 0x6c /* Interr= -upt Mask Register */ -> = - -> +#define AT91_PMC_FSMR 0x70 /* Fast Startup M= -ode Register */ -> +#define AT91_PMC_FSTT0 (1 << 0) /= -* Fast Startup from WKUP Pin Enable */ -> +#define AT91_PMC_FSTT1 (1 << 1) /= -* Fast Startup from Security Module Enable */ -> +#define AT91_PMC_FSTT2 (1 << 2) /= -* Fast Startup from PIOBU0 Input Enable */ -> +#define AT91_PMC_FSTT3 (1 << 3) /= -* Fast Startup from PIOBU1 Input Enable */ -> +#define AT91_PMC_FSTT4 (1 << 4) /= -* Fast Startup from PIOBU2 Input Enable */ -> +#define AT91_PMC_FSTT5 (1 << 5) /= -* Fast Startup from PIOBU3 Input Enable */ -> +#define AT91_PMC_FSTT6 (1 << 6) /= -* Fast Startup from PIOBU4 Input Enable */ -> +#define AT91_PMC_FSTT7 (1 << 7) /= -* Fast Startup from PIOBU5 Input Enable */ -> +#define AT91_PMC_FSTT8 (1 << 8) /= -* Fast Startup from PIOBU6 Input Enable */ -> +#define AT91_PMC_FSTT9 (1 << 9) /= -* Fast Startup from PIOBU7 Input Enable */ -> +#define AT91_PMC_FSTT10 (1 << 10) /= -* Fast Startup from GMAC Wake-up On LAN Enable */ -> +#define AT91_PMC_RTCAL (1 << 17) /= -* Fast Startup from RTC Alarm Enable */ -> +#define AT91_PMC_USBAL (1 << 18) /= -* Fast Startup from USB Resume Enable */ -> +#define AT91_PMC_SDMMC_CD (1 << 19) /= -* Fast Startup from SDMMC Card Detect Enable */ -> +#define AT91_PMC_LPM (1 << 20) /= -* Low-power Mode */ -> +#define AT91_PMC_RXLP_MCE (1 << 24) /= -* Fast Startup from Backup UART Receive Match Condition Enable */ -> +#define AT91_PMC_ACC_CE (1 << 25) /= -* Fast Startup from Analog Comparator Controller Comparison Enable*/ -> + -> +#define AT91_PMC_FSPR 0x74 /* Fast Startup P= -olarity Register */ -> +#define AT91_PMC_FSTP0 (1 << 0) /= -* WKUP Pin Polarity for Fast Startup */ -> +#define AT91_PMC_FSTP1 (1 << 1) /= -* Security Module Polarity for Fast Startup */ -> +#define AT91_PMC_FSTP2 (1 << 2) /= -* PIOBU0 Pin Polarity for Fast Startup */ -> +#define AT91_PMC_FSTP3 (1 << 3) /= -* PIOBU1 Pin Polarity for Fast Startup */ -> +#define AT91_PMC_FSTP4 (1 << 4) /= -* PIOBU2 Pin Polarity for Fast Startup */ -> +#define AT91_PMC_FSTP5 (1 << 5) /= -* PIOBU3 Pin Polarity for Fast Startup */ -> +#define AT91_PMC_FSTP6 (1 << 6) /= -* PIOBU4 Pin Polarity for Fast Startup */ -> +#define AT91_PMC_FSTP7 (1 << 7) /= -* PIOBU5 Pin Polarity for Fast Startup */ -> +#define AT91_PMC_FSTP8 (1 << 8) /= -* PIOBU6 Pin Polarity for Fast Startup */ -> +#define AT91_PMC_FSTP9 (1 << 9) /= -* PIOBU7 Pin Polarity for Fast Startup */ -> +#define AT91_PMC_FSTP10 (1 << 10) /= -* GMAC Wake-up On LAN Polarity for Fast Startup */ -> + -> #define AT91_PMC_PLLICPR 0x80 /* PLL Charge Pum= -p Current Register */ -> = - -> #define AT91_PMC_PROT 0xe4 /* Write Protect = -Mode Register [some SAM9] */ +> #define AT91_PMC_CFDEV (1 << 18) /* Clock Failure Detector Event [some SAM9] */ +> #define AT91_PMC_IMR 0x6c /* Interrupt Mask Register */ +> +> +#define AT91_PMC_FSMR 0x70 /* Fast Startup Mode Register */ +> +#define AT91_PMC_FSTT0 (1 << 0) /* Fast Startup from WKUP Pin Enable */ +> +#define AT91_PMC_FSTT1 (1 << 1) /* Fast Startup from Security Module Enable */ +> +#define AT91_PMC_FSTT2 (1 << 2) /* Fast Startup from PIOBU0 Input Enable */ +> +#define AT91_PMC_FSTT3 (1 << 3) /* Fast Startup from PIOBU1 Input Enable */ +> +#define AT91_PMC_FSTT4 (1 << 4) /* Fast Startup from PIOBU2 Input Enable */ +> +#define AT91_PMC_FSTT5 (1 << 5) /* Fast Startup from PIOBU3 Input Enable */ +> +#define AT91_PMC_FSTT6 (1 << 6) /* Fast Startup from PIOBU4 Input Enable */ +> +#define AT91_PMC_FSTT7 (1 << 7) /* Fast Startup from PIOBU5 Input Enable */ +> +#define AT91_PMC_FSTT8 (1 << 8) /* Fast Startup from PIOBU6 Input Enable */ +> +#define AT91_PMC_FSTT9 (1 << 9) /* Fast Startup from PIOBU7 Input Enable */ +> +#define AT91_PMC_FSTT10 (1 << 10) /* Fast Startup from GMAC Wake-up On LAN Enable */ +> +#define AT91_PMC_RTCAL (1 << 17) /* Fast Startup from RTC Alarm Enable */ +> +#define AT91_PMC_USBAL (1 << 18) /* Fast Startup from USB Resume Enable */ +> +#define AT91_PMC_SDMMC_CD (1 << 19) /* Fast Startup from SDMMC Card Detect Enable */ +> +#define AT91_PMC_LPM (1 << 20) /* Low-power Mode */ +> +#define AT91_PMC_RXLP_MCE (1 << 24) /* Fast Startup from Backup UART Receive Match Condition Enable */ +> +#define AT91_PMC_ACC_CE (1 << 25) /* Fast Startup from Analog Comparator Controller Comparison Enable*/ +> + +> +#define AT91_PMC_FSPR 0x74 /* Fast Startup Polarity Register */ +> +#define AT91_PMC_FSTP0 (1 << 0) /* WKUP Pin Polarity for Fast Startup */ +> +#define AT91_PMC_FSTP1 (1 << 1) /* Security Module Polarity for Fast Startup */ +> +#define AT91_PMC_FSTP2 (1 << 2) /* PIOBU0 Pin Polarity for Fast Startup */ +> +#define AT91_PMC_FSTP3 (1 << 3) /* PIOBU1 Pin Polarity for Fast Startup */ +> +#define AT91_PMC_FSTP4 (1 << 4) /* PIOBU2 Pin Polarity for Fast Startup */ +> +#define AT91_PMC_FSTP5 (1 << 5) /* PIOBU3 Pin Polarity for Fast Startup */ +> +#define AT91_PMC_FSTP6 (1 << 6) /* PIOBU4 Pin Polarity for Fast Startup */ +> +#define AT91_PMC_FSTP7 (1 << 7) /* PIOBU5 Pin Polarity for Fast Startup */ +> +#define AT91_PMC_FSTP8 (1 << 8) /* PIOBU6 Pin Polarity for Fast Startup */ +> +#define AT91_PMC_FSTP9 (1 << 9) /* PIOBU7 Pin Polarity for Fast Startup */ +> +#define AT91_PMC_FSTP10 (1 << 10) /* GMAC Wake-up On LAN Polarity for Fast Startup */ +> + +> #define AT91_PMC_PLLICPR 0x80 /* PLL Charge Pump Current Register */ +> +> #define AT91_PMC_PROT 0xe4 /* Write Protect Mode Register [some SAM9] */ > @@ -177,6 +211,8 @@ extern void __iomem *at91_pmc_base; -> #define AT91_PMC_WPVS (0x1 << 0) /= -* Write Protect Violation Status */ -> #define AT91_PMC_WPVSRC (0xffff << 8) /= -* Write Protect Violation Source */ -> = - +> #define AT91_PMC_WPVS (0x1 << 0) /* Write Protect Violation Status */ +> #define AT91_PMC_WPVSRC (0xffff << 8) /* Write Protect Violation Source */ +> > +#define AT91_PMC_VERSION 0xfc > + -> #define AT91_PMC_PCER1 0x100 /* Peripheral Clo= -ck Enable Register 1 [SAMA5 only]*/ -> #define AT91_PMC_PCDR1 0x104 /* Peripheral Clo= -ck Enable Register 1 */ -> #define AT91_PMC_PCSR1 0x108 /* Peripheral Clo= -ck Enable Register 1 */ -> -- = - +> #define AT91_PMC_PCER1 0x100 /* Peripheral Clock Enable Register 1 [SAMA5 only]*/ +> #define AT91_PMC_PCDR1 0x104 /* Peripheral Clock Enable Register 1 */ +> #define AT91_PMC_PCSR1 0x108 /* Peripheral Clock Enable Register 1 */ +> -- > 1.7.9.5 ->=20 +> diff --git a/a/content_digest b/N1/content_digest index 28ec370..6cd427c 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,42 +1,29 @@ "ref\01444880467-18598-1-git-send-email-wenyou.yang@atmel.com\0" "ref\01444880467-18598-3-git-send-email-wenyou.yang@atmel.com\0" - "From\0Michael Turquette <mturquette@baylibre.com>\0" - "Subject\0Re: [PATCH 2/2] ARM: at91/pm: add ultra Low-power mode 1(ULP1) support\0" + "From\0mturquette@baylibre.com (Michael Turquette)\0" + "Subject\0[PATCH 2/2] ARM: at91/pm: add ultra Low-power mode 1(ULP1) support\0" "Date\0Thu, 15 Oct 2015 02:31:46 -0700\0" - "To\0Wenyou Yang <wenyou.yang@atmel.com>" - Nicolas Ferre <nicolas.ferre@atmel.com> - Alexandre Belloni <alexandre.belloni@free-electrons.com> - " Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com>\0" - "Cc\0Russell King <linux@arm.linux.org.uk>" - Stephen Boyd <sboyd@codeaurora.org> - linux-arm-kernel@lists.infradead.org - linux-kernel@vger.kernel.org - linux-clk@vger.kernel.org - " Wenyou Yang <wenyou.yang@atmel.com>\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "Quoting Wenyou Yang (2015-10-14 20:41:07)\n" "> The Ultra Low-power mode 1(ULP1) is introduced by SAMA5D2.\n" - "> =\n" - "\n" + "> \n" "> In the ULP1 mode, all the clocks are shut off, inclusive the embedded\n" "> 12MHz RC oscillator, so as to achieve the lowest power consumption\n" "> with the system in retention mode and able to resume on the wake up\n" "> events. As soon as the wake up event is asserted, the embedded 12MHz\n" "> RC oscillator restarts automatically.\n" - "> =\n" - "\n" + "> \n" "> The number of wake up sources for the ULP1 mode is limited, the wake\n" "> up sources should be configured via the PMC_FSMR and PMC_FSPR\n" "> registers.\n" - "> =\n" - "\n" + "> \n" "> In this patch, the following wake up sources are enabled,\n" "> - WKUP0 pin\n" "> - WKUP1 pin to WKUP8 pin (shared with PIOBU0 to PIOBU7)\n" "> - RTC alarm\n" - "> =\n" - "\n" + "> \n" "> Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>\n" "\n" "For the changes to the clk header:\n" @@ -44,16 +31,13 @@ "Acked-by: Michael Turquette <mturquette@baylibre.com>\n" "\n" "> ---\n" - "> =\n" - "\n" + "> \n" "> arch/arm/mach-at91/pm.c | 29 ++++++++++\n" "> arch/arm/mach-at91/pm.h | 7 +++\n" - "> arch/arm/mach-at91/pm_suspend.S | 111 +++++++++++++++++++++++++++++++++=\n" - "++++++\n" + "> arch/arm/mach-at91/pm_suspend.S | 111 +++++++++++++++++++++++++++++++++++++++\n" "> include/linux/clk/at91_pmc.h | 36 +++++++++++++\n" "> 4 files changed, 183 insertions(+)\n" - "> =\n" - "\n" + "> \n" "> diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c\n" "> index 80e277c..49443d9 100644\n" "> --- a/arch/arm/mach-at91/pm.c\n" @@ -61,8 +45,7 @@ "> @@ -35,6 +35,11 @@\n" "> #include \"generic.h\"\n" "> #include \"pm.h\"\n" - "> =\n" - "\n" + "> \n" "> +#define ULP0_MODE 0x00\n" "> +#define ULP1_MODE 0x11\n" "> +\n" @@ -74,11 +57,10 @@ "> @@ -64,6 +69,23 @@ static int at91_pm_valid_state(suspend_state_t state)\n" "> }\n" "> }\n" - "> =\n" - "\n" + "> \n" "> +static void at91_config_ulp1_wkup_source(void)\n" "> +{\n" - "> + if (at91_pmc_read(AT91_PMC_VERSION) >=3D SAMA5D2_PMC_VERSION) {\n" + "> + if (at91_pmc_read(AT91_PMC_VERSION) >= SAMA5D2_PMC_VERSION) {\n" "> + at91_pmc_write(AT91_PMC_FSMR, AT91_PMC_RTCAL |\n" "> + AT91_PMC_FSTT9 |\n" "> + AT91_PMC_FSTT8 |\n" @@ -93,64 +75,53 @@ "> + at91_pmc_write(AT91_PMC_FSPR, 0);\n" "> + }\n" "> +}\n" - "> =\n" - "\n" + "> \n" "> static suspend_state_t target_state;\n" - "> =\n" - "\n" + "> \n" "> @@ -73,6 +95,9 @@ static suspend_state_t target_state;\n" "> static int at91_pm_begin(suspend_state_t state)\n" "> {\n" - "> target_state =3D state;\n" + "> target_state = state;\n" "> +\n" "> + at91_config_ulp1_wkup_source();\n" "> +\n" "> return 0;\n" "> }\n" - "> =\n" - "\n" + "> \n" "> @@ -140,6 +165,10 @@ static void at91_pm_suspend(suspend_state_t state)\n" - "> pm_data |=3D (state =3D=3D PM_SUSPEND_MEM) ?\n" + "> pm_data |= (state == PM_SUSPEND_MEM) ?\n" "> AT91_PM_MODE(AT91_PM_SLOW_CLOCK) : 0;\n" - "> =\n" - "\n" - "> + pm_data |=3D ((state =3D=3D PM_SUSPEND_MEM) &&\n" - "> + (at91_pmc_read(AT91_PMC_VERSION) >=3D SAMA5D2_PMC_VER=\n" - "SION)) ?\n" + "> \n" + "> + pm_data |= ((state == PM_SUSPEND_MEM) &&\n" + "> + (at91_pmc_read(AT91_PMC_VERSION) >= SAMA5D2_PMC_VERSION)) ?\n" "> + AT91_PM_ULP(AT91_PM_ULP1_MODE) : 0;\n" "> +\n" "> flush_cache_all();\n" "> outer_disable();\n" - "> =\n" - "\n" + "> \n" "> diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h\n" "> index 3fcf881..2e76745 100644\n" "> --- a/arch/arm/mach-at91/pm.h\n" "> +++ b/arch/arm/mach-at91/pm.h\n" "> @@ -39,4 +39,11 @@ extern void __iomem *at91_ramc_base[];\n" - "> =\n" - "\n" + "> \n" "> #define AT91_PM_SLOW_CLOCK 0x01\n" - "> =\n" - "\n" + "> \n" "> +#define AT91_PM_ULP_OFFSET 5\n" "> +#define AT91_PM_ULP_MASK 0x03\n" - "> +#define AT91_PM_ULP(x) (((x) & AT91_PM_ULP_MASK) << AT91_PM_ULP_=\n" - "OFFSET)\n" + "> +#define AT91_PM_ULP(x) (((x) & AT91_PM_ULP_MASK) << AT91_PM_ULP_OFFSET)\n" "> +\n" "> +#define AT91_PM_ULP0_MODE 0x00\n" "> +#define AT91_PM_ULP1_MODE 0x01\n" "> +\n" "> #endif\n" - "> diff --git a/arch/arm/mach-at91/pm_suspend.S b/arch/arm/mach-at91/pm_susp=\n" - "end.S\n" + "> diff --git a/arch/arm/mach-at91/pm_suspend.S b/arch/arm/mach-at91/pm_suspend.S\n" "> index 825347b..543c430 100644\n" "> --- a/arch/arm/mach-at91/pm_suspend.S\n" "> +++ b/arch/arm/mach-at91/pm_suspend.S\n" "> @@ -41,6 +41,15 @@ tmp2 .req r5\n" "> .endm\n" - "> =\n" - "\n" + "> \n" "> /*\n" "> + * Wait for main oscillator selection is done\n" "> + */\n" @@ -167,8 +138,7 @@ "> @@ -99,6 +108,10 @@ ENTRY(at91_pm_suspend_in_sram)\n" "> and r0, r0, #AT91_PM_MODE_MASK\n" "> str r0, .pm_mode\n" - "> =\n" - "\n" + "> \n" "> + lsr r0, r3, #AT91_PM_ULP_OFFSET\n" "> + and r0, r0, #AT91_PM_ULP_MASK\n" "> + str r0, .ulp_mode\n" @@ -179,8 +149,7 @@ "> @@ -107,6 +120,14 @@ ENTRY(at91_pm_suspend_in_sram)\n" "> tst r0, #AT91_PM_SLOW_CLOCK\n" "> beq standby_mode\n" - "> =\n" - "\n" + "> \n" "> + ldr r0, .ulp_mode\n" "> + tst r0, #AT91_PM_ULP1_MODE\n" "> + beq ulp0_mode\n" @@ -195,8 +164,7 @@ "> @@ -313,6 +334,94 @@ ENTRY(at91_pm_ulp0_mode)\n" "> mov pc, lr\n" "> ENDPROC(at91_pm_ulp0_mode)\n" - "> =\n" - "\n" + "> \n" "> +/*\n" "> + * void at91_pm_ulp1_mode(void)\n" "> + *\n" @@ -302,118 +270,66 @@ "> --- a/include/linux/clk/at91_pmc.h\n" "> +++ b/include/linux/clk/at91_pmc.h\n" "> @@ -59,8 +59,10 @@ extern void __iomem *at91_pmc_base;\n" - "> #define AT91_CKGR_MOR 0x20 /* Main O=\n" - "scillator Register [not on SAM9RL] */\n" - "> #define AT91_PMC_MOSCEN (1 << 0) /=\n" - "* Main Oscillator Enable */\n" - "> #define AT91_PMC_OSCBYPASS (1 << 1) /=\n" - "* Oscillator Bypass */\n" - "> +#define AT91_PMC_WAITMODE (1 << 2) /=\n" - "* Wait Mode Command */\n" - "> #define AT91_PMC_MOSCRCEN (1 << 3) /=\n" - "* Main On-Chip RC Oscillator Enable [some SAM9] */\n" - "> #define AT91_PMC_OSCOUNT (0xff << 8) /=\n" - "* Main Oscillator Start-up Time */\n" + "> #define AT91_CKGR_MOR 0x20 /* Main Oscillator Register [not on SAM9RL] */\n" + "> #define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */\n" + "> #define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass */\n" + "> +#define AT91_PMC_WAITMODE (1 << 2) /* Wait Mode Command */\n" + "> #define AT91_PMC_MOSCRCEN (1 << 3) /* Main On-Chip RC Oscillator Enable [some SAM9] */\n" + "> #define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */\n" "> +#define AT91_PMC_KEY_MASK (0xff << 16)\n" - "> #define AT91_PMC_KEY (0x37 << 16) /=\n" - "* MOR Writing Key */\n" - "> #define AT91_PMC_MOSCSEL (1 << 24) /=\n" - "* Main Oscillator Selection [some SAM9] */\n" - "> #define AT91_PMC_CFDEN (1 << 25) /=\n" - "* Clock Failure Detector Enable [some SAM9] */\n" + "> #define AT91_PMC_KEY (0x37 << 16) /* MOR Writing Key */\n" + "> #define AT91_PMC_MOSCSEL (1 << 24) /* Main Oscillator Selection [some SAM9] */\n" + "> #define AT91_PMC_CFDEN (1 << 25) /* Clock Failure Detector Enable [some SAM9] */\n" "> @@ -166,6 +168,38 @@ extern void __iomem *at91_pmc_base;\n" - "> #define AT91_PMC_CFDEV (1 << 18) /=\n" - "* Clock Failure Detector Event [some SAM9] */\n" - "> #define AT91_PMC_IMR 0x6c /* Interr=\n" - "upt Mask Register */\n" - "> =\n" - "\n" - "> +#define AT91_PMC_FSMR 0x70 /* Fast Startup M=\n" - "ode Register */\n" - "> +#define AT91_PMC_FSTT0 (1 << 0) /=\n" - "* Fast Startup from WKUP Pin Enable */\n" - "> +#define AT91_PMC_FSTT1 (1 << 1) /=\n" - "* Fast Startup from Security Module Enable */\n" - "> +#define AT91_PMC_FSTT2 (1 << 2) /=\n" - "* Fast Startup from PIOBU0 Input Enable */\n" - "> +#define AT91_PMC_FSTT3 (1 << 3) /=\n" - "* Fast Startup from PIOBU1 Input Enable */\n" - "> +#define AT91_PMC_FSTT4 (1 << 4) /=\n" - "* Fast Startup from PIOBU2 Input Enable */\n" - "> +#define AT91_PMC_FSTT5 (1 << 5) /=\n" - "* Fast Startup from PIOBU3 Input Enable */\n" - "> +#define AT91_PMC_FSTT6 (1 << 6) /=\n" - "* Fast Startup from PIOBU4 Input Enable */\n" - "> +#define AT91_PMC_FSTT7 (1 << 7) /=\n" - "* Fast Startup from PIOBU5 Input Enable */\n" - "> +#define AT91_PMC_FSTT8 (1 << 8) /=\n" - "* Fast Startup from PIOBU6 Input Enable */\n" - "> +#define AT91_PMC_FSTT9 (1 << 9) /=\n" - "* Fast Startup from PIOBU7 Input Enable */\n" - "> +#define AT91_PMC_FSTT10 (1 << 10) /=\n" - "* Fast Startup from GMAC Wake-up On LAN Enable */\n" - "> +#define AT91_PMC_RTCAL (1 << 17) /=\n" - "* Fast Startup from RTC Alarm Enable */\n" - "> +#define AT91_PMC_USBAL (1 << 18) /=\n" - "* Fast Startup from USB Resume Enable */\n" - "> +#define AT91_PMC_SDMMC_CD (1 << 19) /=\n" - "* Fast Startup from SDMMC Card Detect Enable */\n" - "> +#define AT91_PMC_LPM (1 << 20) /=\n" - "* Low-power Mode */\n" - "> +#define AT91_PMC_RXLP_MCE (1 << 24) /=\n" - "* Fast Startup from Backup UART Receive Match Condition Enable */\n" - "> +#define AT91_PMC_ACC_CE (1 << 25) /=\n" - "* Fast Startup from Analog Comparator Controller Comparison Enable*/\n" - "> +\n" - "> +#define AT91_PMC_FSPR 0x74 /* Fast Startup P=\n" - "olarity Register */\n" - "> +#define AT91_PMC_FSTP0 (1 << 0) /=\n" - "* WKUP Pin Polarity for Fast Startup */\n" - "> +#define AT91_PMC_FSTP1 (1 << 1) /=\n" - "* Security Module Polarity for Fast Startup */\n" - "> +#define AT91_PMC_FSTP2 (1 << 2) /=\n" - "* PIOBU0 Pin Polarity for Fast Startup */\n" - "> +#define AT91_PMC_FSTP3 (1 << 3) /=\n" - "* PIOBU1 Pin Polarity for Fast Startup */\n" - "> +#define AT91_PMC_FSTP4 (1 << 4) /=\n" - "* PIOBU2 Pin Polarity for Fast Startup */\n" - "> +#define AT91_PMC_FSTP5 (1 << 5) /=\n" - "* PIOBU3 Pin Polarity for Fast Startup */\n" - "> +#define AT91_PMC_FSTP6 (1 << 6) /=\n" - "* PIOBU4 Pin Polarity for Fast Startup */\n" - "> +#define AT91_PMC_FSTP7 (1 << 7) /=\n" - "* PIOBU5 Pin Polarity for Fast Startup */\n" - "> +#define AT91_PMC_FSTP8 (1 << 8) /=\n" - "* PIOBU6 Pin Polarity for Fast Startup */\n" - "> +#define AT91_PMC_FSTP9 (1 << 9) /=\n" - "* PIOBU7 Pin Polarity for Fast Startup */\n" - "> +#define AT91_PMC_FSTP10 (1 << 10) /=\n" - "* GMAC Wake-up On LAN Polarity for Fast Startup */\n" - "> +\n" - "> #define AT91_PMC_PLLICPR 0x80 /* PLL Charge Pum=\n" - "p Current Register */\n" - "> =\n" - "\n" - "> #define AT91_PMC_PROT 0xe4 /* Write Protect =\n" - "Mode Register [some SAM9] */\n" + "> #define AT91_PMC_CFDEV (1 << 18) /* Clock Failure Detector Event [some SAM9] */\n" + "> #define AT91_PMC_IMR 0x6c /* Interrupt Mask Register */\n" + "> \n" + "> +#define AT91_PMC_FSMR 0x70 /* Fast Startup Mode Register */\n" + "> +#define AT91_PMC_FSTT0 (1 << 0) /* Fast Startup from WKUP Pin Enable */\n" + "> +#define AT91_PMC_FSTT1 (1 << 1) /* Fast Startup from Security Module Enable */\n" + "> +#define AT91_PMC_FSTT2 (1 << 2) /* Fast Startup from PIOBU0 Input Enable */\n" + "> +#define AT91_PMC_FSTT3 (1 << 3) /* Fast Startup from PIOBU1 Input Enable */\n" + "> +#define AT91_PMC_FSTT4 (1 << 4) /* Fast Startup from PIOBU2 Input Enable */\n" + "> +#define AT91_PMC_FSTT5 (1 << 5) /* Fast Startup from PIOBU3 Input Enable */\n" + "> +#define AT91_PMC_FSTT6 (1 << 6) /* Fast Startup from PIOBU4 Input Enable */\n" + "> +#define AT91_PMC_FSTT7 (1 << 7) /* Fast Startup from PIOBU5 Input Enable */\n" + "> +#define AT91_PMC_FSTT8 (1 << 8) /* Fast Startup from PIOBU6 Input Enable */\n" + "> +#define AT91_PMC_FSTT9 (1 << 9) /* Fast Startup from PIOBU7 Input Enable */\n" + "> +#define AT91_PMC_FSTT10 (1 << 10) /* Fast Startup from GMAC Wake-up On LAN Enable */\n" + "> +#define AT91_PMC_RTCAL (1 << 17) /* Fast Startup from RTC Alarm Enable */\n" + "> +#define AT91_PMC_USBAL (1 << 18) /* Fast Startup from USB Resume Enable */\n" + "> +#define AT91_PMC_SDMMC_CD (1 << 19) /* Fast Startup from SDMMC Card Detect Enable */\n" + "> +#define AT91_PMC_LPM (1 << 20) /* Low-power Mode */\n" + "> +#define AT91_PMC_RXLP_MCE (1 << 24) /* Fast Startup from Backup UART Receive Match Condition Enable */\n" + "> +#define AT91_PMC_ACC_CE (1 << 25) /* Fast Startup from Analog Comparator Controller Comparison Enable*/\n" + "> +\n" + "> +#define AT91_PMC_FSPR 0x74 /* Fast Startup Polarity Register */\n" + "> +#define AT91_PMC_FSTP0 (1 << 0) /* WKUP Pin Polarity for Fast Startup */\n" + "> +#define AT91_PMC_FSTP1 (1 << 1) /* Security Module Polarity for Fast Startup */\n" + "> +#define AT91_PMC_FSTP2 (1 << 2) /* PIOBU0 Pin Polarity for Fast Startup */\n" + "> +#define AT91_PMC_FSTP3 (1 << 3) /* PIOBU1 Pin Polarity for Fast Startup */\n" + "> +#define AT91_PMC_FSTP4 (1 << 4) /* PIOBU2 Pin Polarity for Fast Startup */\n" + "> +#define AT91_PMC_FSTP5 (1 << 5) /* PIOBU3 Pin Polarity for Fast Startup */\n" + "> +#define AT91_PMC_FSTP6 (1 << 6) /* PIOBU4 Pin Polarity for Fast Startup */\n" + "> +#define AT91_PMC_FSTP7 (1 << 7) /* PIOBU5 Pin Polarity for Fast Startup */\n" + "> +#define AT91_PMC_FSTP8 (1 << 8) /* PIOBU6 Pin Polarity for Fast Startup */\n" + "> +#define AT91_PMC_FSTP9 (1 << 9) /* PIOBU7 Pin Polarity for Fast Startup */\n" + "> +#define AT91_PMC_FSTP10 (1 << 10) /* GMAC Wake-up On LAN Polarity for Fast Startup */\n" + "> +\n" + "> #define AT91_PMC_PLLICPR 0x80 /* PLL Charge Pump Current Register */\n" + "> \n" + "> #define AT91_PMC_PROT 0xe4 /* Write Protect Mode Register [some SAM9] */\n" "> @@ -177,6 +211,8 @@ extern void __iomem *at91_pmc_base;\n" - "> #define AT91_PMC_WPVS (0x1 << 0) /=\n" - "* Write Protect Violation Status */\n" - "> #define AT91_PMC_WPVSRC (0xffff << 8) /=\n" - "* Write Protect Violation Source */\n" - "> =\n" - "\n" + "> #define AT91_PMC_WPVS (0x1 << 0) /* Write Protect Violation Status */\n" + "> #define AT91_PMC_WPVSRC (0xffff << 8) /* Write Protect Violation Source */\n" + "> \n" "> +#define AT91_PMC_VERSION 0xfc\n" "> +\n" - "> #define AT91_PMC_PCER1 0x100 /* Peripheral Clo=\n" - "ck Enable Register 1 [SAMA5 only]*/\n" - "> #define AT91_PMC_PCDR1 0x104 /* Peripheral Clo=\n" - "ck Enable Register 1 */\n" - "> #define AT91_PMC_PCSR1 0x108 /* Peripheral Clo=\n" - "ck Enable Register 1 */\n" - "> -- =\n" - "\n" + "> #define AT91_PMC_PCER1 0x100 /* Peripheral Clock Enable Register 1 [SAMA5 only]*/\n" + "> #define AT91_PMC_PCDR1 0x104 /* Peripheral Clock Enable Register 1 */\n" + "> #define AT91_PMC_PCSR1 0x108 /* Peripheral Clock Enable Register 1 */\n" + "> -- \n" "> 1.7.9.5\n" - >=20 + > -f9e4333820332aa9a2710ff730fba23e9f7e998da9db1c0d79128714b42154e3 +7f5c3935fd89b2c15c1e10aa2cd82843e75a697a83cab6f2a300cc750c97da96
diff --git a/a/1.txt b/N2/1.txt index b973438..72852c8 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -1,25 +1,21 @@ Quoting Wenyou Yang (2015-10-14 20:41:07) > The Ultra Low-power mode 1(ULP1) is introduced by SAMA5D2. -> = - +> > In the ULP1 mode, all the clocks are shut off, inclusive the embedded > 12MHz RC oscillator, so as to achieve the lowest power consumption > with the system in retention mode and able to resume on the wake up > events. As soon as the wake up event is asserted, the embedded 12MHz > RC oscillator restarts automatically. -> = - +> > The number of wake up sources for the ULP1 mode is limited, the wake > up sources should be configured via the PMC_FSMR and PMC_FSPR > registers. -> = - +> > In this patch, the following wake up sources are enabled, > - WKUP0 pin > - WKUP1 pin to WKUP8 pin (shared with PIOBU0 to PIOBU7) > - RTC alarm -> = - +> > Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> For the changes to the clk header: @@ -27,16 +23,13 @@ For the changes to the clk header: Acked-by: Michael Turquette <mturquette@baylibre.com> > --- -> = - +> > arch/arm/mach-at91/pm.c | 29 ++++++++++ > arch/arm/mach-at91/pm.h | 7 +++ -> arch/arm/mach-at91/pm_suspend.S | 111 +++++++++++++++++++++++++++++++++= -++++++ +> arch/arm/mach-at91/pm_suspend.S | 111 +++++++++++++++++++++++++++++++++++++++ > include/linux/clk/at91_pmc.h | 36 +++++++++++++ > 4 files changed, 183 insertions(+) -> = - +> > diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c > index 80e277c..49443d9 100644 > --- a/arch/arm/mach-at91/pm.c @@ -44,8 +37,7 @@ Acked-by: Michael Turquette <mturquette@baylibre.com> > @@ -35,6 +35,11 @@ > #include "generic.h" > #include "pm.h" -> = - +> > +#define ULP0_MODE 0x00 > +#define ULP1_MODE 0x11 > + @@ -57,11 +49,10 @@ Acked-by: Michael Turquette <mturquette@baylibre.com> > @@ -64,6 +69,23 @@ static int at91_pm_valid_state(suspend_state_t state) > } > } -> = - +> > +static void at91_config_ulp1_wkup_source(void) > +{ -> + if (at91_pmc_read(AT91_PMC_VERSION) >=3D SAMA5D2_PMC_VERSION) { +> + if (at91_pmc_read(AT91_PMC_VERSION) >= SAMA5D2_PMC_VERSION) { > + at91_pmc_write(AT91_PMC_FSMR, AT91_PMC_RTCAL | > + AT91_PMC_FSTT9 | > + AT91_PMC_FSTT8 | @@ -76,64 +67,53 @@ Acked-by: Michael Turquette <mturquette@baylibre.com> > + at91_pmc_write(AT91_PMC_FSPR, 0); > + } > +} -> = - +> > static suspend_state_t target_state; -> = - +> > @@ -73,6 +95,9 @@ static suspend_state_t target_state; > static int at91_pm_begin(suspend_state_t state) > { -> target_state =3D state; +> target_state = state; > + > + at91_config_ulp1_wkup_source(); > + > return 0; > } -> = - +> > @@ -140,6 +165,10 @@ static void at91_pm_suspend(suspend_state_t state) -> pm_data |=3D (state =3D=3D PM_SUSPEND_MEM) ? +> pm_data |= (state == PM_SUSPEND_MEM) ? > AT91_PM_MODE(AT91_PM_SLOW_CLOCK) : 0; -> = - -> + pm_data |=3D ((state =3D=3D PM_SUSPEND_MEM) && -> + (at91_pmc_read(AT91_PMC_VERSION) >=3D SAMA5D2_PMC_VER= -SION)) ? +> +> + pm_data |= ((state == PM_SUSPEND_MEM) && +> + (at91_pmc_read(AT91_PMC_VERSION) >= SAMA5D2_PMC_VERSION)) ? > + AT91_PM_ULP(AT91_PM_ULP1_MODE) : 0; > + > flush_cache_all(); > outer_disable(); -> = - +> > diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h > index 3fcf881..2e76745 100644 > --- a/arch/arm/mach-at91/pm.h > +++ b/arch/arm/mach-at91/pm.h > @@ -39,4 +39,11 @@ extern void __iomem *at91_ramc_base[]; -> = - +> > #define AT91_PM_SLOW_CLOCK 0x01 -> = - +> > +#define AT91_PM_ULP_OFFSET 5 > +#define AT91_PM_ULP_MASK 0x03 -> +#define AT91_PM_ULP(x) (((x) & AT91_PM_ULP_MASK) << AT91_PM_ULP_= -OFFSET) +> +#define AT91_PM_ULP(x) (((x) & AT91_PM_ULP_MASK) << AT91_PM_ULP_OFFSET) > + > +#define AT91_PM_ULP0_MODE 0x00 > +#define AT91_PM_ULP1_MODE 0x01 > + > #endif -> diff --git a/arch/arm/mach-at91/pm_suspend.S b/arch/arm/mach-at91/pm_susp= -end.S +> diff --git a/arch/arm/mach-at91/pm_suspend.S b/arch/arm/mach-at91/pm_suspend.S > index 825347b..543c430 100644 > --- a/arch/arm/mach-at91/pm_suspend.S > +++ b/arch/arm/mach-at91/pm_suspend.S > @@ -41,6 +41,15 @@ tmp2 .req r5 > .endm -> = - +> > /* > + * Wait for main oscillator selection is done > + */ @@ -150,8 +130,7 @@ end.S > @@ -99,6 +108,10 @@ ENTRY(at91_pm_suspend_in_sram) > and r0, r0, #AT91_PM_MODE_MASK > str r0, .pm_mode -> = - +> > + lsr r0, r3, #AT91_PM_ULP_OFFSET > + and r0, r0, #AT91_PM_ULP_MASK > + str r0, .ulp_mode @@ -162,8 +141,7 @@ end.S > @@ -107,6 +120,14 @@ ENTRY(at91_pm_suspend_in_sram) > tst r0, #AT91_PM_SLOW_CLOCK > beq standby_mode -> = - +> > + ldr r0, .ulp_mode > + tst r0, #AT91_PM_ULP1_MODE > + beq ulp0_mode @@ -178,8 +156,7 @@ end.S > @@ -313,6 +334,94 @@ ENTRY(at91_pm_ulp0_mode) > mov pc, lr > ENDPROC(at91_pm_ulp0_mode) -> = - +> > +/* > + * void at91_pm_ulp1_mode(void) > + * @@ -285,116 +262,64 @@ end.S > --- a/include/linux/clk/at91_pmc.h > +++ b/include/linux/clk/at91_pmc.h > @@ -59,8 +59,10 @@ extern void __iomem *at91_pmc_base; -> #define AT91_CKGR_MOR 0x20 /* Main O= -scillator Register [not on SAM9RL] */ -> #define AT91_PMC_MOSCEN (1 << 0) /= -* Main Oscillator Enable */ -> #define AT91_PMC_OSCBYPASS (1 << 1) /= -* Oscillator Bypass */ -> +#define AT91_PMC_WAITMODE (1 << 2) /= -* Wait Mode Command */ -> #define AT91_PMC_MOSCRCEN (1 << 3) /= -* Main On-Chip RC Oscillator Enable [some SAM9] */ -> #define AT91_PMC_OSCOUNT (0xff << 8) /= -* Main Oscillator Start-up Time */ +> #define AT91_CKGR_MOR 0x20 /* Main Oscillator Register [not on SAM9RL] */ +> #define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */ +> #define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass */ +> +#define AT91_PMC_WAITMODE (1 << 2) /* Wait Mode Command */ +> #define AT91_PMC_MOSCRCEN (1 << 3) /* Main On-Chip RC Oscillator Enable [some SAM9] */ +> #define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */ > +#define AT91_PMC_KEY_MASK (0xff << 16) -> #define AT91_PMC_KEY (0x37 << 16) /= -* MOR Writing Key */ -> #define AT91_PMC_MOSCSEL (1 << 24) /= -* Main Oscillator Selection [some SAM9] */ -> #define AT91_PMC_CFDEN (1 << 25) /= -* Clock Failure Detector Enable [some SAM9] */ +> #define AT91_PMC_KEY (0x37 << 16) /* MOR Writing Key */ +> #define AT91_PMC_MOSCSEL (1 << 24) /* Main Oscillator Selection [some SAM9] */ +> #define AT91_PMC_CFDEN (1 << 25) /* Clock Failure Detector Enable [some SAM9] */ > @@ -166,6 +168,38 @@ extern void __iomem *at91_pmc_base; -> #define AT91_PMC_CFDEV (1 << 18) /= -* Clock Failure Detector Event [some SAM9] */ -> #define AT91_PMC_IMR 0x6c /* Interr= -upt Mask Register */ -> = - -> +#define AT91_PMC_FSMR 0x70 /* Fast Startup M= -ode Register */ -> +#define AT91_PMC_FSTT0 (1 << 0) /= -* Fast Startup from WKUP Pin Enable */ -> +#define AT91_PMC_FSTT1 (1 << 1) /= -* Fast Startup from Security Module Enable */ -> +#define AT91_PMC_FSTT2 (1 << 2) /= -* Fast Startup from PIOBU0 Input Enable */ -> +#define AT91_PMC_FSTT3 (1 << 3) /= -* Fast Startup from PIOBU1 Input Enable */ -> +#define AT91_PMC_FSTT4 (1 << 4) /= -* Fast Startup from PIOBU2 Input Enable */ -> +#define AT91_PMC_FSTT5 (1 << 5) /= -* Fast Startup from PIOBU3 Input Enable */ -> +#define AT91_PMC_FSTT6 (1 << 6) /= -* Fast Startup from PIOBU4 Input Enable */ -> +#define AT91_PMC_FSTT7 (1 << 7) /= -* Fast Startup from PIOBU5 Input Enable */ -> +#define AT91_PMC_FSTT8 (1 << 8) /= -* Fast Startup from PIOBU6 Input Enable */ -> +#define AT91_PMC_FSTT9 (1 << 9) /= -* Fast Startup from PIOBU7 Input Enable */ -> +#define AT91_PMC_FSTT10 (1 << 10) /= -* Fast Startup from GMAC Wake-up On LAN Enable */ -> +#define AT91_PMC_RTCAL (1 << 17) /= -* Fast Startup from RTC Alarm Enable */ -> +#define AT91_PMC_USBAL (1 << 18) /= -* Fast Startup from USB Resume Enable */ -> +#define AT91_PMC_SDMMC_CD (1 << 19) /= -* Fast Startup from SDMMC Card Detect Enable */ -> +#define AT91_PMC_LPM (1 << 20) /= -* Low-power Mode */ -> +#define AT91_PMC_RXLP_MCE (1 << 24) /= -* Fast Startup from Backup UART Receive Match Condition Enable */ -> +#define AT91_PMC_ACC_CE (1 << 25) /= -* Fast Startup from Analog Comparator Controller Comparison Enable*/ -> + -> +#define AT91_PMC_FSPR 0x74 /* Fast Startup P= -olarity Register */ -> +#define AT91_PMC_FSTP0 (1 << 0) /= -* WKUP Pin Polarity for Fast Startup */ -> +#define AT91_PMC_FSTP1 (1 << 1) /= -* Security Module Polarity for Fast Startup */ -> +#define AT91_PMC_FSTP2 (1 << 2) /= -* PIOBU0 Pin Polarity for Fast Startup */ -> +#define AT91_PMC_FSTP3 (1 << 3) /= -* PIOBU1 Pin Polarity for Fast Startup */ -> +#define AT91_PMC_FSTP4 (1 << 4) /= -* PIOBU2 Pin Polarity for Fast Startup */ -> +#define AT91_PMC_FSTP5 (1 << 5) /= -* PIOBU3 Pin Polarity for Fast Startup */ -> +#define AT91_PMC_FSTP6 (1 << 6) /= -* PIOBU4 Pin Polarity for Fast Startup */ -> +#define AT91_PMC_FSTP7 (1 << 7) /= -* PIOBU5 Pin Polarity for Fast Startup */ -> +#define AT91_PMC_FSTP8 (1 << 8) /= -* PIOBU6 Pin Polarity for Fast Startup */ -> +#define AT91_PMC_FSTP9 (1 << 9) /= -* PIOBU7 Pin Polarity for Fast Startup */ -> +#define AT91_PMC_FSTP10 (1 << 10) /= -* GMAC Wake-up On LAN Polarity for Fast Startup */ -> + -> #define AT91_PMC_PLLICPR 0x80 /* PLL Charge Pum= -p Current Register */ -> = - -> #define AT91_PMC_PROT 0xe4 /* Write Protect = -Mode Register [some SAM9] */ +> #define AT91_PMC_CFDEV (1 << 18) /* Clock Failure Detector Event [some SAM9] */ +> #define AT91_PMC_IMR 0x6c /* Interrupt Mask Register */ +> +> +#define AT91_PMC_FSMR 0x70 /* Fast Startup Mode Register */ +> +#define AT91_PMC_FSTT0 (1 << 0) /* Fast Startup from WKUP Pin Enable */ +> +#define AT91_PMC_FSTT1 (1 << 1) /* Fast Startup from Security Module Enable */ +> +#define AT91_PMC_FSTT2 (1 << 2) /* Fast Startup from PIOBU0 Input Enable */ +> +#define AT91_PMC_FSTT3 (1 << 3) /* Fast Startup from PIOBU1 Input Enable */ +> +#define AT91_PMC_FSTT4 (1 << 4) /* Fast Startup from PIOBU2 Input Enable */ +> +#define AT91_PMC_FSTT5 (1 << 5) /* Fast Startup from PIOBU3 Input Enable */ +> +#define AT91_PMC_FSTT6 (1 << 6) /* Fast Startup from PIOBU4 Input Enable */ +> +#define AT91_PMC_FSTT7 (1 << 7) /* Fast Startup from PIOBU5 Input Enable */ +> +#define AT91_PMC_FSTT8 (1 << 8) /* Fast Startup from PIOBU6 Input Enable */ +> +#define AT91_PMC_FSTT9 (1 << 9) /* Fast Startup from PIOBU7 Input Enable */ +> +#define AT91_PMC_FSTT10 (1 << 10) /* Fast Startup from GMAC Wake-up On LAN Enable */ +> +#define AT91_PMC_RTCAL (1 << 17) /* Fast Startup from RTC Alarm Enable */ +> +#define AT91_PMC_USBAL (1 << 18) /* Fast Startup from USB Resume Enable */ +> +#define AT91_PMC_SDMMC_CD (1 << 19) /* Fast Startup from SDMMC Card Detect Enable */ +> +#define AT91_PMC_LPM (1 << 20) /* Low-power Mode */ +> +#define AT91_PMC_RXLP_MCE (1 << 24) /* Fast Startup from Backup UART Receive Match Condition Enable */ +> +#define AT91_PMC_ACC_CE (1 << 25) /* Fast Startup from Analog Comparator Controller Comparison Enable*/ +> + +> +#define AT91_PMC_FSPR 0x74 /* Fast Startup Polarity Register */ +> +#define AT91_PMC_FSTP0 (1 << 0) /* WKUP Pin Polarity for Fast Startup */ +> +#define AT91_PMC_FSTP1 (1 << 1) /* Security Module Polarity for Fast Startup */ +> +#define AT91_PMC_FSTP2 (1 << 2) /* PIOBU0 Pin Polarity for Fast Startup */ +> +#define AT91_PMC_FSTP3 (1 << 3) /* PIOBU1 Pin Polarity for Fast Startup */ +> +#define AT91_PMC_FSTP4 (1 << 4) /* PIOBU2 Pin Polarity for Fast Startup */ +> +#define AT91_PMC_FSTP5 (1 << 5) /* PIOBU3 Pin Polarity for Fast Startup */ +> +#define AT91_PMC_FSTP6 (1 << 6) /* PIOBU4 Pin Polarity for Fast Startup */ +> +#define AT91_PMC_FSTP7 (1 << 7) /* PIOBU5 Pin Polarity for Fast Startup */ +> +#define AT91_PMC_FSTP8 (1 << 8) /* PIOBU6 Pin Polarity for Fast Startup */ +> +#define AT91_PMC_FSTP9 (1 << 9) /* PIOBU7 Pin Polarity for Fast Startup */ +> +#define AT91_PMC_FSTP10 (1 << 10) /* GMAC Wake-up On LAN Polarity for Fast Startup */ +> + +> #define AT91_PMC_PLLICPR 0x80 /* PLL Charge Pump Current Register */ +> +> #define AT91_PMC_PROT 0xe4 /* Write Protect Mode Register [some SAM9] */ > @@ -177,6 +211,8 @@ extern void __iomem *at91_pmc_base; -> #define AT91_PMC_WPVS (0x1 << 0) /= -* Write Protect Violation Status */ -> #define AT91_PMC_WPVSRC (0xffff << 8) /= -* Write Protect Violation Source */ -> = - +> #define AT91_PMC_WPVS (0x1 << 0) /* Write Protect Violation Status */ +> #define AT91_PMC_WPVSRC (0xffff << 8) /* Write Protect Violation Source */ +> > +#define AT91_PMC_VERSION 0xfc > + -> #define AT91_PMC_PCER1 0x100 /* Peripheral Clo= -ck Enable Register 1 [SAMA5 only]*/ -> #define AT91_PMC_PCDR1 0x104 /* Peripheral Clo= -ck Enable Register 1 */ -> #define AT91_PMC_PCSR1 0x108 /* Peripheral Clo= -ck Enable Register 1 */ -> -- = - +> #define AT91_PMC_PCER1 0x100 /* Peripheral Clock Enable Register 1 [SAMA5 only]*/ +> #define AT91_PMC_PCDR1 0x104 /* Peripheral Clock Enable Register 1 */ +> #define AT91_PMC_PCSR1 0x108 /* Peripheral Clock Enable Register 1 */ +> -- > 1.7.9.5 ->=20 +> diff --git a/a/content_digest b/N2/content_digest index 28ec370..f5a52c9 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -17,26 +17,22 @@ "b\0" "Quoting Wenyou Yang (2015-10-14 20:41:07)\n" "> The Ultra Low-power mode 1(ULP1) is introduced by SAMA5D2.\n" - "> =\n" - "\n" + "> \n" "> In the ULP1 mode, all the clocks are shut off, inclusive the embedded\n" "> 12MHz RC oscillator, so as to achieve the lowest power consumption\n" "> with the system in retention mode and able to resume on the wake up\n" "> events. As soon as the wake up event is asserted, the embedded 12MHz\n" "> RC oscillator restarts automatically.\n" - "> =\n" - "\n" + "> \n" "> The number of wake up sources for the ULP1 mode is limited, the wake\n" "> up sources should be configured via the PMC_FSMR and PMC_FSPR\n" "> registers.\n" - "> =\n" - "\n" + "> \n" "> In this patch, the following wake up sources are enabled,\n" "> - WKUP0 pin\n" "> - WKUP1 pin to WKUP8 pin (shared with PIOBU0 to PIOBU7)\n" "> - RTC alarm\n" - "> =\n" - "\n" + "> \n" "> Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>\n" "\n" "For the changes to the clk header:\n" @@ -44,16 +40,13 @@ "Acked-by: Michael Turquette <mturquette@baylibre.com>\n" "\n" "> ---\n" - "> =\n" - "\n" + "> \n" "> arch/arm/mach-at91/pm.c | 29 ++++++++++\n" "> arch/arm/mach-at91/pm.h | 7 +++\n" - "> arch/arm/mach-at91/pm_suspend.S | 111 +++++++++++++++++++++++++++++++++=\n" - "++++++\n" + "> arch/arm/mach-at91/pm_suspend.S | 111 +++++++++++++++++++++++++++++++++++++++\n" "> include/linux/clk/at91_pmc.h | 36 +++++++++++++\n" "> 4 files changed, 183 insertions(+)\n" - "> =\n" - "\n" + "> \n" "> diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c\n" "> index 80e277c..49443d9 100644\n" "> --- a/arch/arm/mach-at91/pm.c\n" @@ -61,8 +54,7 @@ "> @@ -35,6 +35,11 @@\n" "> #include \"generic.h\"\n" "> #include \"pm.h\"\n" - "> =\n" - "\n" + "> \n" "> +#define ULP0_MODE 0x00\n" "> +#define ULP1_MODE 0x11\n" "> +\n" @@ -74,11 +66,10 @@ "> @@ -64,6 +69,23 @@ static int at91_pm_valid_state(suspend_state_t state)\n" "> }\n" "> }\n" - "> =\n" - "\n" + "> \n" "> +static void at91_config_ulp1_wkup_source(void)\n" "> +{\n" - "> + if (at91_pmc_read(AT91_PMC_VERSION) >=3D SAMA5D2_PMC_VERSION) {\n" + "> + if (at91_pmc_read(AT91_PMC_VERSION) >= SAMA5D2_PMC_VERSION) {\n" "> + at91_pmc_write(AT91_PMC_FSMR, AT91_PMC_RTCAL |\n" "> + AT91_PMC_FSTT9 |\n" "> + AT91_PMC_FSTT8 |\n" @@ -93,64 +84,53 @@ "> + at91_pmc_write(AT91_PMC_FSPR, 0);\n" "> + }\n" "> +}\n" - "> =\n" - "\n" + "> \n" "> static suspend_state_t target_state;\n" - "> =\n" - "\n" + "> \n" "> @@ -73,6 +95,9 @@ static suspend_state_t target_state;\n" "> static int at91_pm_begin(suspend_state_t state)\n" "> {\n" - "> target_state =3D state;\n" + "> target_state = state;\n" "> +\n" "> + at91_config_ulp1_wkup_source();\n" "> +\n" "> return 0;\n" "> }\n" - "> =\n" - "\n" + "> \n" "> @@ -140,6 +165,10 @@ static void at91_pm_suspend(suspend_state_t state)\n" - "> pm_data |=3D (state =3D=3D PM_SUSPEND_MEM) ?\n" + "> pm_data |= (state == PM_SUSPEND_MEM) ?\n" "> AT91_PM_MODE(AT91_PM_SLOW_CLOCK) : 0;\n" - "> =\n" - "\n" - "> + pm_data |=3D ((state =3D=3D PM_SUSPEND_MEM) &&\n" - "> + (at91_pmc_read(AT91_PMC_VERSION) >=3D SAMA5D2_PMC_VER=\n" - "SION)) ?\n" + "> \n" + "> + pm_data |= ((state == PM_SUSPEND_MEM) &&\n" + "> + (at91_pmc_read(AT91_PMC_VERSION) >= SAMA5D2_PMC_VERSION)) ?\n" "> + AT91_PM_ULP(AT91_PM_ULP1_MODE) : 0;\n" "> +\n" "> flush_cache_all();\n" "> outer_disable();\n" - "> =\n" - "\n" + "> \n" "> diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h\n" "> index 3fcf881..2e76745 100644\n" "> --- a/arch/arm/mach-at91/pm.h\n" "> +++ b/arch/arm/mach-at91/pm.h\n" "> @@ -39,4 +39,11 @@ extern void __iomem *at91_ramc_base[];\n" - "> =\n" - "\n" + "> \n" "> #define AT91_PM_SLOW_CLOCK 0x01\n" - "> =\n" - "\n" + "> \n" "> +#define AT91_PM_ULP_OFFSET 5\n" "> +#define AT91_PM_ULP_MASK 0x03\n" - "> +#define AT91_PM_ULP(x) (((x) & AT91_PM_ULP_MASK) << AT91_PM_ULP_=\n" - "OFFSET)\n" + "> +#define AT91_PM_ULP(x) (((x) & AT91_PM_ULP_MASK) << AT91_PM_ULP_OFFSET)\n" "> +\n" "> +#define AT91_PM_ULP0_MODE 0x00\n" "> +#define AT91_PM_ULP1_MODE 0x01\n" "> +\n" "> #endif\n" - "> diff --git a/arch/arm/mach-at91/pm_suspend.S b/arch/arm/mach-at91/pm_susp=\n" - "end.S\n" + "> diff --git a/arch/arm/mach-at91/pm_suspend.S b/arch/arm/mach-at91/pm_suspend.S\n" "> index 825347b..543c430 100644\n" "> --- a/arch/arm/mach-at91/pm_suspend.S\n" "> +++ b/arch/arm/mach-at91/pm_suspend.S\n" "> @@ -41,6 +41,15 @@ tmp2 .req r5\n" "> .endm\n" - "> =\n" - "\n" + "> \n" "> /*\n" "> + * Wait for main oscillator selection is done\n" "> + */\n" @@ -167,8 +147,7 @@ "> @@ -99,6 +108,10 @@ ENTRY(at91_pm_suspend_in_sram)\n" "> and r0, r0, #AT91_PM_MODE_MASK\n" "> str r0, .pm_mode\n" - "> =\n" - "\n" + "> \n" "> + lsr r0, r3, #AT91_PM_ULP_OFFSET\n" "> + and r0, r0, #AT91_PM_ULP_MASK\n" "> + str r0, .ulp_mode\n" @@ -179,8 +158,7 @@ "> @@ -107,6 +120,14 @@ ENTRY(at91_pm_suspend_in_sram)\n" "> tst r0, #AT91_PM_SLOW_CLOCK\n" "> beq standby_mode\n" - "> =\n" - "\n" + "> \n" "> + ldr r0, .ulp_mode\n" "> + tst r0, #AT91_PM_ULP1_MODE\n" "> + beq ulp0_mode\n" @@ -195,8 +173,7 @@ "> @@ -313,6 +334,94 @@ ENTRY(at91_pm_ulp0_mode)\n" "> mov pc, lr\n" "> ENDPROC(at91_pm_ulp0_mode)\n" - "> =\n" - "\n" + "> \n" "> +/*\n" "> + * void at91_pm_ulp1_mode(void)\n" "> + *\n" @@ -302,118 +279,66 @@ "> --- a/include/linux/clk/at91_pmc.h\n" "> +++ b/include/linux/clk/at91_pmc.h\n" "> @@ -59,8 +59,10 @@ extern void __iomem *at91_pmc_base;\n" - "> #define AT91_CKGR_MOR 0x20 /* Main O=\n" - "scillator Register [not on SAM9RL] */\n" - "> #define AT91_PMC_MOSCEN (1 << 0) /=\n" - "* Main Oscillator Enable */\n" - "> #define AT91_PMC_OSCBYPASS (1 << 1) /=\n" - "* Oscillator Bypass */\n" - "> +#define AT91_PMC_WAITMODE (1 << 2) /=\n" - "* Wait Mode Command */\n" - "> #define AT91_PMC_MOSCRCEN (1 << 3) /=\n" - "* Main On-Chip RC Oscillator Enable [some SAM9] */\n" - "> #define AT91_PMC_OSCOUNT (0xff << 8) /=\n" - "* Main Oscillator Start-up Time */\n" + "> #define AT91_CKGR_MOR 0x20 /* Main Oscillator Register [not on SAM9RL] */\n" + "> #define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */\n" + "> #define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass */\n" + "> +#define AT91_PMC_WAITMODE (1 << 2) /* Wait Mode Command */\n" + "> #define AT91_PMC_MOSCRCEN (1 << 3) /* Main On-Chip RC Oscillator Enable [some SAM9] */\n" + "> #define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */\n" "> +#define AT91_PMC_KEY_MASK (0xff << 16)\n" - "> #define AT91_PMC_KEY (0x37 << 16) /=\n" - "* MOR Writing Key */\n" - "> #define AT91_PMC_MOSCSEL (1 << 24) /=\n" - "* Main Oscillator Selection [some SAM9] */\n" - "> #define AT91_PMC_CFDEN (1 << 25) /=\n" - "* Clock Failure Detector Enable [some SAM9] */\n" + "> #define AT91_PMC_KEY (0x37 << 16) /* MOR Writing Key */\n" + "> #define AT91_PMC_MOSCSEL (1 << 24) /* Main Oscillator Selection [some SAM9] */\n" + "> #define AT91_PMC_CFDEN (1 << 25) /* Clock Failure Detector Enable [some SAM9] */\n" "> @@ -166,6 +168,38 @@ extern void __iomem *at91_pmc_base;\n" - "> #define AT91_PMC_CFDEV (1 << 18) /=\n" - "* Clock Failure Detector Event [some SAM9] */\n" - "> #define AT91_PMC_IMR 0x6c /* Interr=\n" - "upt Mask Register */\n" - "> =\n" - "\n" - "> +#define AT91_PMC_FSMR 0x70 /* Fast Startup M=\n" - "ode Register */\n" - "> +#define AT91_PMC_FSTT0 (1 << 0) /=\n" - "* Fast Startup from WKUP Pin Enable */\n" - "> +#define AT91_PMC_FSTT1 (1 << 1) /=\n" - "* Fast Startup from Security Module Enable */\n" - "> +#define AT91_PMC_FSTT2 (1 << 2) /=\n" - "* Fast Startup from PIOBU0 Input Enable */\n" - "> +#define AT91_PMC_FSTT3 (1 << 3) /=\n" - "* Fast Startup from PIOBU1 Input Enable */\n" - "> +#define AT91_PMC_FSTT4 (1 << 4) /=\n" - "* Fast Startup from PIOBU2 Input Enable */\n" - "> +#define AT91_PMC_FSTT5 (1 << 5) /=\n" - "* Fast Startup from PIOBU3 Input Enable */\n" - "> +#define AT91_PMC_FSTT6 (1 << 6) /=\n" - "* Fast Startup from PIOBU4 Input Enable */\n" - "> +#define AT91_PMC_FSTT7 (1 << 7) /=\n" - "* Fast Startup from PIOBU5 Input Enable */\n" - "> +#define AT91_PMC_FSTT8 (1 << 8) /=\n" - "* Fast Startup from PIOBU6 Input Enable */\n" - "> +#define AT91_PMC_FSTT9 (1 << 9) /=\n" - "* Fast Startup from PIOBU7 Input Enable */\n" - "> +#define AT91_PMC_FSTT10 (1 << 10) /=\n" - "* Fast Startup from GMAC Wake-up On LAN Enable */\n" - "> +#define AT91_PMC_RTCAL (1 << 17) /=\n" - "* Fast Startup from RTC Alarm Enable */\n" - "> +#define AT91_PMC_USBAL (1 << 18) /=\n" - "* Fast Startup from USB Resume Enable */\n" - "> +#define AT91_PMC_SDMMC_CD (1 << 19) /=\n" - "* Fast Startup from SDMMC Card Detect Enable */\n" - "> +#define AT91_PMC_LPM (1 << 20) /=\n" - "* Low-power Mode */\n" - "> +#define AT91_PMC_RXLP_MCE (1 << 24) /=\n" - "* Fast Startup from Backup UART Receive Match Condition Enable */\n" - "> +#define AT91_PMC_ACC_CE (1 << 25) /=\n" - "* Fast Startup from Analog Comparator Controller Comparison Enable*/\n" - "> +\n" - "> +#define AT91_PMC_FSPR 0x74 /* Fast Startup P=\n" - "olarity Register */\n" - "> +#define AT91_PMC_FSTP0 (1 << 0) /=\n" - "* WKUP Pin Polarity for Fast Startup */\n" - "> +#define AT91_PMC_FSTP1 (1 << 1) /=\n" - "* Security Module Polarity for Fast Startup */\n" - "> +#define AT91_PMC_FSTP2 (1 << 2) /=\n" - "* PIOBU0 Pin Polarity for Fast Startup */\n" - "> +#define AT91_PMC_FSTP3 (1 << 3) /=\n" - "* PIOBU1 Pin Polarity for Fast Startup */\n" - "> +#define AT91_PMC_FSTP4 (1 << 4) /=\n" - "* PIOBU2 Pin Polarity for Fast Startup */\n" - "> +#define AT91_PMC_FSTP5 (1 << 5) /=\n" - "* PIOBU3 Pin Polarity for Fast Startup */\n" - "> +#define AT91_PMC_FSTP6 (1 << 6) /=\n" - "* PIOBU4 Pin Polarity for Fast Startup */\n" - "> +#define AT91_PMC_FSTP7 (1 << 7) /=\n" - "* PIOBU5 Pin Polarity for Fast Startup */\n" - "> +#define AT91_PMC_FSTP8 (1 << 8) /=\n" - "* PIOBU6 Pin Polarity for Fast Startup */\n" - "> +#define AT91_PMC_FSTP9 (1 << 9) /=\n" - "* PIOBU7 Pin Polarity for Fast Startup */\n" - "> +#define AT91_PMC_FSTP10 (1 << 10) /=\n" - "* GMAC Wake-up On LAN Polarity for Fast Startup */\n" - "> +\n" - "> #define AT91_PMC_PLLICPR 0x80 /* PLL Charge Pum=\n" - "p Current Register */\n" - "> =\n" - "\n" - "> #define AT91_PMC_PROT 0xe4 /* Write Protect =\n" - "Mode Register [some SAM9] */\n" + "> #define AT91_PMC_CFDEV (1 << 18) /* Clock Failure Detector Event [some SAM9] */\n" + "> #define AT91_PMC_IMR 0x6c /* Interrupt Mask Register */\n" + "> \n" + "> +#define AT91_PMC_FSMR 0x70 /* Fast Startup Mode Register */\n" + "> +#define AT91_PMC_FSTT0 (1 << 0) /* Fast Startup from WKUP Pin Enable */\n" + "> +#define AT91_PMC_FSTT1 (1 << 1) /* Fast Startup from Security Module Enable */\n" + "> +#define AT91_PMC_FSTT2 (1 << 2) /* Fast Startup from PIOBU0 Input Enable */\n" + "> +#define AT91_PMC_FSTT3 (1 << 3) /* Fast Startup from PIOBU1 Input Enable */\n" + "> +#define AT91_PMC_FSTT4 (1 << 4) /* Fast Startup from PIOBU2 Input Enable */\n" + "> +#define AT91_PMC_FSTT5 (1 << 5) /* Fast Startup from PIOBU3 Input Enable */\n" + "> +#define AT91_PMC_FSTT6 (1 << 6) /* Fast Startup from PIOBU4 Input Enable */\n" + "> +#define AT91_PMC_FSTT7 (1 << 7) /* Fast Startup from PIOBU5 Input Enable */\n" + "> +#define AT91_PMC_FSTT8 (1 << 8) /* Fast Startup from PIOBU6 Input Enable */\n" + "> +#define AT91_PMC_FSTT9 (1 << 9) /* Fast Startup from PIOBU7 Input Enable */\n" + "> +#define AT91_PMC_FSTT10 (1 << 10) /* Fast Startup from GMAC Wake-up On LAN Enable */\n" + "> +#define AT91_PMC_RTCAL (1 << 17) /* Fast Startup from RTC Alarm Enable */\n" + "> +#define AT91_PMC_USBAL (1 << 18) /* Fast Startup from USB Resume Enable */\n" + "> +#define AT91_PMC_SDMMC_CD (1 << 19) /* Fast Startup from SDMMC Card Detect Enable */\n" + "> +#define AT91_PMC_LPM (1 << 20) /* Low-power Mode */\n" + "> +#define AT91_PMC_RXLP_MCE (1 << 24) /* Fast Startup from Backup UART Receive Match Condition Enable */\n" + "> +#define AT91_PMC_ACC_CE (1 << 25) /* Fast Startup from Analog Comparator Controller Comparison Enable*/\n" + "> +\n" + "> +#define AT91_PMC_FSPR 0x74 /* Fast Startup Polarity Register */\n" + "> +#define AT91_PMC_FSTP0 (1 << 0) /* WKUP Pin Polarity for Fast Startup */\n" + "> +#define AT91_PMC_FSTP1 (1 << 1) /* Security Module Polarity for Fast Startup */\n" + "> +#define AT91_PMC_FSTP2 (1 << 2) /* PIOBU0 Pin Polarity for Fast Startup */\n" + "> +#define AT91_PMC_FSTP3 (1 << 3) /* PIOBU1 Pin Polarity for Fast Startup */\n" + "> +#define AT91_PMC_FSTP4 (1 << 4) /* PIOBU2 Pin Polarity for Fast Startup */\n" + "> +#define AT91_PMC_FSTP5 (1 << 5) /* PIOBU3 Pin Polarity for Fast Startup */\n" + "> +#define AT91_PMC_FSTP6 (1 << 6) /* PIOBU4 Pin Polarity for Fast Startup */\n" + "> +#define AT91_PMC_FSTP7 (1 << 7) /* PIOBU5 Pin Polarity for Fast Startup */\n" + "> +#define AT91_PMC_FSTP8 (1 << 8) /* PIOBU6 Pin Polarity for Fast Startup */\n" + "> +#define AT91_PMC_FSTP9 (1 << 9) /* PIOBU7 Pin Polarity for Fast Startup */\n" + "> +#define AT91_PMC_FSTP10 (1 << 10) /* GMAC Wake-up On LAN Polarity for Fast Startup */\n" + "> +\n" + "> #define AT91_PMC_PLLICPR 0x80 /* PLL Charge Pump Current Register */\n" + "> \n" + "> #define AT91_PMC_PROT 0xe4 /* Write Protect Mode Register [some SAM9] */\n" "> @@ -177,6 +211,8 @@ extern void __iomem *at91_pmc_base;\n" - "> #define AT91_PMC_WPVS (0x1 << 0) /=\n" - "* Write Protect Violation Status */\n" - "> #define AT91_PMC_WPVSRC (0xffff << 8) /=\n" - "* Write Protect Violation Source */\n" - "> =\n" - "\n" + "> #define AT91_PMC_WPVS (0x1 << 0) /* Write Protect Violation Status */\n" + "> #define AT91_PMC_WPVSRC (0xffff << 8) /* Write Protect Violation Source */\n" + "> \n" "> +#define AT91_PMC_VERSION 0xfc\n" "> +\n" - "> #define AT91_PMC_PCER1 0x100 /* Peripheral Clo=\n" - "ck Enable Register 1 [SAMA5 only]*/\n" - "> #define AT91_PMC_PCDR1 0x104 /* Peripheral Clo=\n" - "ck Enable Register 1 */\n" - "> #define AT91_PMC_PCSR1 0x108 /* Peripheral Clo=\n" - "ck Enable Register 1 */\n" - "> -- =\n" - "\n" + "> #define AT91_PMC_PCER1 0x100 /* Peripheral Clock Enable Register 1 [SAMA5 only]*/\n" + "> #define AT91_PMC_PCDR1 0x104 /* Peripheral Clock Enable Register 1 */\n" + "> #define AT91_PMC_PCSR1 0x108 /* Peripheral Clock Enable Register 1 */\n" + "> -- \n" "> 1.7.9.5\n" - >=20 + > -f9e4333820332aa9a2710ff730fba23e9f7e998da9db1c0d79128714b42154e3 +4e305b41a379ae344c3d436c0d78b231d233f81e2a5147dde6af1afe78d8d02a
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