From: Tony Lindgren <tony@atomide.com>
To: Tero Kristo <t-kristo@ti.com>
Cc: linux-clk@vger.kernel.org, linux-omap@vger.kernel.org,
sboyd@codeaurora.org, mturquette@baylibre.com,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCHv2] clk: ti: omap5+: dpll: implement errata i810
Date: Wed, 16 Dec 2015 09:16:50 -0800 [thread overview]
Message-ID: <20151216171650.GS23396@atomide.com> (raw)
In-Reply-To: <1450256530-10251-1-git-send-email-t-kristo@ti.com>
* Tero Kristo <t-kristo@ti.com> [151216 01:00]:
> Errata i810 states that DPLL controller can get stuck while transitioning
> to a power saving state, while its M/N ratio is being re-programmed.
>
> As a workaround, before re-programming the M/N ratio, SW has to ensure
> the DPLL cannot start an idle state transition. SW can disable DPLL
> idling by setting the DPLL AUTO_DPLL_MODE=0 or keeping a clock request
> active by setting a dependent clock domain in SW_WKUP.
>
> This errata is known to impact OMAP5 and DRA7 chips, but lets enable it
> unconditionally to avoid any potential problems with earlier generation
> SoCs also.
>
> Signed-off-by: Tero Kristo <t-kristo@ti.com>
> ---
> v2: made the fix to be applied unconditionally on all OMAP3+ SoCs
Thanks looks good to me now:
Acked-by: Tony Lindgren <tony@atomide.com>
WARNING: multiple messages have this Message-ID (diff)
From: tony@atomide.com (Tony Lindgren)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCHv2] clk: ti: omap5+: dpll: implement errata i810
Date: Wed, 16 Dec 2015 09:16:50 -0800 [thread overview]
Message-ID: <20151216171650.GS23396@atomide.com> (raw)
In-Reply-To: <1450256530-10251-1-git-send-email-t-kristo@ti.com>
* Tero Kristo <t-kristo@ti.com> [151216 01:00]:
> Errata i810 states that DPLL controller can get stuck while transitioning
> to a power saving state, while its M/N ratio is being re-programmed.
>
> As a workaround, before re-programming the M/N ratio, SW has to ensure
> the DPLL cannot start an idle state transition. SW can disable DPLL
> idling by setting the DPLL AUTO_DPLL_MODE=0 or keeping a clock request
> active by setting a dependent clock domain in SW_WKUP.
>
> This errata is known to impact OMAP5 and DRA7 chips, but lets enable it
> unconditionally to avoid any potential problems with earlier generation
> SoCs also.
>
> Signed-off-by: Tero Kristo <t-kristo@ti.com>
> ---
> v2: made the fix to be applied unconditionally on all OMAP3+ SoCs
Thanks looks good to me now:
Acked-by: Tony Lindgren <tony@atomide.com>
next prev parent reply other threads:[~2015-12-16 17:16 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-12-16 9:02 [PATCHv2] clk: ti: omap5+: dpll: implement errata i810 Tero Kristo
2015-12-16 9:02 ` Tero Kristo
2015-12-16 9:02 ` Tero Kristo
2015-12-16 17:16 ` Tony Lindgren [this message]
2015-12-16 17:16 ` Tony Lindgren
2015-12-23 0:37 ` Michael Turquette
2015-12-23 0:37 ` Michael Turquette
2015-12-23 0:37 ` Michael Turquette
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