From: Thierry Reding <thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
To: Wei Ni <wni-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Cc: rui.zhang-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org,
mikko.perttunen-/1wQRMveznE@public.gmane.org,
swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org,
linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Subject: Re: [PATCH V1 04/10] thermal: tegra: add T210-specific SOC_THERM driver
Date: Wed, 13 Jan 2016 16:06:56 +0100 [thread overview]
Message-ID: <20160113150656.GD2588@ulmo> (raw)
In-Reply-To: <1452671929-32740-5-git-send-email-wni-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
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On Wed, Jan 13, 2016 at 03:58:43PM +0800, Wei Ni wrote:
[...]
> diff --git a/drivers/thermal/tegra/tegra_soctherm_fuse.c b/drivers/thermal/tegra/tegra_soctherm_fuse.c
> index 7c608698f1ae..22f402240672 100644
> --- a/drivers/thermal/tegra/tegra_soctherm_fuse.c
> +++ b/drivers/thermal/tegra/tegra_soctherm_fuse.c
> @@ -28,6 +28,17 @@
> #define FUSE_TSENSOR_COMMON 0x180
>
> /*
> + * T210: Layout of bits in FUSE_TSENSOR_COMMON:
> + * 3 2 1 0
> + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
> + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
> + * | BASE_FT | BASE_CP | SHFT_FT | SHIFT_CP |
> + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
> + *
> + * In chips prior to T210, this fuse was incorrectly sized as 26 bits,
> + * and didn't hold SHIFT_CP in [31:26]. Therefore these missing six bits
The above diagram aso doesn't contain SHIFT_CP in bits [31:26] but
rather in bits [5:0]. Which one is correct: the text or the diagram?
Thierry
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WARNING: multiple messages have this Message-ID (diff)
From: Thierry Reding <thierry.reding@gmail.com>
To: Wei Ni <wni@nvidia.com>
Cc: rui.zhang@intel.com, mikko.perttunen@kapsi.fi,
swarren@wwwdotorg.org, linux-tegra@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH V1 04/10] thermal: tegra: add T210-specific SOC_THERM driver
Date: Wed, 13 Jan 2016 16:06:56 +0100 [thread overview]
Message-ID: <20160113150656.GD2588@ulmo> (raw)
In-Reply-To: <1452671929-32740-5-git-send-email-wni@nvidia.com>
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On Wed, Jan 13, 2016 at 03:58:43PM +0800, Wei Ni wrote:
[...]
> diff --git a/drivers/thermal/tegra/tegra_soctherm_fuse.c b/drivers/thermal/tegra/tegra_soctherm_fuse.c
> index 7c608698f1ae..22f402240672 100644
> --- a/drivers/thermal/tegra/tegra_soctherm_fuse.c
> +++ b/drivers/thermal/tegra/tegra_soctherm_fuse.c
> @@ -28,6 +28,17 @@
> #define FUSE_TSENSOR_COMMON 0x180
>
> /*
> + * T210: Layout of bits in FUSE_TSENSOR_COMMON:
> + * 3 2 1 0
> + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
> + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
> + * | BASE_FT | BASE_CP | SHFT_FT | SHIFT_CP |
> + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
> + *
> + * In chips prior to T210, this fuse was incorrectly sized as 26 bits,
> + * and didn't hold SHIFT_CP in [31:26]. Therefore these missing six bits
The above diagram aso doesn't contain SHIFT_CP in bits [31:26] but
rather in bits [5:0]. Which one is correct: the text or the diagram?
Thierry
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next prev parent reply other threads:[~2016-01-13 15:06 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-01-13 7:58 [PATCH V1 00/10] Add T210 support in tegra_soctherm Wei Ni
2016-01-13 7:58 ` Wei Ni
2016-01-13 7:58 ` [PATCH V1 01/10] thermal: tegra: move tegra thermal files into tegra directory Wei Ni
2016-01-13 7:58 ` Wei Ni
[not found] ` <1452671929-32740-2-git-send-email-wni-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2016-01-13 14:24 ` Thierry Reding
2016-01-13 14:24 ` Thierry Reding
2016-01-14 5:33 ` Wei Ni
2016-01-14 5:33 ` Wei Ni
2016-01-13 7:58 ` [PATCH V1 02/10] thermal: tegra: combine sensor group-related data Wei Ni
2016-01-13 7:58 ` Wei Ni
2016-01-13 14:31 ` Thierry Reding
2016-01-14 5:40 ` Wei Ni
2016-01-14 5:40 ` Wei Ni
2016-01-13 7:58 ` [PATCH V1 03/10] thermal: tegra: split tegra_soctherm driver Wei Ni
2016-01-13 7:58 ` Wei Ni
[not found] ` <1452671929-32740-4-git-send-email-wni-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2016-01-13 15:04 ` Thierry Reding
2016-01-13 15:04 ` Thierry Reding
2016-01-14 9:54 ` Wei Ni
2016-01-14 9:54 ` Wei Ni
2016-01-13 7:58 ` [PATCH V1 04/10] thermal: tegra: add T210-specific SOC_THERM driver Wei Ni
2016-01-13 7:58 ` Wei Ni
[not found] ` <1452671929-32740-5-git-send-email-wni-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2016-01-13 15:06 ` Thierry Reding [this message]
2016-01-13 15:06 ` Thierry Reding
2016-01-14 10:18 ` Wei Ni
2016-01-14 10:18 ` Wei Ni
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