From: Thierry Reding <thierry.reding@gmail.com>
To: Rhyland Klein <rklein@nvidia.com>
Cc: Peter De Schrijver <pdeschrijver@nvidia.com>,
Mike Turquette <mturquette@baylibre.com>,
Stephen Warren <swarren@wwwdotorg.org>,
Stephen Boyd <sboyd@codeaurora.org>,
Alexandre Courbot <gnurou@gmail.com>,
Bill Huang <bilhuang@nvidia.com>, Jim Lin <jilin@nvidia.com>,
Benson Leung <bleung@chromium.org>,
linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH 9/9] clk: tegra210: Initialize PLL_D2 to a sane rate
Date: Wed, 13 Jan 2016 18:28:56 +0100 [thread overview]
Message-ID: <20160113172856.GT2588@ulmo> (raw)
In-Reply-To: <56967ADD.8090904@nvidia.com>
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On Wed, Jan 13, 2016 at 11:27:09AM -0500, Rhyland Klein wrote:
> On 1/13/2016 9:03 AM, Thierry Reding wrote:
> > * PGP Signed by an unknown key
> >
> > On Fri, Jan 08, 2016 at 01:45:14PM -0500, Rhyland Klein wrote:
> >> Initialize PLL_D2 to a sane rate at the start of the day.
> >>
> >> Signed-off-by: Rhyland Klein <rklein@nvidia.com>
> >> ---
> >> drivers/clk/tegra/clk-tegra210.c | 1 +
> >> 1 file changed, 1 insertion(+)
> >
> > There are a lot of assumptions in this commit message. I'm asking myself
> > why does it need to be initialized to any rate at all? Isn't it up to
> > the user driver to set the PLL to whatever it knows to be a sane rate?
> > Why is 594 MHz a sane rate?
> >
> > A good commit message should answer those questions.
> >
>
> Thanks. This patch came about in response to some work with
> suspend/resume logic in the ChromeOS kernel. In the suspend/resume patch
> there, it reads all clk rates and caches them in suspend, then re-sets
> them on resume. We hadn't been using pll_d2 at all, and its rate (when
> read in suspend()) came back as 0. Then in resume, we would tr to set
> it, clk_set_rate(pll_d2, 0) and would generate a warning/error that 0
> wasn't a valid rate.
>
> As for the specific rate I chose, I simply took one off the table of
> supported frequencies in the clk-tegra210 code, so that it was non-zero.
>
> Since we don't support suspend/resume right now in the clk drivers, I
> don't think its urgent to merge this patch. I can drop in in the next
> rev if thats easier.
Yes, that would be my preference as well. Once suspend/resume support
gets added we should run into this again. Setting the rate so some sane
value (the meaning of which is highly dependent on the use-case) sounds
to me more like a workaround rather than a real fix.
pll_d2 is used for display, so I don't quite understand why we'd have
to restore the rate on resume, since DRM/KMS would set it to whatever
it needs at a higher level anyway. Perhaps this will turn out to be a
non-issue upstream.
Thierry
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WARNING: multiple messages have this Message-ID (diff)
From: Thierry Reding <thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
To: Rhyland Klein <rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Cc: Peter De Schrijver
<pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>,
Mike Turquette
<mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>,
Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>,
Stephen Boyd <sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>,
Alexandre Courbot
<gnurou-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
Bill Huang <bilhuang-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>,
Jim Lin <jilin-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>,
Benson Leung <bleung-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>,
linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Subject: Re: [PATCH 9/9] clk: tegra210: Initialize PLL_D2 to a sane rate
Date: Wed, 13 Jan 2016 18:28:56 +0100 [thread overview]
Message-ID: <20160113172856.GT2588@ulmo> (raw)
In-Reply-To: <56967ADD.8090904-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
[-- Attachment #1: Type: text/plain, Size: 2114 bytes --]
On Wed, Jan 13, 2016 at 11:27:09AM -0500, Rhyland Klein wrote:
> On 1/13/2016 9:03 AM, Thierry Reding wrote:
> > * PGP Signed by an unknown key
> >
> > On Fri, Jan 08, 2016 at 01:45:14PM -0500, Rhyland Klein wrote:
> >> Initialize PLL_D2 to a sane rate at the start of the day.
> >>
> >> Signed-off-by: Rhyland Klein <rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> >> ---
> >> drivers/clk/tegra/clk-tegra210.c | 1 +
> >> 1 file changed, 1 insertion(+)
> >
> > There are a lot of assumptions in this commit message. I'm asking myself
> > why does it need to be initialized to any rate at all? Isn't it up to
> > the user driver to set the PLL to whatever it knows to be a sane rate?
> > Why is 594 MHz a sane rate?
> >
> > A good commit message should answer those questions.
> >
>
> Thanks. This patch came about in response to some work with
> suspend/resume logic in the ChromeOS kernel. In the suspend/resume patch
> there, it reads all clk rates and caches them in suspend, then re-sets
> them on resume. We hadn't been using pll_d2 at all, and its rate (when
> read in suspend()) came back as 0. Then in resume, we would tr to set
> it, clk_set_rate(pll_d2, 0) and would generate a warning/error that 0
> wasn't a valid rate.
>
> As for the specific rate I chose, I simply took one off the table of
> supported frequencies in the clk-tegra210 code, so that it was non-zero.
>
> Since we don't support suspend/resume right now in the clk drivers, I
> don't think its urgent to merge this patch. I can drop in in the next
> rev if thats easier.
Yes, that would be my preference as well. Once suspend/resume support
gets added we should run into this again. Setting the rate so some sane
value (the meaning of which is highly dependent on the use-case) sounds
to me more like a workaround rather than a real fix.
pll_d2 is used for display, so I don't quite understand why we'd have
to restore the rate on resume, since DRM/KMS would set it to whatever
it needs at a higher level anyway. Perhaps this will turn out to be a
non-issue upstream.
Thierry
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next prev parent reply other threads:[~2016-01-13 17:28 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-01-08 18:45 [PATCH 0/9 REPOST] Tegra CLK Fixes Rhyland Klein
2016-01-08 18:45 ` [PATCH 1/9] clk: tegra: Fix divider on VI_I2C Rhyland Klein
2016-01-08 18:45 ` [PATCH 2/9] clk: tegra210: Remove improper flags for lock_enable Rhyland Klein
2016-01-08 18:45 ` [PATCH 3/9] clk: tegra210: Fix naming of MISC registers Rhyland Klein
2016-01-08 18:45 ` Rhyland Klein
2016-01-08 18:45 ` [PATCH 4/9] clk: tegra: Fix the misnaming of nvenc from msenc Rhyland Klein
2016-01-08 18:45 ` [PATCH 5/9] clk: tegra: pll: Fix potential sleeping-while-atomic Rhyland Klein
2016-01-08 18:45 ` [PATCH 6/9] clk: tegra210: fix pllx dyn step calculation Rhyland Klein
2016-01-08 18:45 ` [PATCH 7/9] clk: tegra: pll: Do not disable PLLE when under HW control Rhyland Klein
2016-01-08 18:45 ` [PATCH 8/9] clk: tegra: pll: Fix PLLE SS config Rhyland Klein
2016-01-13 14:00 ` Thierry Reding
2016-01-08 18:45 ` [PATCH 9/9] clk: tegra210: Initialize PLL_D2 to a sane rate Rhyland Klein
2016-01-13 14:03 ` Thierry Reding
2016-01-13 14:03 ` Thierry Reding
2016-01-13 16:27 ` Rhyland Klein
2016-01-13 16:27 ` Rhyland Klein
2016-01-13 17:28 ` Thierry Reding [this message]
2016-01-13 17:28 ` Thierry Reding
2016-01-13 14:05 ` [PATCH 0/9 REPOST] Tegra CLK Fixes Thierry Reding
-- strict thread matches above, loose matches on Subject: below --
2016-01-08 18:37 Rhyland Klein
2016-01-08 18:37 ` [PATCH 9/9] clk: tegra210: Initialize PLL_D2 to a sane rate Rhyland Klein
2015-12-10 22:08 [PATCH 0/9] Tegra CLK Fixes Rhyland Klein
2015-12-10 22:08 ` [PATCH 9/9] clk: tegra210: Initialize PLL_D2 to a sane rate Rhyland Klein
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