Re: [PATCH] mips: scache: fix scache init with invalid line size.

[James Hogan <james.hogan@imgtec.com>]

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Hi Govindraj,

On Mon, Jan 18, 2016 at 02:18:26PM +0000, Govindraj Raja wrote:
> In current scache init cache line_size is determined from
> cpu config register, however if there there no scache
> then mips_sc_probe_cm3 function populates a invalid line_size of 2.
> 
> The invalid line_size can cause a NULL pointer deference
> during r4k_dma_cache_inv as r4k_blast_scache is populated based on
> line_size. Scache line_size of 2 is invalid option in r4k_blast_scache_setup.
> 
> This issue was faced during a MIPS I6400 based virtual platform bring up
> where scache was not available in virtual platform model.
> 
> Signed-off-by: Govindraj Raja <Govindraj.Raja@imgtec.com>
> ---
>  arch/mips/mm/sc-mips.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c
> index 3bd0597..6e422bc 100644
> --- a/arch/mips/mm/sc-mips.c
> +++ b/arch/mips/mm/sc-mips.c
> @@ -168,7 +168,8 @@ static int __init mips_sc_probe_cm3(void)
>  
>  	line_sz = cfg & CM_GCR_L2_CONFIG_LINE_SIZE_MSK;
>  	line_sz >>= CM_GCR_L2_CONFIG_LINE_SIZE_SHF;
> -	c->scache.linesz = 2 << line_sz;
> +	if (line_sz)
> +		c->scache.linesz = 2 << line_sz;

It seems wrong to clear MIPS_CACHE_NOT_PRESENT if we know there isn't a
cache actually present.

Cheers
James

>  
>  	assoc = cfg & CM_GCR_L2_CONFIG_ASSOC_MSK;
>  	assoc >>= CM_GCR_L2_CONFIG_ASSOC_SHF;
> -- 
> 2.5.0
> 

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