* [PATCH] drm/i915/skl/kbl: Add support for pipe fusing
@ 2016-01-18 14:11 Patrik Jakobsson
2016-01-18 14:50 ` [PATCH v2] " Patrik Jakobsson
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Patrik Jakobsson @ 2016-01-18 14:11 UTC (permalink / raw)
To: intel-gfx
On SKL and KBL we can have pipe A/B/C disabled by fuse settings. The
pipes must be fused in descending order (e.g. C, B+C, A+B+C). There are
several registers that can contain fuse settings so to simplify things
we keep around a mask in device info with bits for each disabled pipe.
This will also come in handy if the rule about the descending order is
changed on future platforms.
Signed-off-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
---
drivers/gpu/drm/i915/i915_dma.c | 34 ++++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_reg.h | 4 ++++
3 files changed, 39 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 988a380..2e9d47d 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -814,6 +814,40 @@ static void intel_device_info_runtime_init(struct drm_device *dev)
DRM_INFO("Display fused off, disabling\n");
info->num_pipes = 0;
}
+ } else if (info->num_pipes > 0 && INTEL_INFO(dev)->gen == 9) {
+ u32 fuse_strap = I915_READ(FUSE_STRAP);
+ u32 dfsm = I915_READ(SKL_DFSM);
+ bool invalid;
+ int num_bits;
+
+ if (dfsm & SKL_DFSM_PIPE_A_DISABLE)
+ info->pipe_disabled_mask |= BIT(PIPE_A);
+ if (dfsm & SKL_DFSM_PIPE_B_DISABLE)
+ info->pipe_disabled_mask |= BIT(PIPE_B);
+ if (dfsm & SKL_DFSM_PIPE_C_DISABLE)
+ info->pipe_disabled_mask |= BIT(PIPE_C);
+
+ if (fuse_strap & SKL_DISPLAY_PIPE_C_DISABLE)
+ info->pipe_disabled_mask |= BIT(PIPE_C);
+
+ num_bits = hweight8(info->pipe_disabled_mask);
+
+ switch (info->pipe_disabled_mask) {
+ case BIT(PIPE_A):
+ case BIT(PIPE_B):
+ case BIT(PIPE_A) | BIT(PIPE_B):
+ case BIT(PIPE_A) | BIT(PIPE_C):
+ invalid = true;
+ break;
+ default:
+ invalid = false;
+ }
+
+ if (num_bits > info->num_pipes || invalid)
+ DRM_ERROR("invalid pipe fuse configuration: 0x%x\n",
+ info->pipe_disabled_mask);
+ else
+ info->num_pipes -= num_bits;
}
/* Initialize slice/subslice/EU info */
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f0f75d7..2b4783c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -792,6 +792,7 @@ struct intel_device_info {
u8 num_pipes:3;
u8 num_sprites[I915_MAX_PIPES];
u8 gen;
+ u8 pipe_disabled_mask;
u8 ring_mask; /* Rings supported by the HW */
DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
/* Register offsets for the various display pipes and transcoders */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7510d508..72f07e6 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5940,6 +5940,7 @@ enum skl_disp_power_wells {
#define ILK_INTERNAL_GRAPHICS_DISABLE (1 << 31)
#define ILK_INTERNAL_DISPLAY_DISABLE (1 << 30)
#define ILK_DISPLAY_DEBUG_DISABLE (1 << 29)
+#define SKL_DISPLAY_PIPE_C_DISABLE (1 << 28)
#define ILK_HDCP_DISABLE (1 << 25)
#define ILK_eDP_A_DISABLE (1 << 24)
#define HSW_CDCLK_LIMIT (1 << 24)
@@ -5986,6 +5987,9 @@ enum skl_disp_power_wells {
#define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23)
#define SKL_DFSM_CDCLK_LIMIT_450 (2 << 23)
#define SKL_DFSM_CDCLK_LIMIT_337_5 (3 << 23)
+#define SKL_DFSM_PIPE_A_DISABLE (1 << 30)
+#define SKL_DFSM_PIPE_B_DISABLE (1 << 21)
+#define SKL_DFSM_PIPE_C_DISABLE (1 << 28)
#define FF_SLICE_CS_CHICKEN2 _MMIO(0x20e4)
#define GEN9_TSG_BARRIER_ACK_DISABLE (1<<8)
--
2.5.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v2] drm/i915/skl/kbl: Add support for pipe fusing
2016-01-18 14:11 [PATCH] drm/i915/skl/kbl: Add support for pipe fusing Patrik Jakobsson
@ 2016-01-18 14:50 ` Patrik Jakobsson
2016-01-18 15:49 ` ✗ Fi.CI.BAT: failure for drm/i915/skl/kbl: Add support for pipe fusing (rev2) Patchwork
2016-01-18 16:01 ` [PATCH] drm/i915/skl/kbl: Add support for pipe fusing Ville Syrjälä
2 siblings, 0 replies; 6+ messages in thread
From: Patrik Jakobsson @ 2016-01-18 14:50 UTC (permalink / raw)
To: intel-gfx
On SKL and KBL we can have pipe A/B/C disabled by fuse settings. The
pipes must be fused in descending order (e.g. C, B+C, A+B+C). We simply
decrease info->num_pipes if we find a valid fused out config.
v2: Don't store the pipe disabled mask in device info (Damien)
Signed-off-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
---
drivers/gpu/drm/i915/i915_dma.c | 35 +++++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/i915_reg.h | 4 ++++
2 files changed, 39 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 44a896c..852b49a 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -814,6 +814,41 @@ static void intel_device_info_runtime_init(struct drm_device *dev)
DRM_INFO("Display fused off, disabling\n");
info->num_pipes = 0;
}
+ } else if (info->num_pipes > 0 && INTEL_INFO(dev)->gen == 9) {
+ u32 fuse_strap = I915_READ(FUSE_STRAP);
+ u32 dfsm = I915_READ(SKL_DFSM);
+ u8 disabled_mask = 0;
+ bool invalid;
+ int num_bits;
+
+ if (dfsm & SKL_DFSM_PIPE_A_DISABLE)
+ disabled_mask |= BIT(PIPE_A);
+ if (dfsm & SKL_DFSM_PIPE_B_DISABLE)
+ disabled_mask |= BIT(PIPE_B);
+ if (dfsm & SKL_DFSM_PIPE_C_DISABLE)
+ disabled_mask |= BIT(PIPE_C);
+
+ if (fuse_strap & SKL_DISPLAY_PIPE_C_DISABLE)
+ disabled_mask |= BIT(PIPE_C);
+
+ num_bits = hweight8(disabled_mask);
+
+ switch (disabled_mask) {
+ case BIT(PIPE_A):
+ case BIT(PIPE_B):
+ case BIT(PIPE_A) | BIT(PIPE_B):
+ case BIT(PIPE_A) | BIT(PIPE_C):
+ invalid = true;
+ break;
+ default:
+ invalid = false;
+ }
+
+ if (num_bits > info->num_pipes || invalid)
+ DRM_ERROR("invalid pipe fuse configuration: 0x%x\n",
+ disabled_mask);
+ else
+ info->num_pipes -= num_bits;
}
/* Initialize slice/subslice/EU info */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 556a458..39a965b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5945,6 +5945,7 @@ enum skl_disp_power_wells {
#define ILK_INTERNAL_GRAPHICS_DISABLE (1 << 31)
#define ILK_INTERNAL_DISPLAY_DISABLE (1 << 30)
#define ILK_DISPLAY_DEBUG_DISABLE (1 << 29)
+#define SKL_DISPLAY_PIPE_C_DISABLE (1 << 28)
#define ILK_HDCP_DISABLE (1 << 25)
#define ILK_eDP_A_DISABLE (1 << 24)
#define HSW_CDCLK_LIMIT (1 << 24)
@@ -5991,6 +5992,9 @@ enum skl_disp_power_wells {
#define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23)
#define SKL_DFSM_CDCLK_LIMIT_450 (2 << 23)
#define SKL_DFSM_CDCLK_LIMIT_337_5 (3 << 23)
+#define SKL_DFSM_PIPE_A_DISABLE (1 << 30)
+#define SKL_DFSM_PIPE_B_DISABLE (1 << 21)
+#define SKL_DFSM_PIPE_C_DISABLE (1 << 28)
#define FF_SLICE_CS_CHICKEN2 _MMIO(0x20e4)
#define GEN9_TSG_BARRIER_ACK_DISABLE (1<<8)
--
2.5.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread
* ✗ Fi.CI.BAT: failure for drm/i915/skl/kbl: Add support for pipe fusing (rev2)
2016-01-18 14:11 [PATCH] drm/i915/skl/kbl: Add support for pipe fusing Patrik Jakobsson
2016-01-18 14:50 ` [PATCH v2] " Patrik Jakobsson
@ 2016-01-18 15:49 ` Patchwork
2016-01-18 16:01 ` [PATCH] drm/i915/skl/kbl: Add support for pipe fusing Ville Syrjälä
2 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2016-01-18 15:49 UTC (permalink / raw)
To: Patrik Jakobsson; +Cc: intel-gfx
== Summary ==
Built on 98ee62c2326e0b6881eb0f427895aab745febf6f drm-intel-nightly: 2016y-01m-18d-14h-18m-27s UTC integration manifest
Test gem_ctx_basic:
pass -> FAIL (bdw-ultra)
Test gem_storedw_loop:
Subgroup basic-render:
pass -> DMESG-WARN (bdw-nuci7) UNSTABLE
pass -> DMESG-WARN (skl-i7k-2) UNSTABLE
Test kms_pipe_crc_basic:
Subgroup read-crc-pipe-b:
pass -> DMESG-WARN (ilk-hp8440p)
Subgroup suspend-read-crc-pipe-a:
dmesg-warn -> PASS (snb-x220t)
bdw-nuci7 total:140 pass:130 dwarn:1 dfail:0 fail:0 skip:9
bdw-ultra total:140 pass:131 dwarn:1 dfail:1 fail:1 skip:6
bsw-nuc-2 total:143 pass:117 dwarn:2 dfail:0 fail:0 skip:24
byt-nuc total:143 pass:125 dwarn:3 dfail:0 fail:0 skip:15
hsw-brixbox total:143 pass:136 dwarn:0 dfail:0 fail:0 skip:7
hsw-gt2 total:143 pass:139 dwarn:0 dfail:0 fail:0 skip:4
ilk-hp8440p total:143 pass:101 dwarn:4 dfail:0 fail:0 skip:38
ivb-t430s total:137 pass:124 dwarn:3 dfail:4 fail:0 skip:6
skl-i5k-2 total:143 pass:134 dwarn:1 dfail:0 fail:0 skip:8
skl-i7k-2 total:143 pass:133 dwarn:2 dfail:0 fail:0 skip:8
snb-dellxps total:143 pass:124 dwarn:5 dfail:0 fail:0 skip:14
snb-x220t total:143 pass:124 dwarn:5 dfail:0 fail:1 skip:13
Results at /archive/results/CI_IGT_test/Patchwork_1213/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] drm/i915/skl/kbl: Add support for pipe fusing
2016-01-18 14:11 [PATCH] drm/i915/skl/kbl: Add support for pipe fusing Patrik Jakobsson
2016-01-18 14:50 ` [PATCH v2] " Patrik Jakobsson
2016-01-18 15:49 ` ✗ Fi.CI.BAT: failure for drm/i915/skl/kbl: Add support for pipe fusing (rev2) Patchwork
@ 2016-01-18 16:01 ` Ville Syrjälä
2016-01-18 16:18 ` Patrik Jakobsson
2016-01-19 16:13 ` Patrik Jakobsson
2 siblings, 2 replies; 6+ messages in thread
From: Ville Syrjälä @ 2016-01-18 16:01 UTC (permalink / raw)
To: Patrik Jakobsson; +Cc: intel-gfx
On Mon, Jan 18, 2016 at 03:11:57PM +0100, Patrik Jakobsson wrote:
> On SKL and KBL we can have pipe A/B/C disabled by fuse settings. The
> pipes must be fused in descending order (e.g. C, B+C, A+B+C). There are
> several registers that can contain fuse settings so to simplify things
> we keep around a mask in device info with bits for each disabled pipe.
> This will also come in handy if the rule about the descending order is
> changed on future platforms.
>
> Signed-off-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_dma.c | 34 ++++++++++++++++++++++++++++++++++
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/i915_reg.h | 4 ++++
> 3 files changed, 39 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
> index 988a380..2e9d47d 100644
> --- a/drivers/gpu/drm/i915/i915_dma.c
> +++ b/drivers/gpu/drm/i915/i915_dma.c
> @@ -814,6 +814,40 @@ static void intel_device_info_runtime_init(struct drm_device *dev)
> DRM_INFO("Display fused off, disabling\n");
> info->num_pipes = 0;
> }
> + } else if (info->num_pipes > 0 && INTEL_INFO(dev)->gen == 9) {
> + u32 fuse_strap = I915_READ(FUSE_STRAP);
> + u32 dfsm = I915_READ(SKL_DFSM);
> + bool invalid;
> + int num_bits;
> +
> + if (dfsm & SKL_DFSM_PIPE_A_DISABLE)
> + info->pipe_disabled_mask |= BIT(PIPE_A);
> + if (dfsm & SKL_DFSM_PIPE_B_DISABLE)
> + info->pipe_disabled_mask |= BIT(PIPE_B);
> + if (dfsm & SKL_DFSM_PIPE_C_DISABLE)
> + info->pipe_disabled_mask |= BIT(PIPE_C);
> +
> + if (fuse_strap & SKL_DISPLAY_PIPE_C_DISABLE)
> + info->pipe_disabled_mask |= BIT(PIPE_C);
> +
> + num_bits = hweight8(info->pipe_disabled_mask);
> +
> + switch (info->pipe_disabled_mask) {
> + case BIT(PIPE_A):
> + case BIT(PIPE_B):
> + case BIT(PIPE_A) | BIT(PIPE_B):
> + case BIT(PIPE_A) | BIT(PIPE_C):
> + invalid = true;
> + break;
> + default:
> + invalid = false;
> + }
> +
> + if (num_bits > info->num_pipes || invalid)
> + DRM_ERROR("invalid pipe fuse configuration: 0x%x\n",
> + info->pipe_disabled_mask);
> + else
> + info->num_pipes -= num_bits;
> }
>
> /* Initialize slice/subslice/EU info */
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index f0f75d7..2b4783c 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -792,6 +792,7 @@ struct intel_device_info {
> u8 num_pipes:3;
> u8 num_sprites[I915_MAX_PIPES];
> u8 gen;
> + u8 pipe_disabled_mask;
> u8 ring_mask; /* Rings supported by the HW */
> DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
> /* Register offsets for the various display pipes and transcoders */
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 7510d508..72f07e6 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5940,6 +5940,7 @@ enum skl_disp_power_wells {
> #define ILK_INTERNAL_GRAPHICS_DISABLE (1 << 31)
> #define ILK_INTERNAL_DISPLAY_DISABLE (1 << 30)
> #define ILK_DISPLAY_DEBUG_DISABLE (1 << 29)
> +#define SKL_DISPLAY_PIPE_C_DISABLE (1 << 28)
Maybe you want to go review the other patch that wants to add this bit?
> #define ILK_HDCP_DISABLE (1 << 25)
> #define ILK_eDP_A_DISABLE (1 << 24)
> #define HSW_CDCLK_LIMIT (1 << 24)
> @@ -5986,6 +5987,9 @@ enum skl_disp_power_wells {
> #define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23)
> #define SKL_DFSM_CDCLK_LIMIT_450 (2 << 23)
> #define SKL_DFSM_CDCLK_LIMIT_337_5 (3 << 23)
> +#define SKL_DFSM_PIPE_A_DISABLE (1 << 30)
> +#define SKL_DFSM_PIPE_B_DISABLE (1 << 21)
> +#define SKL_DFSM_PIPE_C_DISABLE (1 << 28)
>
> #define FF_SLICE_CS_CHICKEN2 _MMIO(0x20e4)
> #define GEN9_TSG_BARRIER_ACK_DISABLE (1<<8)
> --
> 2.5.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] drm/i915/skl/kbl: Add support for pipe fusing
2016-01-18 16:01 ` [PATCH] drm/i915/skl/kbl: Add support for pipe fusing Ville Syrjälä
@ 2016-01-18 16:18 ` Patrik Jakobsson
2016-01-19 16:13 ` Patrik Jakobsson
1 sibling, 0 replies; 6+ messages in thread
From: Patrik Jakobsson @ 2016-01-18 16:18 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Mon, Jan 18, 2016 at 06:01:27PM +0200, Ville Syrjälä wrote:
> On Mon, Jan 18, 2016 at 03:11:57PM +0100, Patrik Jakobsson wrote:
> > On SKL and KBL we can have pipe A/B/C disabled by fuse settings. The
> > pipes must be fused in descending order (e.g. C, B+C, A+B+C). There are
> > several registers that can contain fuse settings so to simplify things
> > we keep around a mask in device info with bits for each disabled pipe.
> > This will also come in handy if the rule about the descending order is
> > changed on future platforms.
> >
> > Signed-off-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_dma.c | 34 ++++++++++++++++++++++++++++++++++
> > drivers/gpu/drm/i915/i915_drv.h | 1 +
> > drivers/gpu/drm/i915/i915_reg.h | 4 ++++
> > 3 files changed, 39 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
> > index 988a380..2e9d47d 100644
> > --- a/drivers/gpu/drm/i915/i915_dma.c
> > +++ b/drivers/gpu/drm/i915/i915_dma.c
> > @@ -814,6 +814,40 @@ static void intel_device_info_runtime_init(struct drm_device *dev)
> > DRM_INFO("Display fused off, disabling\n");
> > info->num_pipes = 0;
> > }
> > + } else if (info->num_pipes > 0 && INTEL_INFO(dev)->gen == 9) {
> > + u32 fuse_strap = I915_READ(FUSE_STRAP);
> > + u32 dfsm = I915_READ(SKL_DFSM);
> > + bool invalid;
> > + int num_bits;
> > +
> > + if (dfsm & SKL_DFSM_PIPE_A_DISABLE)
> > + info->pipe_disabled_mask |= BIT(PIPE_A);
> > + if (dfsm & SKL_DFSM_PIPE_B_DISABLE)
> > + info->pipe_disabled_mask |= BIT(PIPE_B);
> > + if (dfsm & SKL_DFSM_PIPE_C_DISABLE)
> > + info->pipe_disabled_mask |= BIT(PIPE_C);
> > +
> > + if (fuse_strap & SKL_DISPLAY_PIPE_C_DISABLE)
> > + info->pipe_disabled_mask |= BIT(PIPE_C);
> > +
> > + num_bits = hweight8(info->pipe_disabled_mask);
> > +
> > + switch (info->pipe_disabled_mask) {
> > + case BIT(PIPE_A):
> > + case BIT(PIPE_B):
> > + case BIT(PIPE_A) | BIT(PIPE_B):
> > + case BIT(PIPE_A) | BIT(PIPE_C):
> > + invalid = true;
> > + break;
> > + default:
> > + invalid = false;
> > + }
> > +
> > + if (num_bits > info->num_pipes || invalid)
> > + DRM_ERROR("invalid pipe fuse configuration: 0x%x\n",
> > + info->pipe_disabled_mask);
> > + else
> > + info->num_pipes -= num_bits;
> > }
> >
> > /* Initialize slice/subslice/EU info */
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index f0f75d7..2b4783c 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -792,6 +792,7 @@ struct intel_device_info {
> > u8 num_pipes:3;
> > u8 num_sprites[I915_MAX_PIPES];
> > u8 gen;
> > + u8 pipe_disabled_mask;
> > u8 ring_mask; /* Rings supported by the HW */
> > DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
> > /* Register offsets for the various display pipes and transcoders */
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 7510d508..72f07e6 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -5940,6 +5940,7 @@ enum skl_disp_power_wells {
> > #define ILK_INTERNAL_GRAPHICS_DISABLE (1 << 31)
> > #define ILK_INTERNAL_DISPLAY_DISABLE (1 << 30)
> > #define ILK_DISPLAY_DEBUG_DISABLE (1 << 29)
> > +#define SKL_DISPLAY_PIPE_C_DISABLE (1 << 28)
>
> Maybe you want to go review the other patch that wants to add this bit?
>
Thanks for the heads up, I hadn't seen that one from Gabriel. I'll let his patch
land first.
> > #define ILK_HDCP_DISABLE (1 << 25)
> > #define ILK_eDP_A_DISABLE (1 << 24)
> > #define HSW_CDCLK_LIMIT (1 << 24)
> > @@ -5986,6 +5987,9 @@ enum skl_disp_power_wells {
> > #define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23)
> > #define SKL_DFSM_CDCLK_LIMIT_450 (2 << 23)
> > #define SKL_DFSM_CDCLK_LIMIT_337_5 (3 << 23)
> > +#define SKL_DFSM_PIPE_A_DISABLE (1 << 30)
> > +#define SKL_DFSM_PIPE_B_DISABLE (1 << 21)
> > +#define SKL_DFSM_PIPE_C_DISABLE (1 << 28)
> >
> > #define FF_SLICE_CS_CHICKEN2 _MMIO(0x20e4)
> > #define GEN9_TSG_BARRIER_ACK_DISABLE (1<<8)
> > --
> > 2.5.0
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Ville Syrjälä
> Intel OTC
--
---
Intel Sweden AB Registered Office: Knarrarnasgatan 15, 164 40 Kista, Stockholm, Sweden Registration Number: 556189-6027
_______________________________________________
Intel-gfx mailing list
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] drm/i915/skl/kbl: Add support for pipe fusing
2016-01-18 16:01 ` [PATCH] drm/i915/skl/kbl: Add support for pipe fusing Ville Syrjälä
2016-01-18 16:18 ` Patrik Jakobsson
@ 2016-01-19 16:13 ` Patrik Jakobsson
1 sibling, 0 replies; 6+ messages in thread
From: Patrik Jakobsson @ 2016-01-19 16:13 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Mon, Jan 18, 2016 at 06:01:27PM +0200, Ville Syrjälä wrote:
> On Mon, Jan 18, 2016 at 03:11:57PM +0100, Patrik Jakobsson wrote:
> > On SKL and KBL we can have pipe A/B/C disabled by fuse settings. The
> > pipes must be fused in descending order (e.g. C, B+C, A+B+C). There are
> > several registers that can contain fuse settings so to simplify things
> > we keep around a mask in device info with bits for each disabled pipe.
> > This will also come in handy if the rule about the descending order is
> > changed on future platforms.
> >
> > Signed-off-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_dma.c | 34 ++++++++++++++++++++++++++++++++++
> > drivers/gpu/drm/i915/i915_drv.h | 1 +
> > drivers/gpu/drm/i915/i915_reg.h | 4 ++++
> > 3 files changed, 39 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
> > index 988a380..2e9d47d 100644
> > --- a/drivers/gpu/drm/i915/i915_dma.c
> > +++ b/drivers/gpu/drm/i915/i915_dma.c
> > @@ -814,6 +814,40 @@ static void intel_device_info_runtime_init(struct drm_device *dev)
> > DRM_INFO("Display fused off, disabling\n");
> > info->num_pipes = 0;
> > }
> > + } else if (info->num_pipes > 0 && INTEL_INFO(dev)->gen == 9) {
> > + u32 fuse_strap = I915_READ(FUSE_STRAP);
> > + u32 dfsm = I915_READ(SKL_DFSM);
> > + bool invalid;
> > + int num_bits;
> > +
> > + if (dfsm & SKL_DFSM_PIPE_A_DISABLE)
> > + info->pipe_disabled_mask |= BIT(PIPE_A);
> > + if (dfsm & SKL_DFSM_PIPE_B_DISABLE)
> > + info->pipe_disabled_mask |= BIT(PIPE_B);
> > + if (dfsm & SKL_DFSM_PIPE_C_DISABLE)
> > + info->pipe_disabled_mask |= BIT(PIPE_C);
> > +
> > + if (fuse_strap & SKL_DISPLAY_PIPE_C_DISABLE)
> > + info->pipe_disabled_mask |= BIT(PIPE_C);
> > +
> > + num_bits = hweight8(info->pipe_disabled_mask);
> > +
> > + switch (info->pipe_disabled_mask) {
> > + case BIT(PIPE_A):
> > + case BIT(PIPE_B):
> > + case BIT(PIPE_A) | BIT(PIPE_B):
> > + case BIT(PIPE_A) | BIT(PIPE_C):
> > + invalid = true;
> > + break;
> > + default:
> > + invalid = false;
> > + }
> > +
> > + if (num_bits > info->num_pipes || invalid)
> > + DRM_ERROR("invalid pipe fuse configuration: 0x%x\n",
> > + info->pipe_disabled_mask);
> > + else
> > + info->num_pipes -= num_bits;
> > }
> >
> > /* Initialize slice/subslice/EU info */
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index f0f75d7..2b4783c 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -792,6 +792,7 @@ struct intel_device_info {
> > u8 num_pipes:3;
> > u8 num_sprites[I915_MAX_PIPES];
> > u8 gen;
> > + u8 pipe_disabled_mask;
> > u8 ring_mask; /* Rings supported by the HW */
> > DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
> > /* Register offsets for the various display pipes and transcoders */
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 7510d508..72f07e6 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -5940,6 +5940,7 @@ enum skl_disp_power_wells {
> > #define ILK_INTERNAL_GRAPHICS_DISABLE (1 << 31)
> > #define ILK_INTERNAL_DISPLAY_DISABLE (1 << 30)
> > #define ILK_DISPLAY_DEBUG_DISABLE (1 << 29)
> > +#define SKL_DISPLAY_PIPE_C_DISABLE (1 << 28)
>
> Maybe you want to go review the other patch that wants to add this bit?
>
My bad, we shouldn't look at FUSE_STRAP on SKL+. I'll resend without it.
> > #define ILK_HDCP_DISABLE (1 << 25)
> > #define ILK_eDP_A_DISABLE (1 << 24)
> > #define HSW_CDCLK_LIMIT (1 << 24)
> > @@ -5986,6 +5987,9 @@ enum skl_disp_power_wells {
> > #define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23)
> > #define SKL_DFSM_CDCLK_LIMIT_450 (2 << 23)
> > #define SKL_DFSM_CDCLK_LIMIT_337_5 (3 << 23)
> > +#define SKL_DFSM_PIPE_A_DISABLE (1 << 30)
> > +#define SKL_DFSM_PIPE_B_DISABLE (1 << 21)
> > +#define SKL_DFSM_PIPE_C_DISABLE (1 << 28)
> >
> > #define FF_SLICE_CS_CHICKEN2 _MMIO(0x20e4)
> > #define GEN9_TSG_BARRIER_ACK_DISABLE (1<<8)
> > --
> > 2.5.0
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Ville Syrjälä
> Intel OTC
--
---
Intel Sweden AB Registered Office: Knarrarnasgatan 15, 164 40 Kista, Stockholm, Sweden Registration Number: 556189-6027
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2016-01-19 16:13 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2016-01-18 14:11 [PATCH] drm/i915/skl/kbl: Add support for pipe fusing Patrik Jakobsson
2016-01-18 14:50 ` [PATCH v2] " Patrik Jakobsson
2016-01-18 15:49 ` ✗ Fi.CI.BAT: failure for drm/i915/skl/kbl: Add support for pipe fusing (rev2) Patchwork
2016-01-18 16:01 ` [PATCH] drm/i915/skl/kbl: Add support for pipe fusing Ville Syrjälä
2016-01-18 16:18 ` Patrik Jakobsson
2016-01-19 16:13 ` Patrik Jakobsson
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