From: "Daniel Glöckner" <daniel-gl@gmx.net>
To: linux-clk@vger.kernel.org
Subject: Bits that affect several muxes
Date: Sat, 23 Jan 2016 00:37:37 +0100 [thread overview]
Message-ID: <20160122233737.GA15679@minime.bse> (raw)
Hi,
today at work I just realized that the i.MX6 clock tree is not correctly
modeled wrt. PLL bypassing since bypassing the PLL also bypasses all PFD
post dividers. I've seen this before on the jz4730 where disabling the
PLL also sets several clocks to the same source.
Maybe I haven't dug deep enough into the mail archive, but I couldn't
find any information on how to handle cases like these. Can this be
modeled with the existing clock primitives?
Best regards,
Daniel
next reply other threads:[~2016-01-22 23:37 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-01-22 23:37 Daniel Glöckner [this message]
2016-01-26 8:22 ` Bits that affect several muxes Vladimir Zapolskiy
2016-01-27 2:32 ` Daniel Glöckner
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