Re: Bits that affect several muxes

["Daniel Glöckner" <daniel-gl@gmx.net>]

Hi Vladimir,

I have added Shawn Guo to CC as the discussion shifts towards the i.MX6.
He wrote the existing i.MX6 PLL bypass code.

On Tue, Jan 26, 2016 at 10:22:15AM +0200, Vladimir Zapolskiy wrote:
> On 23.01.2016 01:37, Daniel Glöckner wrote:
> > today at work I just realized that the i.MX6 clock tree is not correctly
> > modeled wrt. PLL bypassing since bypassing the PLL also bypasses all PFD
> > post dividers. I've seen this before on the jz4730 where disabling the
> > PLL also sets several clocks to the same source.
> 
> could you please give a more detailed example for iMX6 (particular clock
> names, registers, bit fields from the Reference Manual)?

The i.MX6 reference manual says "For the PLL equipped with PFDs the
input reference clock is also bypassed to all PFDs outputs."

I have taken the time to measure the effect of putting the PLLs in
bypass by routing their output to an LVDS clock output on an i.MX6Q.
The results are:

 - All four PFD outputs of PLL2 are switched to the bypass source
   (LVDS1_CLK_SEL=2..5), even the undocumented PFD3
 - The PLL2 output itself (LVDS1_CLK_SEL=1) is not affected by bypass
 - USB1 PLL (LVDS1_CLK_SEL=12) and its PFDs (LVDS1_CLK_SEL=14..17) are
   _not_ affected by bypass
 - USB2 PLL (LVDS1_CLK_SEL=13) is affected by bypass
 - When the ENET PLL is in bypass, only PCIE REF (LVDS1_CLK_SEL=12) is
   switched to the bypass clock, ETHERNET REF and SATA REF
   (LVDS1_CLK_SEL=9, 11) still derive their clock from the ENET PLL
 - ARM, Audio, and Video PLL (LVDS1_CLK_SEL=0, 6, 7) are not affected
   by bypass

It also seems like the ENABLE bit has no effect on many of the PLLs
and only POWERDOWN stops the clock from being forwarded to the LVDS
output. Looks like someone at Freescale/NXP needs to fix some diagrams
in the reference manual.

Best regards,

  Daniel