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From: Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
To: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>
Cc: Ulf Hansson <ulf.hansson-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>,
	Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>,
	"linux-mmc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org"
	<linux-mmc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
	linux-arm-kernel
	<linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>,
	linux-kernel
	<linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
	linux-sunxi <linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org>
Subject: Re: [PATCH RFC 08/15] ARM: dts: sun6i: Add mmc3 pins for 8 bit emmc
Date: Sun, 24 Jan 2016 17:54:47 +0100	[thread overview]
Message-ID: <20160124165447.GA7908@lukather> (raw)
In-Reply-To: <CAGb2v66Ma7QmJpNO=Gv=ojrwL3n_MZm3H5XNKA2fpf_3AbOTBA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>

[-- Attachment #1: Type: text/plain, Size: 2729 bytes --]

Hi,

On Sat, Jan 23, 2016 at 07:04:54PM +0800, Chen-Yu Tsai wrote:
> Hi,
> 
> On Sat, Jan 23, 2016 at 4:31 AM, Maxime Ripard
> <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org> wrote:
> > Hi,
> >
> > On Thu, Jan 21, 2016 at 01:26:35PM +0800, Chen-Yu Tsai wrote:
> >> mmc2 and mmc3 are available on the same pins, with different mux values.
> >> However, only mmc3 supports 8 bit DDR transfer modes.
> >>
> >> Since preference for mmc3 over mmc2 is due to DDR transfer modes, just
> >> set the drive strength to 40mA, which is needed for DDR.
> >>
> >> This pinmux setting also includes the hardware reset pin for emmc.
> >>
> >> Signed-off-by: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>
> >> ---
> >>  arch/arm/boot/dts/sun6i-a31.dtsi | 10 ++++++++++
> >>  1 file changed, 10 insertions(+)
> >>
> >> diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
> >> index b6ad7850fac6..1867af24ff52 100644
> >> --- a/arch/arm/boot/dts/sun6i-a31.dtsi
> >> +++ b/arch/arm/boot/dts/sun6i-a31.dtsi
> >> @@ -709,6 +709,16 @@
> >>                               allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> >>                       };
> >>
> >> +                     mmc3_8bit_emmc_pins: mmc3@1 {
> >> +                             allwinner,pins = "PC6", "PC7", "PC8", "PC9",
> >> +                                              "PC10", "PC11", "PC12",
> >> +                                              "PC13", "PC14", "PC15",
> >> +                                              "PC24";
> >> +                             allwinner,function = "mmc3";
> >> +                             allwinner,drive = <SUN4I_PINCTRL_40_MA>;
> >> +                             allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> >> +                     };
> >> +
> >
> > Is that reset pin optional?
> >
> > If so, I'd prefer it to be a separate node, like we're doing for the
> > SPI chip selects for example.
> >
> > It allows more reusability between different devices without declaring
> > new nodes.
> 
> All eMMC devices have a reset pin. The MMC standard specifies this as
> one way to reset the card, others being a special reset command, or
> powering the card off. It also notes a state when the card will not
> accept commands, and will require a power cycle or asserting the reset
> pin.
> 
> I assume all designs would route this pin. The FEX files also have this
> pin included by default.

I was more concerned about the case were you'd have a 8bits bus
without an emmc. But I guess that can't happen, since all SD cards are
using a 4 bits width anyway.

I'll apply this patch.

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

WARNING: multiple messages have this Message-ID (diff)
From: maxime.ripard@free-electrons.com (Maxime Ripard)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH RFC 08/15] ARM: dts: sun6i: Add mmc3 pins for 8 bit emmc
Date: Sun, 24 Jan 2016 17:54:47 +0100	[thread overview]
Message-ID: <20160124165447.GA7908@lukather> (raw)
In-Reply-To: <CAGb2v66Ma7QmJpNO=Gv=ojrwL3n_MZm3H5XNKA2fpf_3AbOTBA@mail.gmail.com>

Hi,

On Sat, Jan 23, 2016 at 07:04:54PM +0800, Chen-Yu Tsai wrote:
> Hi,
> 
> On Sat, Jan 23, 2016 at 4:31 AM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
> > Hi,
> >
> > On Thu, Jan 21, 2016 at 01:26:35PM +0800, Chen-Yu Tsai wrote:
> >> mmc2 and mmc3 are available on the same pins, with different mux values.
> >> However, only mmc3 supports 8 bit DDR transfer modes.
> >>
> >> Since preference for mmc3 over mmc2 is due to DDR transfer modes, just
> >> set the drive strength to 40mA, which is needed for DDR.
> >>
> >> This pinmux setting also includes the hardware reset pin for emmc.
> >>
> >> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> >> ---
> >>  arch/arm/boot/dts/sun6i-a31.dtsi | 10 ++++++++++
> >>  1 file changed, 10 insertions(+)
> >>
> >> diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
> >> index b6ad7850fac6..1867af24ff52 100644
> >> --- a/arch/arm/boot/dts/sun6i-a31.dtsi
> >> +++ b/arch/arm/boot/dts/sun6i-a31.dtsi
> >> @@ -709,6 +709,16 @@
> >>                               allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> >>                       };
> >>
> >> +                     mmc3_8bit_emmc_pins: mmc3 at 1 {
> >> +                             allwinner,pins = "PC6", "PC7", "PC8", "PC9",
> >> +                                              "PC10", "PC11", "PC12",
> >> +                                              "PC13", "PC14", "PC15",
> >> +                                              "PC24";
> >> +                             allwinner,function = "mmc3";
> >> +                             allwinner,drive = <SUN4I_PINCTRL_40_MA>;
> >> +                             allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> >> +                     };
> >> +
> >
> > Is that reset pin optional?
> >
> > If so, I'd prefer it to be a separate node, like we're doing for the
> > SPI chip selects for example.
> >
> > It allows more reusability between different devices without declaring
> > new nodes.
> 
> All eMMC devices have a reset pin. The MMC standard specifies this as
> one way to reset the card, others being a special reset command, or
> powering the card off. It also notes a state when the card will not
> accept commands, and will require a power cycle or asserting the reset
> pin.
> 
> I assume all designs would route this pin. The FEX files also have this
> pin included by default.

I was more concerned about the case were you'd have a 8bits bus
without an emmc. But I guess that can't happen, since all SD cards are
using a 4 bits width anyway.

I'll apply this patch.

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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WARNING: multiple messages have this Message-ID (diff)
From: Maxime Ripard <maxime.ripard@free-electrons.com>
To: Chen-Yu Tsai <wens@csie.org>
Cc: Ulf Hansson <ulf.hansson@linaro.org>,
	Hans de Goede <hdegoede@redhat.com>,
	"linux-mmc@vger.kernel.org" <linux-mmc@vger.kernel.org>,
	linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
	linux-kernel <linux-kernel@vger.kernel.org>,
	linux-sunxi <linux-sunxi@googlegroups.com>
Subject: Re: [PATCH RFC 08/15] ARM: dts: sun6i: Add mmc3 pins for 8 bit emmc
Date: Sun, 24 Jan 2016 17:54:47 +0100	[thread overview]
Message-ID: <20160124165447.GA7908@lukather> (raw)
In-Reply-To: <CAGb2v66Ma7QmJpNO=Gv=ojrwL3n_MZm3H5XNKA2fpf_3AbOTBA@mail.gmail.com>

[-- Attachment #1: Type: text/plain, Size: 2751 bytes --]

Hi,

On Sat, Jan 23, 2016 at 07:04:54PM +0800, Chen-Yu Tsai wrote:
> Hi,
> 
> On Sat, Jan 23, 2016 at 4:31 AM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
> > Hi,
> >
> > On Thu, Jan 21, 2016 at 01:26:35PM +0800, Chen-Yu Tsai wrote:
> >> mmc2 and mmc3 are available on the same pins, with different mux values.
> >> However, only mmc3 supports 8 bit DDR transfer modes.
> >>
> >> Since preference for mmc3 over mmc2 is due to DDR transfer modes, just
> >> set the drive strength to 40mA, which is needed for DDR.
> >>
> >> This pinmux setting also includes the hardware reset pin for emmc.
> >>
> >> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> >> ---
> >>  arch/arm/boot/dts/sun6i-a31.dtsi | 10 ++++++++++
> >>  1 file changed, 10 insertions(+)
> >>
> >> diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
> >> index b6ad7850fac6..1867af24ff52 100644
> >> --- a/arch/arm/boot/dts/sun6i-a31.dtsi
> >> +++ b/arch/arm/boot/dts/sun6i-a31.dtsi
> >> @@ -709,6 +709,16 @@
> >>                               allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> >>                       };
> >>
> >> +                     mmc3_8bit_emmc_pins: mmc3@1 {
> >> +                             allwinner,pins = "PC6", "PC7", "PC8", "PC9",
> >> +                                              "PC10", "PC11", "PC12",
> >> +                                              "PC13", "PC14", "PC15",
> >> +                                              "PC24";
> >> +                             allwinner,function = "mmc3";
> >> +                             allwinner,drive = <SUN4I_PINCTRL_40_MA>;
> >> +                             allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> >> +                     };
> >> +
> >
> > Is that reset pin optional?
> >
> > If so, I'd prefer it to be a separate node, like we're doing for the
> > SPI chip selects for example.
> >
> > It allows more reusability between different devices without declaring
> > new nodes.
> 
> All eMMC devices have a reset pin. The MMC standard specifies this as
> one way to reset the card, others being a special reset command, or
> powering the card off. It also notes a state when the card will not
> accept commands, and will require a power cycle or asserting the reset
> pin.
> 
> I assume all designs would route this pin. The FEX files also have this
> pin included by default.

I was more concerned about the case were you'd have a 8bits bus
without an emmc. But I guess that can't happen, since all SD cards are
using a 4 bits width anyway.

I'll apply this patch.

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

[-- Attachment #2: Digital signature --]
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  parent reply	other threads:[~2016-01-24 16:54 UTC|newest]

Thread overview: 106+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-01-21  5:26 [PATCH RFC 00/15] mmc: sunxi: Support vqmmc regulator and eMMC DDR modes Chen-Yu Tsai
2016-01-21  5:26 ` Chen-Yu Tsai
2016-01-21  5:26 ` Chen-Yu Tsai
2016-01-21  5:26 ` [PATCH RFC 01/15] mmc: sunxi: Document host init sequence Chen-Yu Tsai
2016-01-21  5:26   ` Chen-Yu Tsai
2016-01-29 11:39   ` Ulf Hansson
2016-01-29 11:39     ` Ulf Hansson
2016-01-21  5:26 ` [PATCH RFC 02/15] mmc: sunxi: Return error on mmc_regulator_set_ocr() fail in .set_ios op Chen-Yu Tsai
2016-01-21  5:26   ` Chen-Yu Tsai
2016-01-29 11:40   ` Ulf Hansson
2016-01-29 11:40     ` Ulf Hansson
2016-01-21  5:26 ` [PATCH RFC 03/15] mmc: sunxi: Block signal voltage switching (CMD11) Chen-Yu Tsai
2016-01-21  5:26   ` Chen-Yu Tsai
     [not found]   ` <1453354002-28366-4-git-send-email-wens-jdAy2FN1RRM@public.gmane.org>
2016-01-29 10:42     ` Ulf Hansson
2016-01-29 10:42       ` Ulf Hansson
2016-01-29 10:42       ` Ulf Hansson
     [not found]       ` <CAPDyKFrG8cXChSRuAx-a++iNHUHU_GuUApDhxfPSJZb1Oo1fsg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2016-01-29 14:44         ` Chen-Yu Tsai
2016-01-29 14:44           ` Chen-Yu Tsai
2016-01-29 14:44           ` Chen-Yu Tsai
2016-01-21  5:26 ` [PATCH RFC 04/15] mmc: sunxi: Support vqmmc regulator Chen-Yu Tsai
2016-01-21  5:26   ` Chen-Yu Tsai
     [not found]   ` <1453354002-28366-5-git-send-email-wens-jdAy2FN1RRM@public.gmane.org>
2016-01-29 11:40     ` Ulf Hansson
2016-01-29 11:40       ` Ulf Hansson
2016-01-29 11:40       ` Ulf Hansson
2016-01-21  5:26 ` [PATCH RFC 05/15] mmc: sunxi: Support MMC_DDR52 timing modes Chen-Yu Tsai
2016-01-21  5:26   ` Chen-Yu Tsai
2016-01-21 11:14   ` Hans de Goede
2016-01-21 11:14     ` Hans de Goede
2016-01-21 11:55     ` Chen-Yu Tsai
2016-01-21 11:55       ` Chen-Yu Tsai
     [not found]       ` <CAGb2v640b6tygtu1TkBEYM6Uf6JqpytzqUQ-Y1uxKf9PUwpQaA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2016-01-21 12:26         ` Hans de Goede
2016-01-21 12:26           ` Hans de Goede
2016-01-21 12:26           ` Hans de Goede
2016-01-21  5:26 ` [PATCH RFC 06/15] mmc: sunxi: Support 8 bit eMMC DDR transfer modes Chen-Yu Tsai
2016-01-21  5:26   ` Chen-Yu Tsai
2016-01-21  5:26 ` [PATCH RFC 07/15] mmc: sunxi: Enable eMMC HS-DDR (MMC_CAP_1_8V_DDR) support Chen-Yu Tsai
2016-01-21  5:26   ` Chen-Yu Tsai
2016-01-21  5:26 ` [PATCH RFC 08/15] ARM: dts: sun6i: Add mmc3 pins for 8 bit emmc Chen-Yu Tsai
2016-01-21  5:26   ` Chen-Yu Tsai
     [not found]   ` <1453354002-28366-9-git-send-email-wens-jdAy2FN1RRM@public.gmane.org>
2016-01-22 20:31     ` Maxime Ripard
2016-01-22 20:31       ` Maxime Ripard
2016-01-22 20:31       ` Maxime Ripard
2016-01-23 11:04       ` Chen-Yu Tsai
2016-01-23 11:04         ` Chen-Yu Tsai
2016-01-23 11:04         ` Chen-Yu Tsai
     [not found]         ` <CAGb2v66Ma7QmJpNO=Gv=ojrwL3n_MZm3H5XNKA2fpf_3AbOTBA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2016-01-24 16:54           ` Maxime Ripard [this message]
2016-01-24 16:54             ` Maxime Ripard
2016-01-24 16:54             ` Maxime Ripard
2016-01-21  5:26 ` [PATCH RFC 09/15] ARM: dts: sun6i: sina31s: Switch to mmc3 for onboard eMMC Chen-Yu Tsai
2016-01-21  5:26   ` Chen-Yu Tsai
     [not found]   ` <1453354002-28366-10-git-send-email-wens-jdAy2FN1RRM@public.gmane.org>
2016-01-21 11:16     ` Hans de Goede
2016-01-21 11:16       ` Hans de Goede
2016-01-21 11:16       ` Hans de Goede
2016-01-21 12:23       ` Chen-Yu Tsai
2016-01-21 12:23         ` Chen-Yu Tsai
2016-01-21 12:25         ` Hans de Goede
2016-01-21 12:25           ` Hans de Goede
2016-01-21 12:28           ` Chen-Yu Tsai
2016-01-21 12:28             ` Chen-Yu Tsai
2016-01-21 12:38             ` Hans de Goede
2016-01-21 12:38               ` Hans de Goede
2016-01-22 20:39     ` Maxime Ripard
2016-01-22 20:39       ` Maxime Ripard
2016-01-22 20:39       ` Maxime Ripard
2016-01-23  4:21       ` Chen-Yu Tsai
2016-01-23  4:21         ` Chen-Yu Tsai
2016-01-23  4:21         ` Chen-Yu Tsai
     [not found]         ` <CAGb2v658auQfvZy8jr__bmuk6=zGicvvE=5Fa5pOnubkgYvjDA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2016-01-24 16:56           ` Maxime Ripard
2016-01-24 16:56             ` Maxime Ripard
2016-01-24 16:56             ` Maxime Ripard
2016-01-21  5:26 ` [PATCH RFC 10/15] ARM: dts: sun8i: Include SDC2_RST pin in mmc2_8bit_pins Chen-Yu Tsai
2016-01-21  5:26   ` Chen-Yu Tsai
     [not found]   ` <1453354002-28366-11-git-send-email-wens-jdAy2FN1RRM@public.gmane.org>
2016-01-24 16:58     ` Maxime Ripard
2016-01-24 16:58       ` Maxime Ripard
2016-01-24 16:58       ` Maxime Ripard
2016-01-21  5:26 ` [PATCH RFC 11/15] ARM: dts: sun8i: sina33: Enable hardware reset and HS-DDR for eMMC Chen-Yu Tsai
2016-01-21  5:26   ` Chen-Yu Tsai
     [not found]   ` <1453354002-28366-12-git-send-email-wens-jdAy2FN1RRM@public.gmane.org>
2016-01-22 20:42     ` Maxime Ripard
2016-01-22 20:42       ` Maxime Ripard
2016-01-22 20:42       ` Maxime Ripard
2016-01-21  5:26 ` [PATCH RFC 12/15] ARM: dts: sun9i: Use sun9i specific mmc compatible Chen-Yu Tsai
2016-01-21  5:26   ` Chen-Yu Tsai
     [not found]   ` <1453354002-28366-13-git-send-email-wens-jdAy2FN1RRM@public.gmane.org>
2016-01-22 20:44     ` Maxime Ripard
2016-01-22 20:44       ` Maxime Ripard
2016-01-22 20:44       ` Maxime Ripard
2016-01-23 10:50       ` Chen-Yu Tsai
2016-01-23 10:50         ` Chen-Yu Tsai
2016-01-23 10:50         ` Chen-Yu Tsai
2016-01-21  5:26 ` [PATCH RFC 13/15] ARM: dts: sun9i: Include SDC2_RST pin in mmc2_8bit_pins Chen-Yu Tsai
2016-01-21  5:26   ` Chen-Yu Tsai
2016-01-21  5:26   ` Chen-Yu Tsai
     [not found]   ` <1453354002-28366-14-git-send-email-wens-jdAy2FN1RRM@public.gmane.org>
2016-01-24 16:58     ` Maxime Ripard
2016-01-24 16:58       ` Maxime Ripard
2016-01-24 16:58       ` Maxime Ripard
2016-01-21  5:26 ` [PATCH RFC 14/15] ARM: dts: sun9i: a80-optimus: Enable hardware reset and HS-DDR for eMMC Chen-Yu Tsai
2016-01-21  5:26   ` Chen-Yu Tsai
2016-01-24 16:59   ` Maxime Ripard
2016-01-24 16:59     ` Maxime Ripard
2016-01-21  5:26 ` [PATCH RFC 15/15] ARM: dts: sun9i: cubieboard4: " Chen-Yu Tsai
2016-01-21  5:26   ` Chen-Yu Tsai
2016-01-21  5:26   ` Chen-Yu Tsai
2016-01-24 16:59   ` Maxime Ripard
2016-01-24 16:59     ` Maxime Ripard
     [not found] ` <1453354002-28366-1-git-send-email-wens-jdAy2FN1RRM@public.gmane.org>
2016-01-21 11:19   ` [PATCH RFC 00/15] mmc: sunxi: Support vqmmc regulator and eMMC DDR modes Hans de Goede
2016-01-21 11:19     ` Hans de Goede
2016-01-21 11:19     ` Hans de Goede

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