From: Thierry Reding <thierry.reding@gmail.com>
To: Rhyland Klein <rklein@nvidia.com>
Cc: Peter De Schrijver <pdeschrijver@nvidia.com>,
Mike Turquette <mturquette@baylibre.com>,
Stephen Warren <swarren@wwwdotorg.org>,
Stephen Boyd <sboyd@codeaurora.org>,
Alexandre Courbot <gnurou@gmail.com>,
linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [Patch V2 6/9] clk: tegra210: fix pllx dyn step calculation
Date: Mon, 25 Jan 2016 13:47:08 +0100 [thread overview]
Message-ID: <20160125124708.GL20452@ulmo.nvidia.com> (raw)
In-Reply-To: <1452799478-14791-7-git-send-email-rklein@nvidia.com>
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On Thu, Jan 14, 2016 at 02:24:35PM -0500, Rhyland Klein wrote:
> The logic for calculating the input rate used when figuring out
> the proper dynamic steps for pllx was incorrect. It is supposed to
> be calculated using parent_rate / m but it was just using the parent
> rate directly, therefore using the wrong step values.
>
> Signed-off-by: Rhyland Klein <rklein@nvidia.com>
> ---
> drivers/clk/tegra/clk-tegra210.c | 10 +++++-----
> 1 file changed, 5 insertions(+), 5 deletions(-)
Applied, thanks.
Thierry
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WARNING: multiple messages have this Message-ID (diff)
From: Thierry Reding <thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
To: Rhyland Klein <rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Cc: Peter De Schrijver
<pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>,
Mike Turquette
<mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>,
Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>,
Stephen Boyd <sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>,
Alexandre Courbot
<gnurou-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Subject: Re: [Patch V2 6/9] clk: tegra210: fix pllx dyn step calculation
Date: Mon, 25 Jan 2016 13:47:08 +0100 [thread overview]
Message-ID: <20160125124708.GL20452@ulmo.nvidia.com> (raw)
In-Reply-To: <1452799478-14791-7-git-send-email-rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
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On Thu, Jan 14, 2016 at 02:24:35PM -0500, Rhyland Klein wrote:
> The logic for calculating the input rate used when figuring out
> the proper dynamic steps for pllx was incorrect. It is supposed to
> be calculated using parent_rate / m but it was just using the parent
> rate directly, therefore using the wrong step values.
>
> Signed-off-by: Rhyland Klein <rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> ---
> drivers/clk/tegra/clk-tegra210.c | 10 +++++-----
> 1 file changed, 5 insertions(+), 5 deletions(-)
Applied, thanks.
Thierry
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next prev parent reply other threads:[~2016-01-25 12:47 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-01-14 19:24 [Patch V2 0/9] Tegra CLK Fixes Rhyland Klein
2016-01-14 19:24 ` [Patch V2 1/9] clk: tegra: Fix divider on VI_I2C Rhyland Klein
2016-01-25 12:30 ` Thierry Reding
2016-01-25 12:30 ` Thierry Reding
2016-01-14 19:24 ` [Patch V2 2/9] clk: tegra210: Remove improper flags for lock_enable Rhyland Klein
2016-01-25 12:34 ` Thierry Reding
2016-01-14 19:24 ` [Patch V2 3/9] clk: tegra210: Fix naming of MISC registers Rhyland Klein
2016-01-25 12:36 ` Thierry Reding
2016-01-14 19:24 ` [Patch V2 4/9] clk: tegra: Fix the misnaming of nvenc from msenc Rhyland Klein
2016-01-25 12:36 ` Thierry Reding
2016-01-14 19:24 ` [Patch V2 5/9] clk: tegra: pll: Fix potential sleeping-while-atomic Rhyland Klein
2016-01-25 12:40 ` Thierry Reding
2016-01-25 12:40 ` Thierry Reding
2016-01-25 12:41 ` Thierry Reding
2016-01-25 12:41 ` Thierry Reding
2016-01-14 19:24 ` [Patch V2 6/9] clk: tegra210: fix pllx dyn step calculation Rhyland Klein
2016-01-25 12:47 ` Thierry Reding [this message]
2016-01-25 12:47 ` Thierry Reding
2016-01-14 19:24 ` [Patch V2 7/9] clk: tegra: pll: Do not disable PLLE when under HW control Rhyland Klein
2016-01-25 12:45 ` Thierry Reding
2016-01-25 12:46 ` Thierry Reding
2016-01-25 12:46 ` Thierry Reding
2016-01-14 19:24 ` [Patch V2 8/9] clk: tegra: pll: Fix typos around clearing plle bits during enable Rhyland Klein
2016-01-25 12:47 ` Thierry Reding
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