diff for duplicates of <20160210204637.GJ30978@codeaurora.org> diff --git a/a/1.txt b/N1/1.txt index 7fdb1d7..c906034 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,5 +1,5 @@ -On 02/10, slemieux.tyco@gmail.com wrote: -> From: Sylvain Lemieux <slemieux@tycoint.com> +On 02/10, slemieux.tyco-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org wrote: +> From: Sylvain Lemieux <slemieux-1xCVI8+nB4ZBDgjK7y7TUQ@public.gmane.org> > > This patch add the support to setup the HCLK PLL output > using the "assigned-clock-rates" parameter in the device tree. @@ -11,7 +11,7 @@ On 02/10, slemieux.tyco@gmail.com wrote: > output setup by the kickstart and/or bootloader; > this version always setup the clock frequency output to 208MHz. > -> Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com> +> Signed-off-by: Sylvain Lemieux <slemieux-1xCVI8+nB4ZBDgjK7y7TUQ@public.gmane.org> > --- I couldn't find any usage of this driver in the tree so I just @@ -21,3 +21,7 @@ branch please let me know. -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project +-- +To unsubscribe from this list: send the line "unsubscribe devicetree" in +the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org +More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/a/content_digest b/N1/content_digest index 9ecbbaf..4da5b35 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,18 +1,19 @@ "ref\01455130352-25860-1-git-send-email-slemieux.tyco@gmail.com\0" - "From\0Stephen Boyd <sboyd@codeaurora.org>\0" + "ref\01455130352-25860-1-git-send-email-slemieux.tyco-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org\0" + "From\0Stephen Boyd <sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>\0" "Subject\0Re: [PATCH v2] clk: lpc32xx: add HCLK PLL output configuration\0" "Date\0Wed, 10 Feb 2016 12:46:37 -0800\0" - "To\0slemieux.tyco@gmail.com\0" - "Cc\0robh+dt@kernel.org" - mturquette@baylibre.com - stigge@antcom.de - vz@mleia.com - devicetree@vger.kernel.org - " linux-clk@vger.kernel.org\0" + "To\0slemieux.tyco-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org\0" + "Cc\0robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org" + mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org + stigge-uj/7R2tJ6VmzQB+pC5nmwQ@public.gmane.org + vz-ChpfBGZJDbMAvxtiuMwx3w@public.gmane.org + devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + " linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\0" "\00:1\0" "b\0" - "On 02/10, slemieux.tyco@gmail.com wrote:\n" - "> From: Sylvain Lemieux <slemieux@tycoint.com>\n" + "On 02/10, slemieux.tyco-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org wrote:\n" + "> From: Sylvain Lemieux <slemieux-1xCVI8+nB4ZBDgjK7y7TUQ@public.gmane.org>\n" "> \n" "> This patch add the support to setup the HCLK PLL output\n" "> using the \"assigned-clock-rates\" parameter in the device tree.\n" @@ -24,7 +25,7 @@ "> output setup by the kickstart and/or bootloader;\n" "> this version always setup the clock frequency output to 208MHz.\n" "> \n" - "> Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>\n" + "> Signed-off-by: Sylvain Lemieux <slemieux-1xCVI8+nB4ZBDgjK7y7TUQ@public.gmane.org>\n" "> ---\n" "\n" "I couldn't find any usage of this driver in the tree so I just\n" @@ -33,6 +34,10 @@ "\n" "-- \n" "Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,\n" - a Linux Foundation Collaborative Project + "a Linux Foundation Collaborative Project\n" + "--\n" + "To unsubscribe from this list: send the line \"unsubscribe devicetree\" in\n" + "the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\n" + More majordomo info at http://vger.kernel.org/majordomo-info.html -533579f678e0f21b757ebd32ef6bd76612ee573ba45b91755aaab07fede6123f +c29201b0602e6afa613403701ed9dc9b47d1ab91be734382cd54a8a8d9a77d9d
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