From: Stephen Boyd <sboyd@codeaurora.org>
To: slemieux.tyco@gmail.com
Cc: robh+dt@kernel.org, mturquette@baylibre.com, stigge@antcom.de,
vz@mleia.com, devicetree@vger.kernel.org,
linux-clk@vger.kernel.org
Subject: Re: [PATCH v2] clk: lpc32xx: add HCLK PLL output configuration
Date: Wed, 10 Feb 2016 12:46:37 -0800 [thread overview]
Message-ID: <20160210204637.GJ30978@codeaurora.org> (raw)
In-Reply-To: <1455130352-25860-1-git-send-email-slemieux.tyco@gmail.com>
On 02/10, slemieux.tyco@gmail.com wrote:
> From: Sylvain Lemieux <slemieux@tycoint.com>
>
> This patch add the support to setup the HCLK PLL output
> using the "assigned-clock-rates" parameter in the device tree.
>
> If the option is not use, the clock setup by the kickstart
> and/or bootloader remain unchanged.
>
> The previous kernel version did not change the clock frequency
> output setup by the kickstart and/or bootloader;
> this version always setup the clock frequency output to 208MHz.
>
> Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
> ---
I couldn't find any usage of this driver in the tree so I just
applied this to clk-next. If it needs to go into some immutable
branch please let me know.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
WARNING: multiple messages have this Message-ID (diff)
From: Stephen Boyd <sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
To: slemieux.tyco-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
Cc: robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org,
mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org,
stigge-uj/7R2tJ6VmzQB+pC5nmwQ@public.gmane.org,
vz-ChpfBGZJDbMAvxtiuMwx3w@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Subject: Re: [PATCH v2] clk: lpc32xx: add HCLK PLL output configuration
Date: Wed, 10 Feb 2016 12:46:37 -0800 [thread overview]
Message-ID: <20160210204637.GJ30978@codeaurora.org> (raw)
In-Reply-To: <1455130352-25860-1-git-send-email-slemieux.tyco-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
On 02/10, slemieux.tyco-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org wrote:
> From: Sylvain Lemieux <slemieux-1xCVI8+nB4ZBDgjK7y7TUQ@public.gmane.org>
>
> This patch add the support to setup the HCLK PLL output
> using the "assigned-clock-rates" parameter in the device tree.
>
> If the option is not use, the clock setup by the kickstart
> and/or bootloader remain unchanged.
>
> The previous kernel version did not change the clock frequency
> output setup by the kickstart and/or bootloader;
> this version always setup the clock frequency output to 208MHz.
>
> Signed-off-by: Sylvain Lemieux <slemieux-1xCVI8+nB4ZBDgjK7y7TUQ@public.gmane.org>
> ---
I couldn't find any usage of this driver in the tree so I just
applied this to clk-next. If it needs to go into some immutable
branch please let me know.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
--
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next prev parent reply other threads:[~2016-02-10 20:46 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-02-10 18:52 [PATCH v2] clk: lpc32xx: add HCLK PLL output configuration slemieux.tyco
2016-02-10 20:46 ` Stephen Boyd [this message]
2016-02-10 20:46 ` Stephen Boyd
2016-03-02 6:19 ` Vladimir Zapolskiy
2016-03-02 14:28 ` Sylvain Lemieux
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