From: jan.glauber@caviumnetworks.com (Jan Glauber)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 4/5] arm64/perf: Enable PMCR long cycle counter bit
Date: Tue, 16 Feb 2016 09:04:24 +0100 [thread overview]
Message-ID: <20160216080424.GB3490@hardcore> (raw)
In-Reply-To: <20160215195529.GW6298@arm.com>
On Mon, Feb 15, 2016 at 07:55:29PM +0000, Will Deacon wrote:
> On Wed, Feb 03, 2016 at 06:11:59PM +0100, Jan Glauber wrote:
> > @@ -768,8 +776,11 @@ static void armv8pmu_reset(void *info)
> > armv8pmu_disable_intens(idx);
> > }
> >
> > - /* Initialize & Reset PMNC: C and P bits. */
> > - armv8pmu_pmcr_write(ARMV8_PMCR_P | ARMV8_PMCR_C);
> > + /*
> > + * Initialize & Reset PMNC. Request overflow on 64 bit but
> > + * cheat in armv8pmu_write_counter().
>
> Can you expand the comment to mention that the 64-bit overflow is only
> for the cycle counter, please?
OK, how about:
/*
* Initialize & Reset PMNC. Request overflow interrupt for
* 64 bit cycle counter but cheat in armv8pmu_write_counter().
*/
Jan
> Will
WARNING: multiple messages have this Message-ID (diff)
From: Jan Glauber <jan.glauber@caviumnetworks.com>
To: Will Deacon <will.deacon@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>,
<linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH v3 4/5] arm64/perf: Enable PMCR long cycle counter bit
Date: Tue, 16 Feb 2016 09:04:24 +0100 [thread overview]
Message-ID: <20160216080424.GB3490@hardcore> (raw)
In-Reply-To: <20160215195529.GW6298@arm.com>
On Mon, Feb 15, 2016 at 07:55:29PM +0000, Will Deacon wrote:
> On Wed, Feb 03, 2016 at 06:11:59PM +0100, Jan Glauber wrote:
> > @@ -768,8 +776,11 @@ static void armv8pmu_reset(void *info)
> > armv8pmu_disable_intens(idx);
> > }
> >
> > - /* Initialize & Reset PMNC: C and P bits. */
> > - armv8pmu_pmcr_write(ARMV8_PMCR_P | ARMV8_PMCR_C);
> > + /*
> > + * Initialize & Reset PMNC. Request overflow on 64 bit but
> > + * cheat in armv8pmu_write_counter().
>
> Can you expand the comment to mention that the 64-bit overflow is only
> for the cycle counter, please?
OK, how about:
/*
* Initialize & Reset PMNC. Request overflow interrupt for
* 64 bit cycle counter but cheat in armv8pmu_write_counter().
*/
Jan
> Will
next prev parent reply other threads:[~2016-02-16 8:04 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-02-03 17:11 [PATCH v3 0/5] Cavium ThunderX PMU support Jan Glauber
2016-02-03 17:11 ` Jan Glauber
2016-02-03 17:11 ` [PATCH v3 1/5] arm64/perf: Rename Cortex A57 events Jan Glauber
2016-02-03 17:11 ` Jan Glauber
2016-02-15 19:40 ` Will Deacon
2016-02-15 19:40 ` Will Deacon
2016-02-15 20:06 ` Will Deacon
2016-02-15 20:06 ` Will Deacon
2016-02-18 9:13 ` Jan Glauber
2016-02-18 9:13 ` Jan Glauber
2016-02-18 11:24 ` Will Deacon
2016-02-18 11:24 ` Will Deacon
2016-02-18 13:45 ` Jan Glauber
2016-02-18 13:45 ` Jan Glauber
2016-02-03 17:11 ` [PATCH v3 2/5] arm64/perf: Add Cavium ThunderX PMU support Jan Glauber
2016-02-03 17:11 ` Jan Glauber
2016-02-03 17:11 ` [PATCH v3 3/5] arm64: dts: Add Cavium ThunderX specific PMU Jan Glauber
2016-02-03 17:11 ` Jan Glauber
2016-02-03 17:11 ` [PATCH v3 4/5] arm64/perf: Enable PMCR long cycle counter bit Jan Glauber
2016-02-03 17:11 ` Jan Glauber
2016-02-15 19:55 ` Will Deacon
2016-02-15 19:55 ` Will Deacon
2016-02-16 8:04 ` Jan Glauber [this message]
2016-02-16 8:04 ` Jan Glauber
2016-02-03 17:12 ` [PATCH v3 5/5] arm64/perf: Extend event mask for ARMv8.1 Jan Glauber
2016-02-03 17:12 ` Jan Glauber
2016-02-15 20:04 ` Will Deacon
2016-02-15 20:04 ` Will Deacon
2016-02-16 8:00 ` Jan Glauber
2016-02-16 8:00 ` Jan Glauber
2016-02-16 15:12 ` Will Deacon
2016-02-16 15:12 ` Will Deacon
2016-02-17 10:47 ` Jan Glauber
2016-02-17 10:47 ` Jan Glauber
2016-02-11 13:28 ` [PATCH v3 0/5] Cavium ThunderX PMU support Jan Glauber
2016-02-11 13:28 ` Jan Glauber
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