From: Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org>
To: Stuart Yoder <stuart.yoder-3arQi8VN3Tc@public.gmane.org>
Cc: Peter Newton <peter.newton-3arQi8VN3Tc@public.gmane.org>,
"iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org"
<iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org>,
Varun Sethi <V.Sethi-3arQi8VN3Tc@public.gmane.org>,
Bharat Bhushan <bharat.bhushan-3arQi8VN3Tc@public.gmane.org>,
"linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org"
<linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>
Subject: Re: RFC: extend IOMMU attributes
Date: Thu, 18 Feb 2016 16:21:45 +0000 [thread overview]
Message-ID: <20160218162145.GB16883@arm.com> (raw)
In-Reply-To: <HE1PR04MB1641F22E38710B68F4ED891F8DAF0-6LN7OEpIatU5tNmRkpaxD89NdZoXdze2vxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
Hi Stuart,
On Thu, Feb 18, 2016 at 04:16:26PM +0000, Stuart Yoder wrote:
> We are implementing support for some specialized NXP SoC network
> devices and have the desire to extend the mapping attributes beyond
> those currently in iommu.h. (I see there is a recent proposal to
> add an IOMMU_MMIO flag)
>
> What we have right now in Linux is a least-common-denominator set of
> attributes, while for the ARM SMMU there is a much richer set of
> attributes that seem useful to support. Specifically, we have one
> SoC device we're dealing with right now that is the target of DMA
> that functionally requires a "cacheable, non-shareable" attribute
> in its SMMU mapping.
>
> In addition, there are many other attributes such as r/w allocate
> hints, transient hints, write-back/write-thru, etc in the SMMU.
>
> We wanted to see what your thinking is with respect to the
> direction the Linux IOMMU layer will head over the longer term with
> respect to attributes.
>
> Is there anything problematic with continuing to grow the
> attributes in iommu.h?...e.g.:
>
> #define IOMMU_READ (1 << 0)
> #define IOMMU_WRITE (1 << 1)
> -#define IOMMU_CACHE (1 << 2) /* DMA cache coherency */
> +#define IOMMU_CACHE_COHERENT (1 << 2) /* cacheable and coherent */
> #define IOMMU_NOEXEC (1 << 3)
> #define IOMMU_MMIO (1 << 4) /* e.g. things like MSI doorbells */
> +#define IOMMU_CACHEABLE (1 << 5) /* cacheable, not coherent */
What does that even mean?
> +#define IOMMU_CACHE_ALLOCATE (1 << 6) /* hint to allocate in the cache */
>
> Also, are we willing to let somewhat architecture specific flags
> onto that list? For, example the ARM 'transient' hint.
If we're going to support fine-grained attribute control, I think it needs
to be done in a page-table specific manner. That is, io-pgtable-arm could
provide those attribute controls which feature in the ARMv8 architecture...
...but that brings me onto my next question: Who on Earth is actually
going to provide these attributes to the IOMMU API?
There seems to be a missing piece.
Will
WARNING: multiple messages have this Message-ID (diff)
From: will.deacon@arm.com (Will Deacon)
To: linux-arm-kernel@lists.infradead.org
Subject: RFC: extend IOMMU attributes
Date: Thu, 18 Feb 2016 16:21:45 +0000 [thread overview]
Message-ID: <20160218162145.GB16883@arm.com> (raw)
In-Reply-To: <HE1PR04MB1641F22E38710B68F4ED891F8DAF0@HE1PR04MB1641.eurprd04.prod.outlook.com>
Hi Stuart,
On Thu, Feb 18, 2016 at 04:16:26PM +0000, Stuart Yoder wrote:
> We are implementing support for some specialized NXP SoC network
> devices and have the desire to extend the mapping attributes beyond
> those currently in iommu.h. (I see there is a recent proposal to
> add an IOMMU_MMIO flag)
>
> What we have right now in Linux is a least-common-denominator set of
> attributes, while for the ARM SMMU there is a much richer set of
> attributes that seem useful to support. Specifically, we have one
> SoC device we're dealing with right now that is the target of DMA
> that functionally requires a "cacheable, non-shareable" attribute
> in its SMMU mapping.
>
> In addition, there are many other attributes such as r/w allocate
> hints, transient hints, write-back/write-thru, etc in the SMMU.
>
> We wanted to see what your thinking is with respect to the
> direction the Linux IOMMU layer will head over the longer term with
> respect to attributes.
>
> Is there anything problematic with continuing to grow the
> attributes in iommu.h?...e.g.:
>
> #define IOMMU_READ (1 << 0)
> #define IOMMU_WRITE (1 << 1)
> -#define IOMMU_CACHE (1 << 2) /* DMA cache coherency */
> +#define IOMMU_CACHE_COHERENT (1 << 2) /* cacheable and coherent */
> #define IOMMU_NOEXEC (1 << 3)
> #define IOMMU_MMIO (1 << 4) /* e.g. things like MSI doorbells */
> +#define IOMMU_CACHEABLE (1 << 5) /* cacheable, not coherent */
What does that even mean?
> +#define IOMMU_CACHE_ALLOCATE (1 << 6) /* hint to allocate in the cache */
>
> Also, are we willing to let somewhat architecture specific flags
> onto that list? For, example the ARM 'transient' hint.
If we're going to support fine-grained attribute control, I think it needs
to be done in a page-table specific manner. That is, io-pgtable-arm could
provide those attribute controls which feature in the ARMv8 architecture...
...but that brings me onto my next question: Who on Earth is actually
going to provide these attributes to the IOMMU API?
There seems to be a missing piece.
Will
next prev parent reply other threads:[~2016-02-18 16:21 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-02-18 16:16 RFC: extend IOMMU attributes Stuart Yoder
2016-02-18 16:16 ` Stuart Yoder
[not found] ` <HE1PR04MB1641F22E38710B68F4ED891F8DAF0-6LN7OEpIatU5tNmRkpaxD89NdZoXdze2vxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2016-02-18 16:21 ` Will Deacon [this message]
2016-02-18 16:21 ` Will Deacon
[not found] ` <20160218162145.GB16883-5wv7dgnIgG8@public.gmane.org>
2016-02-18 19:33 ` Stuart Yoder
2016-02-18 19:33 ` Stuart Yoder
2016-02-25 14:38 ` joro-zLv9SwRftAIdnm+yROfE0A
2016-02-25 14:38 ` joro at 8bytes.org
[not found] ` <20160225143855.GD16675-zLv9SwRftAIdnm+yROfE0A@public.gmane.org>
2016-02-25 15:00 ` Will Deacon
2016-02-25 15:00 ` Will Deacon
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20160218162145.GB16883@arm.com \
--to=will.deacon-5wv7dgnigg8@public.gmane.org \
--cc=V.Sethi-3arQi8VN3Tc@public.gmane.org \
--cc=bharat.bhushan-3arQi8VN3Tc@public.gmane.org \
--cc=iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org \
--cc=linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org \
--cc=peter.newton-3arQi8VN3Tc@public.gmane.org \
--cc=stuart.yoder-3arQi8VN3Tc@public.gmane.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.