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From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: "QEMU Developers" <qemu-devel@nongnu.org>,
	"Alex Bennée" <alex.bennee@linaro.org>,
	"Sergey Fedorov" <serge.fdrv@gmail.com>,
	"Richard Henderson" <rth@twiddle.net>,
	qemu-arm <qemu-arm@nongnu.org>,
	"Edgar Iglesias" <edgar.iglesias@xilinx.com>
Subject: Re: [PATCH v1 8/9] target-arm: A64: Create Instruction Syndromes for Data Aborts
Date: Fri, 19 Feb 2016 14:12:27 +0100	[thread overview]
Message-ID: <20160219131227.GB25623@toto> (raw)
In-Reply-To: <CAFEAcA99-ypB=cMvL8aQwwStbFquv5zUE0xfgKnkwGVaUvdkog@mail.gmail.com>

On Thu, Feb 18, 2016 at 11:42:17AM +0000, Peter Maydell wrote:
> On 18 February 2016 at 09:56, Edgar E. Iglesias
> <edgar.iglesias@gmail.com> wrote:
> > On Tue, Feb 16, 2016 at 07:13:32PM +0000, Peter Maydell wrote:
> >> I think this patch also would be simpler if the encoded info
> >> put in with the TBs was just the syndrome register, rather
> >> than some other encoding.
> >
> > My first try was to only pass the bits needed for the iss
> > (i.e not the full data abort syndrome). We don't have all
> > the info needed at translation time to create the full
> > syndrome (e.g stage2 trap? stage2 trap while stage1 PTW, etc).
> >
> > But we could maybe create as much of the data abort syndrome
> > as possible at translation time and then have the exception
> > handling code add the missing bits. We can then pass the
> > preliminary syndrome from translation time to exception time
> > in the std syndrome format. I can have a look and see what I
> > can do if that makes more sense.
> 
> Yep, that was basically what I had in mind.
> 
> Am I right in thinking that at translate time we capture:
>  IL ISV SAS SSE SRT SF AR
> and then at exception time we determine:
>  EC FnV EA CM S1PTW WnR DFSC
> ?

Yes. It gets a little messy due to the need to the clearing
of ISV (and related fields) and thus setting IL, if the abort
does not target EL2 but it's not too bad.

> 
> In that case I think you could reasonably have the info stored
> with the TBs be "template syndrome >> 14" (since bits [13:0] are
> all info determined at exception-time). The only reason for doing
> this is that the encoded data is stored as sleb128 deltas between
> lines so keeping the values numerically smaller should make them
> take up a bit less space. (I have no idea how significant the
> space saving would be.)
> 
> You should then be able to just have restore_state_to_opc()
> write straight to env->exception.syndrome rather than needing
> a new field in the cpu state.

Sounds good!

Thanks!
Edgar

WARNING: multiple messages have this Message-ID (diff)
From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: "Edgar Iglesias" <edgar.iglesias@xilinx.com>,
	"QEMU Developers" <qemu-devel@nongnu.org>,
	qemu-arm <qemu-arm@nongnu.org>,
	"Sergey Fedorov" <serge.fdrv@gmail.com>,
	"Alex Bennée" <alex.bennee@linaro.org>,
	"Richard Henderson" <rth@twiddle.net>
Subject: Re: [Qemu-devel] [PATCH v1 8/9] target-arm: A64: Create Instruction Syndromes for Data Aborts
Date: Fri, 19 Feb 2016 14:12:27 +0100	[thread overview]
Message-ID: <20160219131227.GB25623@toto> (raw)
In-Reply-To: <CAFEAcA99-ypB=cMvL8aQwwStbFquv5zUE0xfgKnkwGVaUvdkog@mail.gmail.com>

On Thu, Feb 18, 2016 at 11:42:17AM +0000, Peter Maydell wrote:
> On 18 February 2016 at 09:56, Edgar E. Iglesias
> <edgar.iglesias@gmail.com> wrote:
> > On Tue, Feb 16, 2016 at 07:13:32PM +0000, Peter Maydell wrote:
> >> I think this patch also would be simpler if the encoded info
> >> put in with the TBs was just the syndrome register, rather
> >> than some other encoding.
> >
> > My first try was to only pass the bits needed for the iss
> > (i.e not the full data abort syndrome). We don't have all
> > the info needed at translation time to create the full
> > syndrome (e.g stage2 trap? stage2 trap while stage1 PTW, etc).
> >
> > But we could maybe create as much of the data abort syndrome
> > as possible at translation time and then have the exception
> > handling code add the missing bits. We can then pass the
> > preliminary syndrome from translation time to exception time
> > in the std syndrome format. I can have a look and see what I
> > can do if that makes more sense.
> 
> Yep, that was basically what I had in mind.
> 
> Am I right in thinking that at translate time we capture:
>  IL ISV SAS SSE SRT SF AR
> and then at exception time we determine:
>  EC FnV EA CM S1PTW WnR DFSC
> ?

Yes. It gets a little messy due to the need to the clearing
of ISV (and related fields) and thus setting IL, if the abort
does not target EL2 but it's not too bad.

> 
> In that case I think you could reasonably have the info stored
> with the TBs be "template syndrome >> 14" (since bits [13:0] are
> all info determined at exception-time). The only reason for doing
> this is that the encoded data is stored as sleb128 deltas between
> lines so keeping the values numerically smaller should make them
> take up a bit less space. (I have no idea how significant the
> space saving would be.)
> 
> You should then be able to just have restore_state_to_opc()
> write straight to env->exception.syndrome rather than needing
> a new field in the cpu state.

Sounds good!

Thanks!
Edgar

  reply	other threads:[~2016-02-19 13:12 UTC|newest]

Thread overview: 38+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-02-12 14:33 [PATCH v1 0/9] arm: Steps towards EL2 support round 6 Edgar E. Iglesias
2016-02-12 14:33 ` [Qemu-devel] " Edgar E. Iglesias
2016-02-12 14:33 ` [PATCH v1 1/9] tcg: Add tcg_set_insn_param Edgar E. Iglesias
2016-02-12 14:33   ` [Qemu-devel] " Edgar E. Iglesias
2016-02-12 14:33 ` [PATCH v1 2/9] gen-icount: Use tcg_set_insn_param Edgar E. Iglesias
2016-02-12 14:33   ` [Qemu-devel] " Edgar E. Iglesias
2016-02-12 14:33 ` [PATCH v1 3/9] target-arm: Add the thumb/IL flag to syn_data_abort Edgar E. Iglesias
2016-02-12 14:33   ` [Qemu-devel] " Edgar E. Iglesias
2016-02-16 19:04   ` Sergey Fedorov
2016-02-16 19:04     ` [Qemu-devel] " Sergey Fedorov
2016-02-18  9:48     ` Edgar E. Iglesias
2016-02-18  9:48       ` [Qemu-devel] " Edgar E. Iglesias
2016-02-12 14:33 ` [PATCH v1 4/9] target-arm: Add more fields to the data abort syndrome generator Edgar E. Iglesias
2016-02-12 14:33   ` [Qemu-devel] " Edgar E. Iglesias
2016-02-12 14:33 ` [PATCH v1 5/9] target-arm/translate-a64.c: Use extract32 in disas_ldst_reg_imm9 Edgar E. Iglesias
2016-02-12 14:33   ` [Qemu-devel] " Edgar E. Iglesias
2016-02-16 21:09   ` Sergey Fedorov
2016-02-16 21:09     ` [Qemu-devel] " Sergey Fedorov
2016-02-12 14:33 ` [PATCH v1 6/9] target-arm/translate-a64.c: Unify some of the ldst_reg decoding Edgar E. Iglesias
2016-02-12 14:33   ` [Qemu-devel] " Edgar E. Iglesias
2016-02-16 21:11   ` Sergey Fedorov
2016-02-16 21:11     ` [Qemu-devel] " Sergey Fedorov
2016-02-12 14:34 ` [PATCH v1 7/9] target-arm: Add the ARMInsnSyndrome type Edgar E. Iglesias
2016-02-12 14:34   ` [Qemu-devel] " Edgar E. Iglesias
2016-02-16 19:11   ` Peter Maydell
2016-02-16 19:11     ` [Qemu-devel] " Peter Maydell
2016-02-12 14:34 ` [PATCH v1 8/9] target-arm: A64: Create Instruction Syndromes for Data Aborts Edgar E. Iglesias
2016-02-12 14:34   ` [Qemu-devel] " Edgar E. Iglesias
2016-02-16 19:13   ` Peter Maydell
2016-02-16 19:13     ` [Qemu-devel] " Peter Maydell
2016-02-18  9:56     ` Edgar E. Iglesias
2016-02-18  9:56       ` [Qemu-devel] " Edgar E. Iglesias
2016-02-18 11:42       ` Peter Maydell
2016-02-18 11:42         ` [Qemu-devel] " Peter Maydell
2016-02-19 13:12         ` Edgar E. Iglesias [this message]
2016-02-19 13:12           ` Edgar E. Iglesias
2016-02-12 14:34 ` [PATCH v1 9/9] target-arm: Use isyn.swstep.ex to hold the is_ldex state Edgar E. Iglesias
2016-02-12 14:34   ` [Qemu-devel] " Edgar E. Iglesias

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