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From: Thierry Reding <thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
To: Alexandre Courbot <acourbot-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Cc: "Terje Bergström"
	<tbergstrom-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>,
	"Stephen Warren"
	<swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>,
	linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	gnurou-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
Subject: Re: [PATCH v4 1/2] gpu: host1x: Set DMA mask
Date: Wed, 2 Mar 2016 18:08:23 +0100	[thread overview]
Message-ID: <20160302170823.GA486@ulmo.nvidia.com> (raw)
In-Reply-To: <1456477613-24995-1-git-send-email-acourbot-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

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On Fri, Feb 26, 2016 at 06:06:52PM +0900, Alexandre Courbot wrote:
> The default DMA mask covers a 32 bits address range, but host1x devices
> can address a larger range on TK1 and TX1. Set the DMA mask to the range
> addressable when we use the IOMMU to prevent the use of bounce buffers.
> 
> Signed-off-by: Alexandre Courbot <acourbot-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> ---
> Change since v3:
> - Use the IOMMU-addressable range (when IOMMU is available) for each host1x
>   variation. This ensures that we can cover all physical memory while remaining
>   conservative if IOMMU is not used.
> - Set the DMA range on the host1x device itself so all its childs inherit from it
> 
>  drivers/gpu/host1x/dev.c | 7 +++++++
>  drivers/gpu/host1x/dev.h | 1 +
>  2 files changed, 8 insertions(+)

I think this could still be better, but what I have in mind is much more
involved and this does fix the issue with a minimum amount of code, so I
have applied this for now.

Thierry

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WARNING: multiple messages have this Message-ID (diff)
From: Thierry Reding <thierry.reding@gmail.com>
To: Alexandre Courbot <acourbot@nvidia.com>
Cc: "Terje Bergström" <tbergstrom@nvidia.com>,
	"Stephen Warren" <swarren@wwwdotorg.org>,
	linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org,
	gnurou@gmail.com
Subject: Re: [PATCH v4 1/2] gpu: host1x: Set DMA mask
Date: Wed, 2 Mar 2016 18:08:23 +0100	[thread overview]
Message-ID: <20160302170823.GA486@ulmo.nvidia.com> (raw)
In-Reply-To: <1456477613-24995-1-git-send-email-acourbot@nvidia.com>

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On Fri, Feb 26, 2016 at 06:06:52PM +0900, Alexandre Courbot wrote:
> The default DMA mask covers a 32 bits address range, but host1x devices
> can address a larger range on TK1 and TX1. Set the DMA mask to the range
> addressable when we use the IOMMU to prevent the use of bounce buffers.
> 
> Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
> ---
> Change since v3:
> - Use the IOMMU-addressable range (when IOMMU is available) for each host1x
>   variation. This ensures that we can cover all physical memory while remaining
>   conservative if IOMMU is not used.
> - Set the DMA range on the host1x device itself so all its childs inherit from it
> 
>  drivers/gpu/host1x/dev.c | 7 +++++++
>  drivers/gpu/host1x/dev.h | 1 +
>  2 files changed, 8 insertions(+)

I think this could still be better, but what I have in mind is much more
involved and this does fix the issue with a minimum amount of code, so I
have applied this for now.

Thierry

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  parent reply	other threads:[~2016-03-02 17:08 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-02-26  9:06 [PATCH v4 1/2] gpu: host1x: Set DMA mask Alexandre Courbot
2016-02-26  9:06 ` Alexandre Courbot
     [not found] ` <1456477613-24995-1-git-send-email-acourbot-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2016-02-26  9:06   ` [PATCH v4 2/2] gpu: host1x: Set DMA ops on device creation Alexandre Courbot
2016-02-26  9:06     ` Alexandre Courbot
     [not found]     ` <1456477613-24995-2-git-send-email-acourbot-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2016-03-02 17:08       ` Thierry Reding
2016-03-02 17:08         ` Thierry Reding
2016-03-02 17:08   ` Thierry Reding [this message]
2016-03-02 17:08     ` [PATCH v4 1/2] gpu: host1x: Set DMA mask Thierry Reding

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