[PATCH 0/8] Clean up ironlake clock computation code

[PATCH 0/8] Clean up ironlake clock computation code

[Ander Conselvan de Oliveira]

Hi,

This patch series simplifies the ironlake clock computation code a bit
by deleting some unused/unnecessary code and moving things around a
little.

I'm planning to split i9xx_crtc_compute_clock() into more platform
specific hooks, and I'll expect they'll look somewhat similar to the
result of this series for the ironlake one.

Thanks,
Ander

Ander Conselvan de Oliveira (8):
  drm/i915: Remove ironlake reduced clock computation
  drm/i915: Remove checks for clone config with LVDS in ILK+ dpll code
  drm/i915: Merge ironlake_get_refclk() into its only caller
  drm/i915: Fold intel_ironlake_limit() into clock computation function
  drm/i915: Call g4x_find_best_dpll() directly from ILK+ code
  drm/i915: Don't calculate a new clock in ILK+ code if it is already
    set
  drm/i915: Remove PCH type checks from ironlake_crtc_compute_clock()
  drm/i915: Simplify ironlake_crtc_compute_clock() CPU eDP case

 drivers/gpu/drm/i915/intel_display.c | 174 +++++++++++------------------------
 1 file changed, 54 insertions(+), 120 deletions(-)

-- 
2.4.3

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[PATCH 1/8] drm/i915: Remove ironlake reduced clock computation

[Ander Conselvan de Oliveira]

The irolanke reduced clock computation code is not used since commit
c329a4ec595e ("drm/i915: Nuke lvds downclock support"), so clean it up.

Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 38 +++++++++---------------------------
 1 file changed, 9 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index a343223..9fc02d4 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8786,9 +8786,7 @@ static void haswell_set_pipeconf(struct drm_crtc *crtc)
 
 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
 				    struct intel_crtc_state *crtc_state,
-				    intel_clock_t *clock,
-				    bool *has_reduced_clock,
-				    intel_clock_t *reduced_clock)
+				    intel_clock_t *clock)
 {
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -8831,8 +8829,7 @@ static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
 
 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
 				      struct intel_crtc_state *crtc_state,
-				      u32 *fp,
-				      intel_clock_t *reduced_clock, u32 *fp2)
+				      u32 *fp)
 {
 	struct drm_crtc *crtc = &intel_crtc->base;
 	struct drm_device *dev = crtc->dev;
@@ -8879,9 +8876,6 @@ static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
 	if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
 		*fp |= FP_CB_TUNE;
 
-	if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
-		*fp2 |= FP_CB_TUNE;
-
 	dpll = 0;
 
 	if (is_lvds)
@@ -8929,22 +8923,18 @@ static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
 				       struct intel_crtc_state *crtc_state)
 {
 	struct drm_device *dev = crtc->base.dev;
-	intel_clock_t clock, reduced_clock;
-	u32 dpll = 0, fp = 0, fp2 = 0;
-	bool ok, has_reduced_clock = false;
-	bool is_lvds = false;
+	intel_clock_t clock;
+	u32 dpll = 0, fp = 0;
+	bool ok;
 	struct intel_shared_dpll *pll;
 
 	memset(&crtc_state->dpll_hw_state, 0,
 	       sizeof(crtc_state->dpll_hw_state));
 
-	is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
-
 	WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
 	     "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
 
-	ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
-				     &has_reduced_clock, &reduced_clock);
+	ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock);
 	if (!ok && !crtc_state->clock_set) {
 		DRM_ERROR("Couldn't find PLL settings for mode!\n");
 		return -EINVAL;
@@ -8961,19 +8951,12 @@ static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
 	/* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
 	if (crtc_state->has_pch_encoder) {
 		fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
-		if (has_reduced_clock)
-			fp2 = i9xx_dpll_compute_fp(&reduced_clock);
 
-		dpll = ironlake_compute_dpll(crtc, crtc_state,
-					     &fp, &reduced_clock,
-					     has_reduced_clock ? &fp2 : NULL);
+		dpll = ironlake_compute_dpll(crtc, crtc_state, &fp);
 
 		crtc_state->dpll_hw_state.dpll = dpll;
 		crtc_state->dpll_hw_state.fp0 = fp;
-		if (has_reduced_clock)
-			crtc_state->dpll_hw_state.fp1 = fp2;
-		else
-			crtc_state->dpll_hw_state.fp1 = fp;
+		crtc_state->dpll_hw_state.fp1 = fp;
 
 		pll = intel_get_shared_dpll(crtc, crtc_state, NULL);
 		if (pll == NULL) {
@@ -8983,10 +8966,7 @@ static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
 		}
 	}
 
-	if (is_lvds && has_reduced_clock)
-		crtc->lowfreq_avail = true;
-	else
-		crtc->lowfreq_avail = false;
+	crtc->lowfreq_avail = false;
 
 	return 0;
 }
-- 
2.4.3

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[PATCH 2/8] drm/i915: Remove checks for clone config with LVDS in ILK+ dpll code

[Ander Conselvan de Oliveira]

LVDS is not cloneable, so the check is unnecessary. Removing it makes
the surrouding code a bit simpler.

Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 31 ++++---------------------------
 1 file changed, 4 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 9fc02d4..6ea576a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8593,30 +8593,9 @@ static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
 {
 	struct drm_device *dev = crtc_state->base.crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct drm_atomic_state *state = crtc_state->base.state;
-	struct drm_connector *connector;
-	struct drm_connector_state *connector_state;
-	struct intel_encoder *encoder;
-	int num_connectors = 0, i;
-	bool is_lvds = false;
-
-	for_each_connector_in_state(state, connector, connector_state, i) {
-		if (connector_state->crtc != crtc_state->base.crtc)
-			continue;
-
-		encoder = to_intel_encoder(connector_state->best_encoder);
 
-		switch (encoder->type) {
-		case INTEL_OUTPUT_LVDS:
-			is_lvds = true;
-			break;
-		default:
-			break;
-		}
-		num_connectors++;
-	}
-
-	if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
+	if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
+	    intel_panel_use_ssc(dev_priv)) {
 		DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
 			      dev_priv->vbt.lvds_ssc_freq);
 		return dev_priv->vbt.lvds_ssc_freq;
@@ -8839,7 +8818,7 @@ static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
 	struct drm_connector_state *connector_state;
 	struct intel_encoder *encoder;
 	uint32_t dpll;
-	int factor, num_connectors = 0, i;
+	int factor, i;
 	bool is_lvds = false, is_sdvo = false;
 
 	for_each_connector_in_state(state, connector, connector_state, i) {
@@ -8859,8 +8838,6 @@ static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
 		default:
 			break;
 		}
-
-		num_connectors++;
 	}
 
 	/* Enable autotuning of the PLL clock (if permissible) */
@@ -8911,7 +8888,7 @@ static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
 		break;
 	}
 
-	if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
+	if (is_lvds && intel_panel_use_ssc(dev_priv))
 		dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
 	else
 		dpll |= PLL_REF_INPUT_DREFCLK;
-- 
2.4.3

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[PATCH 3/8] drm/i915: Merge ironlake_get_refclk() into its only caller

[Ander Conselvan de Oliveira]

Previous patches made ironlake_get_refclk() and its only caller,
ironlake_compute_clocks(), very simple, so merge them into one
simple function.

Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 24 ++++++++----------------
 1 file changed, 8 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 6ea576a..bad0b55 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8589,21 +8589,6 @@ void intel_init_pch_refclk(struct drm_device *dev)
 		lpt_init_pch_refclk(dev);
 }
 
-static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
-{
-	struct drm_device *dev = crtc_state->base.crtc->dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
-
-	if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
-	    intel_panel_use_ssc(dev_priv)) {
-		DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
-			      dev_priv->vbt.lvds_ssc_freq);
-		return dev_priv->vbt.lvds_ssc_freq;
-	}
-
-	return 120000;
-}
-
 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
 {
 	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
@@ -8773,7 +8758,14 @@ static bool ironlake_compute_clocks(struct drm_crtc *crtc,
 	const intel_limit_t *limit;
 	bool ret;
 
-	refclk = ironlake_get_refclk(crtc_state);
+	if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
+	    intel_panel_use_ssc(dev_priv)) {
+		DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
+			      dev_priv->vbt.lvds_ssc_freq);
+		refclk = dev_priv->vbt.lvds_ssc_freq;
+	} else {
+		refclk = 120000;
+	}
 
 	/*
 	 * Returns a set of divisors for the desired target clock with the given
-- 
2.4.3

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[PATCH 4/8] drm/i915: Fold intel_ironlake_limit() into clock computation function

[Ander Conselvan de Oliveira]

The funcion intel_ironlake_limit() is only called by the crtc compute
clock path. By merging it into ironlake_compute_clocks(), the code gets
clearer, since there's no more if-ladders to follow.

Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 56 +++++++++++++++---------------------
 1 file changed, 23 insertions(+), 33 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index bad0b55..02abeaa 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -566,30 +566,6 @@ static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
 }
 
 static const intel_limit_t *
-intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
-{
-	struct drm_device *dev = crtc_state->base.crtc->dev;
-	const intel_limit_t *limit;
-
-	if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
-		if (intel_is_dual_link_lvds(dev)) {
-			if (refclk == 100000)
-				limit = &intel_limits_ironlake_dual_lvds_100m;
-			else
-				limit = &intel_limits_ironlake_dual_lvds;
-		} else {
-			if (refclk == 100000)
-				limit = &intel_limits_ironlake_single_lvds_100m;
-			else
-				limit = &intel_limits_ironlake_single_lvds;
-		}
-	} else
-		limit = &intel_limits_ironlake_dac;
-
-	return limit;
-}
-
-static const intel_limit_t *
 intel_g4x_limit(struct intel_crtc_state *crtc_state)
 {
 	struct drm_device *dev = crtc_state->base.crtc->dev;
@@ -619,8 +595,8 @@ intel_limit(struct intel_crtc_state *crtc_state, int refclk)
 
 	if (IS_BROXTON(dev))
 		limit = &intel_limits_bxt;
-	else if (HAS_PCH_SPLIT(dev))
-		limit = intel_ironlake_limit(crtc_state, refclk);
+	else if (WARN_ON(HAS_PCH_SPLIT(dev)))
+		limit = NULL;
 	else if (IS_G4X(dev)) {
 		limit = intel_g4x_limit(crtc_state);
 	} else if (IS_PINEVIEW(dev)) {
@@ -8758,13 +8734,28 @@ static bool ironlake_compute_clocks(struct drm_crtc *crtc,
 	const intel_limit_t *limit;
 	bool ret;
 
-	if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
-	    intel_panel_use_ssc(dev_priv)) {
-		DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
-			      dev_priv->vbt.lvds_ssc_freq);
-		refclk = dev_priv->vbt.lvds_ssc_freq;
+	refclk = 120000;
+
+	if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
+		if (intel_panel_use_ssc(dev_priv)) {
+			DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
+				      dev_priv->vbt.lvds_ssc_freq);
+			refclk = dev_priv->vbt.lvds_ssc_freq;
+		}
+
+		if (intel_is_dual_link_lvds(dev)) {
+			if (refclk == 100000)
+				limit = &intel_limits_ironlake_dual_lvds_100m;
+			else
+				limit = &intel_limits_ironlake_dual_lvds;
+		} else {
+			if (refclk == 100000)
+				limit = &intel_limits_ironlake_single_lvds_100m;
+			else
+				limit = &intel_limits_ironlake_single_lvds;
+		}
 	} else {
-		refclk = 120000;
+		limit = &intel_limits_ironlake_dac;
 	}
 
 	/*
@@ -8772,7 +8763,6 @@ static bool ironlake_compute_clocks(struct drm_crtc *crtc,
 	 * refclk, or FALSE.  The returned values represent the clock equation:
 	 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 	 */
-	limit = intel_limit(crtc_state, refclk);
 	ret = dev_priv->display.find_dpll(limit, crtc_state,
 					  crtc_state->port_clock,
 					  refclk, NULL, clock);
-- 
2.4.3

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[PATCH 5/8] drm/i915: Call g4x_find_best_dpll() directly from ILK+ code

[Ander Conselvan de Oliveira]

The call to dev_priv->display.find_dpll() is already in platform
specific code, so avoid the extra detour.

Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 02abeaa..c9d4511 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8763,9 +8763,8 @@ static bool ironlake_compute_clocks(struct drm_crtc *crtc,
 	 * refclk, or FALSE.  The returned values represent the clock equation:
 	 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 	 */
-	ret = dev_priv->display.find_dpll(limit, crtc_state,
-					  crtc_state->port_clock,
-					  refclk, NULL, clock);
+	ret = g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
+				 refclk, NULL, clock);
 	if (!ret)
 		return false;
 
-- 
2.4.3

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Re: [PATCH 5/8] drm/i915: Call g4x_find_best_dpll() directly from ILK+ code

[Ville Syrjälä]

On Fri, Mar 11, 2016 at 04:52:32PM +0200, Ander Conselvan de Oliveira wrote:
> The call to dev_priv->display.find_dpll() is already in platform
> specific code, so avoid the extra detour.
> 
> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/intel_display.c | 5 ++---
>  1 file changed, 2 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 02abeaa..c9d4511 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -8763,9 +8763,8 @@ static bool ironlake_compute_clocks(struct drm_crtc *crtc,
>  	 * refclk, or FALSE.  The returned values represent the clock equation:
>  	 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
>  	 */
> -	ret = dev_priv->display.find_dpll(limit, crtc_state,
> -					  crtc_state->port_clock,
> -					  refclk, NULL, clock);
> +	ret = g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
> +				 refclk, NULL, clock);
>  	if (!ret)
>  		return false;
>  
> -- 
> 2.4.3
> 
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
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[PATCH 6/8] drm/i915: Don't calculate a new clock in ILK+ code if it is already set

[Ander Conselvan de Oliveira]

Remove the clock calculation from ironlake_crtc_compute_clock() when the
encoder compute_config() already set one. The value was just thrown away
in that case.

Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index c9d4511..fb71693 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8883,7 +8883,6 @@ static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
 	struct drm_device *dev = crtc->base.dev;
 	intel_clock_t clock;
 	u32 dpll = 0, fp = 0;
-	bool ok;
 	struct intel_shared_dpll *pll;
 
 	memset(&crtc_state->dpll_hw_state, 0,
@@ -8892,13 +8891,14 @@ static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
 	WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
 	     "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
 
-	ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock);
-	if (!ok && !crtc_state->clock_set) {
-		DRM_ERROR("Couldn't find PLL settings for mode!\n");
-		return -EINVAL;
-	}
-	/* Compat-code for transition, will disappear. */
 	if (!crtc_state->clock_set) {
+		if (!ironlake_compute_clocks(&crtc->base, crtc_state,
+					     &clock)) {
+			DRM_ERROR("Couldn't find PLL settings for mode!\n");
+			return -EINVAL;
+		}
+
+		/* Compat-code for transition, will disappear. */
 		crtc_state->dpll.n = clock.n;
 		crtc_state->dpll.m1 = clock.m1;
 		crtc_state->dpll.m2 = clock.m2;
-- 
2.4.3

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[PATCH 7/8] drm/i915: Remove PCH type checks from ironlake_crtc_compute_clock()

[Ander Conselvan de Oliveira]

The checks were added in commit 5dc5298bb3e5 ("drm/i915: add proper
CPU/PCH checks to crtc_mode_set functions") in a time when there was
doubts on what PCHs would be supported by HSW. There are similar checks
for PCH type in intel_detect_pch() and the function pointers are
initialized based on platform/pch information, so the removed WARN can't
ever be reached.

Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index fb71693..ef5f5ac 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8880,7 +8880,6 @@ static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
 				       struct intel_crtc_state *crtc_state)
 {
-	struct drm_device *dev = crtc->base.dev;
 	intel_clock_t clock;
 	u32 dpll = 0, fp = 0;
 	struct intel_shared_dpll *pll;
@@ -8888,9 +8887,6 @@ static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
 	memset(&crtc_state->dpll_hw_state, 0,
 	       sizeof(crtc_state->dpll_hw_state));
 
-	WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
-	     "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
-
 	if (!crtc_state->clock_set) {
 		if (!ironlake_compute_clocks(&crtc->base, crtc_state,
 					     &clock)) {
-- 
2.4.3

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[PATCH 8/8] drm/i915: Simplify ironlake_crtc_compute_clock() CPU eDP case

[Ander Conselvan de Oliveira]

None of the code in ironlake_crtc_compute_clock() is relevant for CPU
eDP. The CPU eDP PLL is turned on and off in ironlake_edp_pll_{on,off}
from the DP code and that doesn't depend on the crtc_state->dpll values,
so just return early in that case.

Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 32 ++++++++++++++++----------------
 1 file changed, 16 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index ef5f5ac..57dd1fb 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8887,6 +8887,12 @@ static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
 	memset(&crtc_state->dpll_hw_state, 0,
 	       sizeof(crtc_state->dpll_hw_state));
 
+	crtc->lowfreq_avail = false;
+
+	/* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
+	if (!crtc_state->has_pch_encoder)
+		return 0;
+
 	if (!crtc_state->clock_set) {
 		if (!ironlake_compute_clocks(&crtc->base, crtc_state,
 					     &clock)) {
@@ -8902,26 +8908,20 @@ static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
 		crtc_state->dpll.p2 = clock.p2;
 	}
 
-	/* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
-	if (crtc_state->has_pch_encoder) {
-		fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
-
-		dpll = ironlake_compute_dpll(crtc, crtc_state, &fp);
+	fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
+	dpll = ironlake_compute_dpll(crtc, crtc_state, &fp);
 
-		crtc_state->dpll_hw_state.dpll = dpll;
-		crtc_state->dpll_hw_state.fp0 = fp;
-		crtc_state->dpll_hw_state.fp1 = fp;
+	crtc_state->dpll_hw_state.dpll = dpll;
+	crtc_state->dpll_hw_state.fp0 = fp;
+	crtc_state->dpll_hw_state.fp1 = fp;
 
-		pll = intel_get_shared_dpll(crtc, crtc_state, NULL);
-		if (pll == NULL) {
-			DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
-					 pipe_name(crtc->pipe));
-			return -EINVAL;
-		}
+	pll = intel_get_shared_dpll(crtc, crtc_state, NULL);
+	if (pll == NULL) {
+		DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
+				 pipe_name(crtc->pipe));
+		return -EINVAL;
 	}
 
-	crtc->lowfreq_avail = false;
-
 	return 0;
 }
 
-- 
2.4.3

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Re: [PATCH 0/8] Clean up ironlake clock computation code

[Ville Syrjälä]

On Fri, Mar 11, 2016 at 04:52:27PM +0200, Ander Conselvan de Oliveira wrote:
> Hi,
> 
> This patch series simplifies the ironlake clock computation code a bit
> by deleting some unused/unnecessary code and moving things around a
> little.
> 
> I'm planning to split i9xx_crtc_compute_clock() into more platform
> specific hooks, and I'll expect they'll look somewhat similar to the
> result of this series for the ironlake one.

Hmm. This is partially at least going against what I had planned (full
resurrection of downclocking). I actually have a branch [1] which has it
working ;)

[1] git://github.com/vsyrjala/linux.git lvds_downclock

> 
> Thanks,
> Ander
> 
> Ander Conselvan de Oliveira (8):
>   drm/i915: Remove ironlake reduced clock computation
>   drm/i915: Remove checks for clone config with LVDS in ILK+ dpll code
>   drm/i915: Merge ironlake_get_refclk() into its only caller
>   drm/i915: Fold intel_ironlake_limit() into clock computation function
>   drm/i915: Call g4x_find_best_dpll() directly from ILK+ code
>   drm/i915: Don't calculate a new clock in ILK+ code if it is already
>     set
>   drm/i915: Remove PCH type checks from ironlake_crtc_compute_clock()
>   drm/i915: Simplify ironlake_crtc_compute_clock() CPU eDP case
> 
>  drivers/gpu/drm/i915/intel_display.c | 174 +++++++++++------------------------
>  1 file changed, 54 insertions(+), 120 deletions(-)
> 
> -- 
> 2.4.3
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
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✗ Fi.CI.BAT: failure for Clean up ironlake clock computation code

[Patchwork]

== Series Details ==

Series: Clean up ironlake clock computation code
URL   : https://patchwork.freedesktop.org/series/4367/
State : failure

== Summary ==

Series 4367v1 Clean up ironlake clock computation code
http://patchwork.freedesktop.org/api/1.0/series/4367/revisions/1/mbox/

Test core_prop_blob:
        Subgroup basic:
                incomplete -> PASS       (bsw-nuc-2)
Test gem_ctx_param_basic:
        Subgroup invalid-param-get:
                incomplete -> PASS       (bsw-nuc-2)
        Subgroup invalid-size-set:
                incomplete -> PASS       (bsw-nuc-2)
Test gem_exec_basic:
        Subgroup gtt-bsd1:
                incomplete -> SKIP       (bsw-nuc-2)
        Subgroup readonly-bsd:
                incomplete -> PASS       (bsw-nuc-2)
Test gem_flink_basic:
        Subgroup flink-lifetime:
                incomplete -> PASS       (bsw-nuc-2)
Test gem_mmap_gtt:
        Subgroup basic-small-copy-xy:
                incomplete -> PASS       (bsw-nuc-2)
Test gem_ringfill:
        Subgroup basic-default-hang:
                incomplete -> PASS       (bsw-nuc-2)
Test gem_storedw_loop:
        Subgroup basic-bsd1:
                incomplete -> SKIP       (bsw-nuc-2)
Test gem_sync:
        Subgroup basic-blt:
                incomplete -> PASS       (bsw-nuc-2)
Test gem_tiled_blits:
        Subgroup basic:
                incomplete -> PASS       (bsw-nuc-2)
Test kms_addfb_basic:
        Subgroup basic:
                incomplete -> PASS       (bsw-nuc-2)
        Subgroup basic-x-tiled:
                incomplete -> PASS       (bsw-nuc-2)
        Subgroup bo-too-small-due-to-tiling:
                incomplete -> PASS       (bsw-nuc-2)
        Subgroup clobberred-modifier:
                incomplete -> PASS       (bsw-nuc-2)
Test kms_pipe_crc_basic:
        Subgroup bad-pipe:
                incomplete -> PASS       (bsw-nuc-2)
        Subgroup nonblocking-crc-pipe-a:
                incomplete -> SKIP       (bsw-nuc-2)
        Subgroup nonblocking-crc-pipe-a-frame-sequence:
                incomplete -> SKIP       (bsw-nuc-2)
        Subgroup nonblocking-crc-pipe-b:
                incomplete -> SKIP       (bsw-nuc-2)
        Subgroup nonblocking-crc-pipe-c:
                pass       -> DMESG-WARN (hsw-gt2)
        Subgroup read-crc-pipe-b:
                pass       -> DMESG-WARN (hsw-gt2)
        Subgroup suspend-read-crc-pipe-a:
                pass       -> DMESG-WARN (snb-x220t)
        Subgroup suspend-read-crc-pipe-c:
                pass       -> DMESG-WARN (bsw-nuc-2)
Test kms_sink_crc_basic:
                incomplete -> SKIP       (bsw-nuc-2)
Test pm_rpm:
        Subgroup basic-pci-d3-state:
                dmesg-fail -> FAIL       (snb-x220t)
                incomplete -> DMESG-WARN (bsw-nuc-2)
                dmesg-warn -> PASS       (byt-nuc)
Test prime_self_import:
        Subgroup basic-llseek-size:
                incomplete -> PASS       (bsw-nuc-2)

bdw-nuci7        total:194  pass:182  dwarn:0   dfail:0   fail:0   skip:12 
bdw-ultra        total:194  pass:173  dwarn:0   dfail:0   fail:0   skip:21 
bsw-nuc-2        total:194  pass:155  dwarn:2   dfail:0   fail:0   skip:37 
byt-nuc          total:194  pass:155  dwarn:4   dfail:0   fail:0   skip:35 
hsw-brixbox      total:194  pass:172  dwarn:0   dfail:0   fail:0   skip:22 
hsw-gt2          total:194  pass:175  dwarn:2   dfail:0   fail:0   skip:17 
ivb-t430s        total:194  pass:169  dwarn:0   dfail:0   fail:0   skip:25 
skl-i5k-2        total:194  pass:171  dwarn:0   dfail:0   fail:0   skip:23 
skl-i7k-2        total:194  pass:171  dwarn:0   dfail:0   fail:0   skip:23 
skl-nuci5        total:194  pass:183  dwarn:0   dfail:0   fail:0   skip:11 
snb-dellxps      total:194  pass:159  dwarn:1   dfail:0   fail:0   skip:34 
snb-x220t        total:194  pass:159  dwarn:1   dfail:0   fail:1   skip:33 

Results at /archive/results/CI_IGT_test/Patchwork_1581/

571147d0be8b04cbbe99db761e82ef105c6f82ad drm-intel-nightly: 2016y-03m-11d-13h-31m-03s UTC integration manifest
c4630e3159e015b381e023c822bc80f71954244c drm/i915: Simplify ironlake_crtc_compute_clock() CPU eDP case
e9799618be36d98af3a388230fcc10ca73af31a9 drm/i915: Remove PCH type checks from ironlake_crtc_compute_clock()
4d5123738be17df0955af4a168742e9a41ef2d43 drm/i915: Don't calculate a new clock in ILK+ code if it is already set
70912f1d69fa4121e9469ce3c006676fd7a57077 drm/i915: Call g4x_find_best_dpll() directly from ILK+ code
4668d26a496dc3cb88d407921d70ea2bdbfec5f1 drm/i915: Fold intel_ironlake_limit() into clock computation function
0a7bff54c66ef40843ce5dca29e754361b2edd0a drm/i915: Merge ironlake_get_refclk() into its only caller
9c4099a6fc9452562c93ce0869d400dda998db88 drm/i915: Remove checks for clone config with LVDS in ILK+ dpll code
fb24937ba548b14531a829448b9ed3d6204faf48 drm/i915: Remove ironlake reduced clock computation

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