diff for duplicates of <20160314160551.GA21898@ulmo.nvidia.com> diff --git a/a/1.txt b/N1/1.txt index 8ac2826..395bad7 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,11 +1,11 @@ On Thu, Mar 10, 2016 at 02:38:05PM -0500, Rhyland Klein wrote: -> From: Bill Huang <bilhuang@nvidia.com> +> From: Bill Huang <bilhuang-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> > > Add some SLCG (Second Level Clock Gating) override clocks to control > gating and un-gating their logics. > -> Signed-off-by: Bill Huang <bilhuang@nvidia.com> -> Signed-off-by: Rhyland Klein <rklein@nvidia.com> +> Signed-off-by: Bill Huang <bilhuang-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> +> Signed-off-by: Rhyland Klein <rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> > --- > drivers/clk/tegra/clk-id.h | 16 ++++++ > drivers/clk/tegra/clk-tegra210.c | 91 ++++++++++++++++++++++++++++++++ diff --git a/a/content_digest b/N1/content_digest index aaa00b1..8169850 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,28 +1,29 @@ "ref\01457638685-31007-1-git-send-email-rklein@nvidia.com\0" - "From\0Thierry Reding <thierry.reding@gmail.com>\0" + "ref\01457638685-31007-1-git-send-email-rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org\0" + "From\0Thierry Reding <thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>\0" "Subject\0Re: [PATCH] clk: tegra210: Add SLCG override gate clocks\0" "Date\0Mon, 14 Mar 2016 17:05:51 +0100\0" - "To\0Rhyland Klein <rklein@nvidia.com>\0" - "Cc\0Peter De Schrijver <pdeschrijver@nvidia.com>" - Prashant Gaikwad <pgaikwad@nvidia.com> - Michael Turquette <mturquette@baylibre.com> - Stephen Boyd <sboyd@codeaurora.org> - Stephen Warren <swarren@wwwdotorg.org> - Alexandre Courbot <gnurou@gmail.com> - Jon Hunter <jonathanh@nvidia.com> - linux-clk@vger.kernel.org - linux-tegra@vger.kernel.org - " Bill Huang <bilhuang@nvidia.com>\0" + "To\0Rhyland Klein <rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>\0" + "Cc\0Peter De Schrijver <pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>" + Prashant Gaikwad <pgaikwad-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> + Michael Turquette <mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org> + Stephen Boyd <sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> + Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> + Alexandre Courbot <gnurou-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> + Jon Hunter <jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> + linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + " Bill Huang <bilhuang-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>\0" "\01:1\0" "b\0" "On Thu, Mar 10, 2016 at 02:38:05PM -0500, Rhyland Klein wrote:\n" - "> From: Bill Huang <bilhuang@nvidia.com>\n" + "> From: Bill Huang <bilhuang-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>\n" "> \n" "> Add some SLCG (Second Level Clock Gating) override clocks to control\n" "> gating and un-gating their logics.\n" "> \n" - "> Signed-off-by: Bill Huang <bilhuang@nvidia.com>\n" - "> Signed-off-by: Rhyland Klein <rklein@nvidia.com>\n" + "> Signed-off-by: Bill Huang <bilhuang-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>\n" + "> Signed-off-by: Rhyland Klein <rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>\n" "> ---\n" "> drivers/clk/tegra/clk-id.h | 16 ++++++\n" "> drivers/clk/tegra/clk-tegra210.c | 91 ++++++++++++++++++++++++++++++++\n" @@ -55,4 +56,4 @@ "=ztSB\n" "-----END PGP SIGNATURE-----\n" -7676d0f5ae1cebb8445a1b4e69034c5a72a32cbcd2310304e45c04b0f6773dbd +aabd8e54b2fe17582b0e828a3fe3da41080ffb5bf9d30c5bcf5c5c8133b21e63
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