From: David Gibson <david@gibson.dropbear.id.au>
To: Thomas Huth <thuth@redhat.com>
Cc: "Cédric Le Goater" <clg@fr.ibm.com>,
qemu-ppc@nongnu.org, qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH 03/17] ppc: Add a bunch of hypervisor SPRs to Book3s
Date: Wed, 16 Mar 2016 12:04:17 +1100 [thread overview]
Message-ID: <20160316010416.GP9032@voom> (raw)
In-Reply-To: <56E7E8BB.5020205@redhat.com>
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On Tue, Mar 15, 2016 at 11:49:31AM +0100, Thomas Huth wrote:
> On 15.03.2016 10:43, David Gibson wrote:
> >
> > On Mon, Mar 14, 2016 at 08:14:59PM +0100, Thomas Huth wrote:
> >> On 14.03.2016 17:56, Cédric Le Goater wrote:
> >>> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> >>>
> >>> We don't give them a KVM reg number to most of the registers yet as no
> >>> current KVM version supports HV mode. For DAWR and DAWRX, the KVM reg
> >>> number is needed since this register can be set by the guest via the
> >>> H_SET_MODE hypercall.
> >>>
> >>> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> >>> [clg: squashed in patch 'ppc: Add KVM numbers to some P8 SPRs' and
> >>> changed the commit log with a proposal of Thomas Huth ]
> >>> Signed-off-by: Cédric Le Goater <clg@fr.ibm.com>
> >>> ---
> >>> target-ppc/translate_init.c | 140 +++++++++++++++++++++++++++++++++++++++++++-
> >>> 1 file changed, 137 insertions(+), 3 deletions(-)
> >>>
> >>> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> >>> index 6a11b41206e5..43c6e524a6bc 100644
> >>> --- a/target-ppc/translate_init.c
> >>> +++ b/target-ppc/translate_init.c
> >>> @@ -1105,6 +1105,11 @@ static void gen_spr_amr (CPUPPCState *env)
> >>> SPR_NOACCESS, SPR_NOACCESS,
> >>> &spr_read_generic, &spr_write_generic,
> >>> KVM_REG_PPC_UAMOR, 0);
> >>> + spr_register_hv(env, SPR_AMOR, "AMOR",
> >>> + SPR_NOACCESS, SPR_NOACCESS,
> >>> + SPR_NOACCESS, SPR_NOACCESS,
> >>> + &spr_read_generic, &spr_write_generic,
> >>> + 0);
> >>> #endif /* !CONFIG_USER_ONLY */
> >>> }
> >>> #endif /* TARGET_PPC64 */
> >>> @@ -7491,6 +7496,20 @@ static void gen_spr_book3s_dbg(CPUPPCState *env)
> >>> KVM_REG_PPC_DABRX, 0x00000000);
> >>> }
> >>>
> >>> +static void gen_spr_book3s_207_dbg(CPUPPCState *env)
> >>> +{
> >>> + spr_register_kvm_hv(env, SPR_DAWR, "DAWR",
> >>> + SPR_NOACCESS, SPR_NOACCESS,
> >>> + SPR_NOACCESS, SPR_NOACCESS,
> >>> + &spr_read_generic, &spr_write_generic,
> >>> + KVM_REG_PPC_DAWR, 0x00000000);
> >>> + spr_register_kvm_hv(env, SPR_DAWRX, "DAWRX",
> >>> + SPR_NOACCESS, SPR_NOACCESS,
> >>> + SPR_NOACCESS, SPR_NOACCESS,
> >>> + &spr_read_generic, &spr_write_generic,
> >>> + KVM_REG_PPC_DAWRX, 0x00000000);
> >>> +}
> >>> +
> >>> static void gen_spr_970_dbg(CPUPPCState *env)
> >>> {
> >>> /* Breakpoints */
> >>> @@ -7683,15 +7702,116 @@ static void gen_spr_power5p_lpar(CPUPPCState *env)
> >>> spr_register_kvm(env, SPR_LPCR, "LPCR",
> >>> SPR_NOACCESS, SPR_NOACCESS,
> >>> &spr_read_generic, &spr_write_generic,
> >>> - KVM_REG_PPC_LPCR, 0x00000000);
> >>> + KVM_REG_PPC_LPCR, LPCR_LPES0 | LPCR_LPES1);
> >>
> >> Could we please postpone that hunk to a later, separate patch (after
> >> QEMU 2.6 has been released)? It looks like it could maybe cause some
> >> trouble with some emulated boards (e.g. there is some code in
> >> target-ppc/excp_helper.c for example - which is currently disabled, but
> >> I'm not sure whether there are other spots like this somewhere else).
> >
> > I think this whole patch needs to wait until after 2.6, I'm not seeing
> > a good rationale for squeezing it into 2.6 at this stage.
>
> Well, this patch registers DAWR and DAWRX registers with KVM - so
> without this patch, the hardware breakpoints will be lost during
> migration. I haven't tested it, but I think that when somebody uses
> hardware breakpoints in gdb in a KVM guest, and migrates it, then the
> breakpoints won't be triggered anymore after migration without this patch.
Ah.. good point. So the question becomes, which is lower risk:
adjusting the patches to just add DAWR without the HV SPR stuff, or
just incorporating the HV SPR stuff as is.
> Cédric, maybe you could send a patch that adds at least the DAWR and
> DAWRX registers if David does not want to have the full patch for 2.6?
>
> Thomas
>
>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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next prev parent reply other threads:[~2016-03-16 1:18 UTC|newest]
Thread overview: 69+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-03-14 16:56 [Qemu-devel] [PATCH 00/17] ppc: preparing pnv landing Cédric Le Goater
2016-03-14 16:56 ` [Qemu-devel] [PATCH 01/17] ppc: Update SPR definitions Cédric Le Goater
2016-03-14 18:34 ` Thomas Huth
2016-03-14 16:56 ` [Qemu-devel] [PATCH 02/17] ppc: Add macros to register hypervisor mode SPRs Cédric Le Goater
2016-03-14 18:50 ` Thomas Huth
2016-03-14 16:56 ` [Qemu-devel] [PATCH 03/17] ppc: Add a bunch of hypervisor SPRs to Book3s Cédric Le Goater
2016-03-14 19:14 ` Thomas Huth
2016-03-15 9:43 ` David Gibson
2016-03-15 10:49 ` Thomas Huth
2016-03-15 17:04 ` [Qemu-devel] [Qemu-ppc] " Cédric Le Goater
2016-03-16 1:04 ` David Gibson [this message]
2016-03-14 16:56 ` [Qemu-devel] [PATCH 04/17] ppc: Add number of threads per core to the processor definition Cédric Le Goater
2016-03-14 19:20 ` Thomas Huth
2016-03-15 8:06 ` Cédric Le Goater
2016-03-15 8:21 ` Bharata B Rao
2016-03-15 9:45 ` David Gibson
2016-03-15 21:11 ` Benjamin Herrenschmidt
2016-03-16 0:41 ` David Gibson
2016-03-14 16:56 ` [Qemu-devel] [PATCH 05/17] ppc: Fix hreg_store_msr() so that non-HV mode cannot alter MSR:HV Cédric Le Goater
2016-03-14 19:29 ` Thomas Huth
2016-03-15 9:47 ` David Gibson
2016-03-14 16:56 ` [Qemu-devel] [PATCH 06/17] ppc: Create cpu_ppc_set_papr() helper Cédric Le Goater
2016-03-17 2:34 ` David Gibson
2016-03-17 12:33 ` Cédric Le Goater
2016-03-17 22:03 ` David Gibson
2016-03-14 16:56 ` [Qemu-devel] [PATCH 07/17] ppc: Better figure out if processor has HV mode Cédric Le Goater
2016-03-16 1:05 ` David Gibson
2016-03-14 16:56 ` [Qemu-devel] [PATCH 08/17] ppc: Add placeholder SPRs for DPDES and DHDES on P8 Cédric Le Goater
2016-03-14 19:32 ` Thomas Huth
2016-03-16 1:06 ` David Gibson
2016-03-14 16:56 ` [Qemu-devel] [PATCH 09/17] ppc: SPURR & PURR are HV writeable and privileged Cédric Le Goater
2016-03-14 19:37 ` Thomas Huth
2016-03-16 1:07 ` David Gibson
2016-03-16 1:07 ` David Gibson
2016-03-14 16:56 ` [Qemu-devel] [PATCH 10/17] ppc: Add dummy SPR_IC for POWER8 Cédric Le Goater
2016-03-14 19:40 ` Thomas Huth
2016-03-16 1:08 ` David Gibson
2016-03-14 16:56 ` [Qemu-devel] [PATCH 11/17] ppc: Initialize AMOR in PAPR mode Cédric Le Goater
2016-03-14 20:13 ` Thomas Huth
2016-03-16 1:09 ` David Gibson
2016-03-17 2:36 ` David Gibson
2016-03-14 16:56 ` [Qemu-devel] [PATCH 12/17] ppc: Fix writing to AMR/UAMOR Cédric Le Goater
2016-03-14 20:26 ` Thomas Huth
2016-03-15 8:05 ` Cédric Le Goater
2016-03-14 16:56 ` [Qemu-devel] [PATCH 13/17] ppc: Add POWER8 IAMR register Cédric Le Goater
2016-03-14 20:36 ` Thomas Huth
2016-03-14 16:56 ` [Qemu-devel] [PATCH 14/17] ppc: Add dummy write to VTB Cédric Le Goater
2016-03-14 20:54 ` Thomas Huth
2016-03-14 21:07 ` [Qemu-devel] [Qemu-ppc] " Benjamin Herrenschmidt
2016-03-16 1:12 ` [Qemu-devel] " David Gibson
2016-03-14 16:56 ` [Qemu-devel] [PATCH 15/17] ppc: Add dummy POWER8 MPPR register Cédric Le Goater
2016-03-16 1:14 ` David Gibson
2016-03-16 6:17 ` Thomas Huth
2016-03-16 9:24 ` Cédric Le Goater
2016-03-14 16:56 ` [Qemu-devel] [PATCH 16/17] ppc: Add dummy CIABR SPR Cédric Le Goater
2016-03-14 20:00 ` Thomas Huth
2016-03-16 1:14 ` David Gibson
2016-03-16 6:24 ` Thomas Huth
2016-03-16 22:28 ` David Gibson
2016-03-14 16:56 ` [Qemu-devel] [PATCH 17/17] ppc: A couple more dummy POWER8 Book4 regs Cédric Le Goater
2016-03-14 20:08 ` Thomas Huth
2016-03-16 1:15 ` David Gibson
2016-03-15 0:39 ` [Qemu-devel] [PATCH 00/17] ppc: preparing pnv landing David Gibson
2016-03-15 8:11 ` Cédric Le Goater
2016-03-16 1:19 ` David Gibson
2016-03-16 9:08 ` Cédric Le Goater
2016-03-17 2:45 ` David Gibson
2016-03-17 14:28 ` Cédric Le Goater
2016-03-21 0:59 ` David Gibson
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