[Xenomai] ARM LS1021A SMP Floating point Interrupt Service Routine

[Xenomai] ARM LS1021A SMP Floating point Interrupt Service Routine

[Henry Bausley]

How does one properly permit floating point operations in an ISR in a
kernel driver running on an ARM CPU.  Our ISR is on cpu 0 and I thought
that the code below would work.  However sometimes the userspace
application using the floating point unit will get a segmentation fault.
The kernel driver running floating point does not have a problem.  I am
sure I am missing something here since I can use floating point in
xenomai kernel threads without a problem.

int FloatingPointISR()
{
  rthal_vfp_save((union vfp_state*)x, rthal_enable_fpu());

   // A bunch of floating point stuff

  rthal_vfp_load((union vfp_state*)x, 0);
}




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Re: [Xenomai] ARM LS1021A SMP Floating point Interrupt Service Routine

[Gilles Chanteperdrix]

On Tue, Mar 15, 2016 at 08:41:45PM -0700, Henry Bausley wrote:
> How does one properly permit floating point operations in an ISR in a
> kernel driver running on an ARM CPU.  Our ISR is on cpu 0 and I thought
> that the code below would work.  However sometimes the userspace
> application using the floating point unit will get a segmentation fault.
> The kernel driver running floating point does not have a problem.  I am
> sure I am missing something here since I can use floating point in
> xenomai kernel threads without a problem.

That is because Xenomai takes care of handling the FPU context for
kernel threads. On the other hand, for irqs, you are on your own.

> 
> int FloatingPointISR()
> {
>   rthal_vfp_save((union vfp_state*)x, rthal_enable_fpu());
> 
>    // A bunch of floating point stuff
> 
>   rthal_vfp_load((union vfp_state*)x, 0);
> }

I guess the problem is that you do not restore at the end of the
isr, the fpu context as it was at the beginning. You can try:

int FloatingPointISR()
{
	unsigned fpexc = rthal_vfp_fmrx(FPEXC);
	rthal_vfp_save((union vfp_state*)x, rthal_enable_fpu());
 
	// A bunch of floating point stuff
 
	rthal_vfp_load((union vfp_state*)x, 0);
	rthal_vfp_fmxr(FPEXC, fpexc);
}

ALso note that x can not be a thread backup area. It must be an area
specific to your ISR. And cpu, you can not share the area between
two cpus either. And if the ISR is still reentrant, you have to shut
irqs off around this piece of code, in order to avoid a context
switch (for instance by the timer irq) in the middle.

-- 
					    Gilles.
https://click-hack.org