[PATCH 0/8] drm/i915/dsi: improved gpio element support for vlv/chv

[PATCH 0/8] drm/i915/dsi: improved gpio element support for vlv/chv

[Jani Nikula]

This series picks up earlier work by Deepak and Yogesh, and splits it up
to smaller chunks for easier review and merging. This way we can make
progress and get some prep work merged.

BXT isn't included yet.

BR,
Jani.

Deepak M (1):
  drm/i915/dsi: add support for sequence block v3 gpio for VLV

Jani Nikula (6):
  drm/i915/dsi: refer to gpio index instead of gpio to avoid confusion
  drm/i915/dsi: add support for DSI sequence block v2 gpio element
  drm/i915/dsi: do not define VLV gpio pad registers separately
  drm/i915/dsi: abstract VLV gpio element execution to a separate
    function
  drm/i915/dsi: clean up the VLV gpio table and definitions
  drm/i915/chv: add more IOSF port definitions

Yogesh Mohan Marimuthu (1):
  drm/i915/dsi: add support for gpio elements on CHV

 drivers/gpu/drm/i915/i915_reg.h            |   4 +
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 224 ++++++++++++++++++++---------
 2 files changed, 158 insertions(+), 70 deletions(-)

-- 
2.1.4

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[PATCH 1/8] drm/i915/dsi: refer to gpio index instead of gpio to avoid confusion

[Jani Nikula]

The DSI sequence blocks contain gpio index references, not actual gpio
numbers. No functional changes.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index 8302a972d2d4..f687b2e9d8ca 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -198,7 +198,7 @@ static const u8 *mipi_exec_delay(struct intel_dsi *intel_dsi, const u8 *data)
 
 static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
 {
-	u8 gpio, action;
+	u8 gpio_index, action;
 	u16 function, pad;
 	u32 val;
 	struct drm_device *dev = intel_dsi->base.base.dev;
@@ -207,13 +207,13 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
 	if (dev_priv->vbt.dsi.seq_version >= 3)
 		data++;
 
-	gpio = *data++;
+	gpio_index = *data++;
 
 	/* pull up/down */
 	action = *data++ & 1;
 
-	if (gpio >= ARRAY_SIZE(gtable)) {
-		DRM_DEBUG_KMS("unknown gpio %u\n", gpio);
+	if (gpio_index >= ARRAY_SIZE(gtable)) {
+		DRM_DEBUG_KMS("unknown gpio index %u\n", gpio_index);
 		goto out;
 	}
 
@@ -227,16 +227,16 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
 		goto out;
 	}
 
-	function = gtable[gpio].function_reg;
-	pad = gtable[gpio].pad_reg;
+	function = gtable[gpio_index].function_reg;
+	pad = gtable[gpio_index].pad_reg;
 
 	mutex_lock(&dev_priv->sb_lock);
-	if (!gtable[gpio].init) {
+	if (!gtable[gpio_index].init) {
 		/* program the function */
 		/* FIXME: remove constant below */
 		vlv_iosf_sb_write(dev_priv, IOSF_PORT_GPIO_NC, function,
 				  0x2000CC00);
-		gtable[gpio].init = 1;
+		gtable[gpio_index].init = 1;
 	}
 
 	val = 0x4 | action;
-- 
2.1.4

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[PATCH 2/8] drm/i915/dsi: add support for DSI sequence block v2 gpio element

[Jani Nikula]

In sequence block v2, and only in v2, the gpio source (i.e. IOSF port)
is specified separately.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 21 +++++++++++++++++----
 1 file changed, 17 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index f687b2e9d8ca..765dd5cd23ac 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -198,7 +198,7 @@ static const u8 *mipi_exec_delay(struct intel_dsi *intel_dsi, const u8 *data)
 
 static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
 {
-	u8 gpio_index, action;
+	u8 gpio_source, gpio_index, action, port;
 	u16 function, pad;
 	u32 val;
 	struct drm_device *dev = intel_dsi->base.base.dev;
@@ -209,6 +209,9 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
 
 	gpio_index = *data++;
 
+	/* gpio source in sequence v2 only */
+	gpio_source = (*data >> 1) & 3;
+
 	/* pull up/down */
 	action = *data++ & 1;
 
@@ -225,6 +228,17 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
 	if (dev_priv->vbt.dsi.seq_version >= 3) {
 		DRM_DEBUG_KMS("GPIO element v3 not supported\n");
 		goto out;
+	} else if (dev_priv->vbt.dsi.seq_version == 2) {
+		if (gpio_source == 0) {
+			port = IOSF_PORT_GPIO_NC;
+		} else if (gpio_source == 1) {
+			port = IOSF_PORT_GPIO_SC;
+		} else {
+			DRM_DEBUG_KMS("unknown gpio source %u\n", gpio_source);
+			goto out;
+		}
+	} else {
+		port = IOSF_PORT_GPIO_NC;
 	}
 
 	function = gtable[gpio_index].function_reg;
@@ -234,15 +248,14 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
 	if (!gtable[gpio_index].init) {
 		/* program the function */
 		/* FIXME: remove constant below */
-		vlv_iosf_sb_write(dev_priv, IOSF_PORT_GPIO_NC, function,
-				  0x2000CC00);
+		vlv_iosf_sb_write(dev_priv, port, function, 0x2000CC00);
 		gtable[gpio_index].init = 1;
 	}
 
 	val = 0x4 | action;
 
 	/* pull up/down */
-	vlv_iosf_sb_write(dev_priv, IOSF_PORT_GPIO_NC, pad, val);
+	vlv_iosf_sb_write(dev_priv, port, pad, val);
 	mutex_unlock(&dev_priv->sb_lock);
 
 out:
-- 
2.1.4

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[PATCH 3/8] drm/i915/dsi: do not define VLV gpio pad registers separately

[Jani Nikula]

They seem to be all just function register offset + 8. No functional
changes, apart from saving some space.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 41 +++++++++++-------------------
 1 file changed, 15 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index 765dd5cd23ac..5e4d92491de7 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -59,49 +59,38 @@ static inline struct vbt_panel *to_vbt_panel(struct drm_panel *panel)
 #define NS_KHZ_RATIO 1000000
 
 #define GPI0_NC_0_HV_DDI0_HPD           0x4130
-#define GPIO_NC_0_HV_DDI0_PAD           0x4138
 #define GPIO_NC_1_HV_DDI0_DDC_SDA       0x4120
-#define GPIO_NC_1_HV_DDI0_DDC_SDA_PAD   0x4128
 #define GPIO_NC_2_HV_DDI0_DDC_SCL       0x4110
-#define GPIO_NC_2_HV_DDI0_DDC_SCL_PAD   0x4118
 #define GPIO_NC_3_PANEL0_VDDEN          0x4140
-#define GPIO_NC_3_PANEL0_VDDEN_PAD      0x4148
 #define GPIO_NC_4_PANEL0_BLKEN          0x4150
-#define GPIO_NC_4_PANEL0_BLKEN_PAD      0x4158
 #define GPIO_NC_5_PANEL0_BLKCTL         0x4160
-#define GPIO_NC_5_PANEL0_BLKCTL_PAD     0x4168
 #define GPIO_NC_6_PCONF0                0x4180
-#define GPIO_NC_6_PAD                   0x4188
 #define GPIO_NC_7_PCONF0                0x4190
-#define GPIO_NC_7_PAD                   0x4198
 #define GPIO_NC_8_PCONF0                0x4170
-#define GPIO_NC_8_PAD                   0x4178
 #define GPIO_NC_9_PCONF0                0x4100
-#define GPIO_NC_9_PAD                   0x4108
 #define GPIO_NC_10_PCONF0               0x40E0
-#define GPIO_NC_10_PAD                  0x40E8
 #define GPIO_NC_11_PCONF0               0x40F0
-#define GPIO_NC_11_PAD                  0x40F8
+
+#define VLV_FUNCTION_TO_PAD_REG(reg) ((reg) + 8)
 
 struct gpio_table {
 	u16 function_reg;
-	u16 pad_reg;
 	u8 init;
 };
 
 static struct gpio_table gtable[] = {
-	{ GPI0_NC_0_HV_DDI0_HPD, GPIO_NC_0_HV_DDI0_PAD, 0 },
-	{ GPIO_NC_1_HV_DDI0_DDC_SDA, GPIO_NC_1_HV_DDI0_DDC_SDA_PAD, 0 },
-	{ GPIO_NC_2_HV_DDI0_DDC_SCL, GPIO_NC_2_HV_DDI0_DDC_SCL_PAD, 0 },
-	{ GPIO_NC_3_PANEL0_VDDEN, GPIO_NC_3_PANEL0_VDDEN_PAD, 0 },
-	{ GPIO_NC_4_PANEL0_BLKEN, GPIO_NC_4_PANEL0_BLKEN_PAD, 0 },
-	{ GPIO_NC_5_PANEL0_BLKCTL, GPIO_NC_5_PANEL0_BLKCTL_PAD, 0 },
-	{ GPIO_NC_6_PCONF0, GPIO_NC_6_PAD, 0 },
-	{ GPIO_NC_7_PCONF0, GPIO_NC_7_PAD, 0 },
-	{ GPIO_NC_8_PCONF0, GPIO_NC_8_PAD, 0 },
-	{ GPIO_NC_9_PCONF0, GPIO_NC_9_PAD, 0 },
-	{ GPIO_NC_10_PCONF0, GPIO_NC_10_PAD, 0},
-	{ GPIO_NC_11_PCONF0, GPIO_NC_11_PAD, 0}
+	{ GPI0_NC_0_HV_DDI0_HPD, 0 },
+	{ GPIO_NC_1_HV_DDI0_DDC_SDA, 0 },
+	{ GPIO_NC_2_HV_DDI0_DDC_SCL, 0 },
+	{ GPIO_NC_3_PANEL0_VDDEN, 0 },
+	{ GPIO_NC_4_PANEL0_BLKEN, 0 },
+	{ GPIO_NC_5_PANEL0_BLKCTL, 0 },
+	{ GPIO_NC_6_PCONF0, 0 },
+	{ GPIO_NC_7_PCONF0, 0 },
+	{ GPIO_NC_8_PCONF0, 0 },
+	{ GPIO_NC_9_PCONF0, 0 },
+	{ GPIO_NC_10_PCONF0, 0},
+	{ GPIO_NC_11_PCONF0, 0}
 };
 
 static inline enum port intel_dsi_seq_port_to_port(u8 port)
@@ -242,7 +231,7 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
 	}
 
 	function = gtable[gpio_index].function_reg;
-	pad = gtable[gpio_index].pad_reg;
+	pad = VLV_FUNCTION_TO_PAD_REG(function);
 
 	mutex_lock(&dev_priv->sb_lock);
 	if (!gtable[gpio_index].init) {
-- 
2.1.4

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[PATCH 4/8] drm/i915/dsi: abstract VLV gpio element execution to a separate function

[Jani Nikula]

Prepare for future. No functional changes.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 57 ++++++++++++++++--------------
 1 file changed, 31 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index 5e4d92491de7..82047eefd3e1 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -185,38 +185,21 @@ static const u8 *mipi_exec_delay(struct intel_dsi *intel_dsi, const u8 *data)
 	return data;
 }
 
-static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
+static void vlv_exec_gpio(struct drm_i915_private *dev_priv,
+			  u8 gpio_source, u8 gpio_index, u8 action)
 {
-	u8 gpio_source, gpio_index, action, port;
-	u16 function, pad;
 	u32 val;
-	struct drm_device *dev = intel_dsi->base.base.dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
-
-	if (dev_priv->vbt.dsi.seq_version >= 3)
-		data++;
-
-	gpio_index = *data++;
-
-	/* gpio source in sequence v2 only */
-	gpio_source = (*data >> 1) & 3;
-
-	/* pull up/down */
-	action = *data++ & 1;
+	u16 function, pad;
+	u8 port;
 
 	if (gpio_index >= ARRAY_SIZE(gtable)) {
-		DRM_DEBUG_KMS("unknown gpio index %u\n", gpio_index);
-		goto out;
-	}
-
-	if (!IS_VALLEYVIEW(dev_priv)) {
-		DRM_DEBUG_KMS("GPIO element not supported on this platform\n");
-		goto out;
+		DRM_DEBUG_KMS("unknown gpio %u\n", gpio_index);
+		return;
 	}
 
 	if (dev_priv->vbt.dsi.seq_version >= 3) {
 		DRM_DEBUG_KMS("GPIO element v3 not supported\n");
-		goto out;
+		return;
 	} else if (dev_priv->vbt.dsi.seq_version == 2) {
 		if (gpio_source == 0) {
 			port = IOSF_PORT_GPIO_NC;
@@ -224,7 +207,7 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
 			port = IOSF_PORT_GPIO_SC;
 		} else {
 			DRM_DEBUG_KMS("unknown gpio source %u\n", gpio_source);
-			goto out;
+			return;
 		}
 	} else {
 		port = IOSF_PORT_GPIO_NC;
@@ -246,8 +229,30 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
 	/* pull up/down */
 	vlv_iosf_sb_write(dev_priv, port, pad, val);
 	mutex_unlock(&dev_priv->sb_lock);
+}
+
+static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
+{
+	struct drm_device *dev = intel_dsi->base.base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	u8 gpio_source, gpio_index, action;
+
+	if (dev_priv->vbt.dsi.seq_version >= 3)
+		data++;
+
+	gpio_index = *data++;
+
+	/* gpio source in sequence v2 only */
+	gpio_source = (*data >> 1) & 3;
+
+	/* pull up/down */
+	action = *data++ & 1;
+
+	if (IS_VALLEYVIEW(dev_priv))
+		vlv_exec_gpio(dev_priv, gpio_source, gpio_index, action);
+	else
+		DRM_DEBUG_KMS("GPIO element not supported on this platform\n");
 
-out:
 	return data;
 }
 
-- 
2.1.4

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[PATCH 5/8] drm/i915/dsi: clean up the VLV gpio table and definitions

[Jani Nikula]

Add some VLV prefixes, remove redundant initialization, etc. No
functional changes.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 60 +++++++++++++++---------------
 1 file changed, 30 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index 82047eefd3e1..3c6275f85ae2 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -58,39 +58,39 @@ static inline struct vbt_panel *to_vbt_panel(struct drm_panel *panel)
 
 #define NS_KHZ_RATIO 1000000
 
-#define GPI0_NC_0_HV_DDI0_HPD           0x4130
-#define GPIO_NC_1_HV_DDI0_DDC_SDA       0x4120
-#define GPIO_NC_2_HV_DDI0_DDC_SCL       0x4110
-#define GPIO_NC_3_PANEL0_VDDEN          0x4140
-#define GPIO_NC_4_PANEL0_BLKEN          0x4150
-#define GPIO_NC_5_PANEL0_BLKCTL         0x4160
-#define GPIO_NC_6_PCONF0                0x4180
-#define GPIO_NC_7_PCONF0                0x4190
-#define GPIO_NC_8_PCONF0                0x4170
-#define GPIO_NC_9_PCONF0                0x4100
-#define GPIO_NC_10_PCONF0               0x40E0
-#define GPIO_NC_11_PCONF0               0x40F0
+#define VLV_GPIO_NC_0_HV_DDI0_HPD	0x4130
+#define VLV_GPIO_NC_1_HV_DDI0_DDC_SDA	0x4120
+#define VLV_GPIO_NC_2_HV_DDI0_DDC_SCL	0x4110
+#define VLV_GPIO_NC_3_PANEL0_VDDEN	0x4140
+#define VLV_GPIO_NC_4_PANEL0_BLKEN	0x4150
+#define VLV_GPIO_NC_5_PANEL0_BLKCTL	0x4160
+#define VLV_GPIO_NC_6_PCONF0		0x4180
+#define VLV_GPIO_NC_7_PCONF0		0x4190
+#define VLV_GPIO_NC_8_PCONF0		0x4170
+#define VLV_GPIO_NC_9_PCONF0		0x4100
+#define VLV_GPIO_NC_10_PCONF0		0x40E0
+#define VLV_GPIO_NC_11_PCONF0		0x40F0
 
 #define VLV_FUNCTION_TO_PAD_REG(reg) ((reg) + 8)
 
 struct gpio_table {
 	u16 function_reg;
-	u8 init;
+	bool init;
 };
 
-static struct gpio_table gtable[] = {
-	{ GPI0_NC_0_HV_DDI0_HPD, 0 },
-	{ GPIO_NC_1_HV_DDI0_DDC_SDA, 0 },
-	{ GPIO_NC_2_HV_DDI0_DDC_SCL, 0 },
-	{ GPIO_NC_3_PANEL0_VDDEN, 0 },
-	{ GPIO_NC_4_PANEL0_BLKEN, 0 },
-	{ GPIO_NC_5_PANEL0_BLKCTL, 0 },
-	{ GPIO_NC_6_PCONF0, 0 },
-	{ GPIO_NC_7_PCONF0, 0 },
-	{ GPIO_NC_8_PCONF0, 0 },
-	{ GPIO_NC_9_PCONF0, 0 },
-	{ GPIO_NC_10_PCONF0, 0},
-	{ GPIO_NC_11_PCONF0, 0}
+static struct gpio_table vlv_gpio_table[] = {
+	{ VLV_GPIO_NC_0_HV_DDI0_HPD },
+	{ VLV_GPIO_NC_1_HV_DDI0_DDC_SDA },
+	{ VLV_GPIO_NC_2_HV_DDI0_DDC_SCL },
+	{ VLV_GPIO_NC_3_PANEL0_VDDEN },
+	{ VLV_GPIO_NC_4_PANEL0_BLKEN },
+	{ VLV_GPIO_NC_5_PANEL0_BLKCTL },
+	{ VLV_GPIO_NC_6_PCONF0 },
+	{ VLV_GPIO_NC_7_PCONF0 },
+	{ VLV_GPIO_NC_8_PCONF0 },
+	{ VLV_GPIO_NC_9_PCONF0 },
+	{ VLV_GPIO_NC_10_PCONF0 },
+	{ VLV_GPIO_NC_11_PCONF0 },
 };
 
 static inline enum port intel_dsi_seq_port_to_port(u8 port)
@@ -192,7 +192,7 @@ static void vlv_exec_gpio(struct drm_i915_private *dev_priv,
 	u16 function, pad;
 	u8 port;
 
-	if (gpio_index >= ARRAY_SIZE(gtable)) {
+	if (gpio_index >= ARRAY_SIZE(vlv_gpio_table)) {
 		DRM_DEBUG_KMS("unknown gpio %u\n", gpio_index);
 		return;
 	}
@@ -213,15 +213,15 @@ static void vlv_exec_gpio(struct drm_i915_private *dev_priv,
 		port = IOSF_PORT_GPIO_NC;
 	}
 
-	function = gtable[gpio_index].function_reg;
+	function = vlv_gpio_table[gpio_index].function_reg;
 	pad = VLV_FUNCTION_TO_PAD_REG(function);
 
 	mutex_lock(&dev_priv->sb_lock);
-	if (!gtable[gpio_index].init) {
+	if (!vlv_gpio_table[gpio_index].init) {
 		/* program the function */
 		/* FIXME: remove constant below */
 		vlv_iosf_sb_write(dev_priv, port, function, 0x2000CC00);
-		gtable[gpio_index].init = 1;
+		vlv_gpio_table[gpio_index].init = true;
 	}
 
 	val = 0x4 | action;
-- 
2.1.4

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[PATCH 6/8] drm/i915/dsi: add support for sequence block v3 gpio for VLV

[Jani Nikula]

From: Deepak M <m.deepak@intel.com>

Currently all gpio indices we support (via the gpio table) fall in NC
anyway, but prepare for bigger indices.

[Rewritten by Jani, based on earlier work by Deepak.]

Signed-off-by: Deepak M <m.deepak@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 16 ++++++++++++++--
 1 file changed, 14 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index 3c6275f85ae2..040ec5d6a7ac 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -58,6 +58,10 @@ static inline struct vbt_panel *to_vbt_panel(struct drm_panel *panel)
 
 #define NS_KHZ_RATIO 1000000
 
+#define VLV_IOSF_MAX_GPIO_NUM_NC	26
+#define VLV_IOSF_MAX_GPIO_NUM_SC	128
+#define VLV_IOSF_MAX_GPIO_NUM		172
+
 #define VLV_GPIO_NC_0_HV_DDI0_HPD	0x4130
 #define VLV_GPIO_NC_1_HV_DDI0_DDC_SDA	0x4120
 #define VLV_GPIO_NC_2_HV_DDI0_DDC_SCL	0x4110
@@ -198,8 +202,16 @@ static void vlv_exec_gpio(struct drm_i915_private *dev_priv,
 	}
 
 	if (dev_priv->vbt.dsi.seq_version >= 3) {
-		DRM_DEBUG_KMS("GPIO element v3 not supported\n");
-		return;
+		if (gpio_index <= VLV_IOSF_MAX_GPIO_NUM_NC) {
+			port = IOSF_PORT_GPIO_NC;
+		} else if (gpio_index <= VLV_IOSF_MAX_GPIO_NUM_SC) {
+			port = IOSF_PORT_GPIO_SC;
+		} else if (gpio_index <= VLV_IOSF_MAX_GPIO_NUM) {
+			port = IOSF_PORT_GPIO_SUS;
+		} else {
+			DRM_DEBUG_KMS("invalid gpio index %u\n", gpio_index);
+			return;
+		}
 	} else if (dev_priv->vbt.dsi.seq_version == 2) {
 		if (gpio_source == 0) {
 			port = IOSF_PORT_GPIO_NC;
-- 
2.1.4

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[PATCH 7/8] drm/i915/chv: add more IOSF port definitions

[Jani Nikula]

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d4a298f715f4..e58d4342c94e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -621,6 +621,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define   IOSF_PORT_GPIO_SC			0x48
 #define   IOSF_PORT_GPIO_SUS			0xa8
 #define   IOSF_PORT_CCU				0xa9
+#define   CHV_IOSF_PORT_GPIO_N			0x13
+#define   CHV_IOSF_PORT_GPIO_SE			0x48
+#define   CHV_IOSF_PORT_GPIO_E			0xa8
+#define   CHV_IOSF_PORT_GPIO_SW			0xb2
 #define VLV_IOSF_DATA				_MMIO(VLV_DISPLAY_BASE + 0x2104)
 #define VLV_IOSF_ADDR				_MMIO(VLV_DISPLAY_BASE + 0x2108)
 
-- 
2.1.4

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[PATCH 8/8] drm/i915/dsi: add support for gpio elements on CHV

[Jani Nikula]

From: Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com>

Add support for CHV gpio programming in DSI gpio elements.

[Rewritten by Jani, based on earlier work by Yogesh and Deepak.]

Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com>
Signed-off-by: Deepak M <m.deepak@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 65 ++++++++++++++++++++++++++++++
 1 file changed, 65 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index 040ec5d6a7ac..7ea588be3e15 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -77,6 +77,23 @@ static inline struct vbt_panel *to_vbt_panel(struct drm_panel *panel)
 
 #define VLV_FUNCTION_TO_PAD_REG(reg) ((reg) + 8)
 
+#define CHV_MAX_GPIO_NUM_N		72
+#define CHV_MAX_GPIO_NUM_SE		99
+#define CHV_MAX_GPIO_NUM_SW		197
+#define CHV_MIN_GPIO_NUM_SE		73
+#define CHV_MIN_GPIO_NUM_SW		100
+#define CHV_MIN_GPIO_NUM_E		198
+
+#define CHV_PAD_FMLY_BASE		0x4400
+#define CHV_PAD_FMLY_SIZE		0x400
+#define CHV_PAD_CFG_0_1_REG_SIZE	0x8
+#define CHV_PAD_CFG_REG_SIZE		0x4
+#define CHV_VBT_MAX_PINS_PER_FMLY	15
+
+#define CHV_GPIO_CFG_UNLOCK		0x00000000
+#define CHV_GPIO_CFG_HIZ		0x00008100
+#define CHV_GPIO_CFG_TX_STATE_SHIFT	1
+
 struct gpio_table {
 	u16 function_reg;
 	bool init;
@@ -243,6 +260,52 @@ static void vlv_exec_gpio(struct drm_i915_private *dev_priv,
 	mutex_unlock(&dev_priv->sb_lock);
 }
 
+static void chv_exec_gpio(struct drm_i915_private *dev_priv,
+			  u8 gpio_source, u8 gpio_index, u8 action)
+{
+	u16 function, pad;
+	u16 family_num;
+	u8 port;
+
+	if (dev_priv->vbt.dsi.seq_version >= 3) {
+		if (gpio_index <= CHV_MAX_GPIO_NUM_N) {
+			port = CHV_IOSF_PORT_GPIO_N;
+		} else if (gpio_index <= CHV_MAX_GPIO_NUM_SE) {
+			port = CHV_IOSF_PORT_GPIO_SE;
+			gpio_index = gpio_index - CHV_MIN_GPIO_NUM_SE;
+		} else if (gpio_index <= CHV_MAX_GPIO_NUM_SW) {
+			port = CHV_IOSF_PORT_GPIO_SW;
+			gpio_index = gpio_index - CHV_MIN_GPIO_NUM_SW;
+		} else {
+			port = CHV_IOSF_PORT_GPIO_E;
+			gpio_index = gpio_index - CHV_MIN_GPIO_NUM_E;
+		}
+	} else if (dev_priv->vbt.dsi.seq_version == 2) {
+		if (gpio_source == 0) {
+			port = IOSF_PORT_GPIO_NC;
+		} else if (gpio_source == 1) {
+			port = IOSF_PORT_GPIO_SC;
+		} else {
+			DRM_DEBUG_KMS("unknown gpio source %u\n", gpio_source);
+			return;
+		}
+	} else {
+		port = IOSF_PORT_GPIO_NC;
+	}
+
+	family_num = gpio_index / CHV_VBT_MAX_PINS_PER_FMLY;
+	gpio_index = gpio_index - (family_num * CHV_VBT_MAX_PINS_PER_FMLY);
+	pad = CHV_PAD_FMLY_BASE + (family_num * CHV_PAD_FMLY_SIZE) +
+		(((u16)gpio_index) * CHV_PAD_CFG_0_1_REG_SIZE);
+	function = pad + CHV_PAD_CFG_REG_SIZE;
+
+	mutex_lock(&dev_priv->sb_lock);
+	vlv_iosf_sb_write(dev_priv, port, function, CHV_GPIO_CFG_UNLOCK);
+	vlv_iosf_sb_write(dev_priv, port, pad, CHV_GPIO_CFG_HIZ |
+			  (action << CHV_GPIO_CFG_TX_STATE_SHIFT));
+	mutex_unlock(&dev_priv->sb_lock);
+}
+
 static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
 {
 	struct drm_device *dev = intel_dsi->base.base.dev;
@@ -262,6 +325,8 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
 
 	if (IS_VALLEYVIEW(dev_priv))
 		vlv_exec_gpio(dev_priv, gpio_source, gpio_index, action);
+	else if (IS_CHERRYVIEW(dev_priv))
+		chv_exec_gpio(dev_priv, gpio_source, gpio_index, action);
 	else
 		DRM_DEBUG_KMS("GPIO element not supported on this platform\n");
 
-- 
2.1.4

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Re: [PATCH 2/8] drm/i915/dsi: add support for DSI sequence block v2 gpio element

[Ville Syrjälä]

On Thu, Mar 17, 2016 at 05:04:40PM +0200, Jani Nikula wrote:
> In sequence block v2, and only in v2, the gpio source (i.e. IOSF port)
> is specified separately.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 21 +++++++++++++++++----
>  1 file changed, 17 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> index f687b2e9d8ca..765dd5cd23ac 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> @@ -198,7 +198,7 @@ static const u8 *mipi_exec_delay(struct intel_dsi *intel_dsi, const u8 *data)
>  
>  static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
>  {
> -	u8 gpio_index, action;
> +	u8 gpio_source, gpio_index, action, port;
>  	u16 function, pad;
>  	u32 val;
>  	struct drm_device *dev = intel_dsi->base.base.dev;
> @@ -209,6 +209,9 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
>  
>  	gpio_index = *data++;
>  
> +	/* gpio source in sequence v2 only */
> +	gpio_source = (*data >> 1) & 3;
> +

Would it perhaps be cleaner to do the version check here and
just leave gpio_source==0 for v1?

>  	/* pull up/down */
>  	action = *data++ & 1;
>  
> @@ -225,6 +228,17 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
>  	if (dev_priv->vbt.dsi.seq_version >= 3) {
>  		DRM_DEBUG_KMS("GPIO element v3 not supported\n");
>  		goto out;
> +	} else if (dev_priv->vbt.dsi.seq_version == 2) {
> +		if (gpio_source == 0) {
> +			port = IOSF_PORT_GPIO_NC;
> +		} else if (gpio_source == 1) {
> +			port = IOSF_PORT_GPIO_SC;
> +		} else {
> +			DRM_DEBUG_KMS("unknown gpio source %u\n", gpio_source);
> +			goto out;
> +		}
> +	} else {
> +		port = IOSF_PORT_GPIO_NC;
>  	}
>  
>  	function = gtable[gpio_index].function_reg;
> @@ -234,15 +248,14 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
>  	if (!gtable[gpio_index].init) {
>  		/* program the function */
>  		/* FIXME: remove constant below */
> -		vlv_iosf_sb_write(dev_priv, IOSF_PORT_GPIO_NC, function,
> -				  0x2000CC00);
> +		vlv_iosf_sb_write(dev_priv, port, function, 0x2000CC00);
>  		gtable[gpio_index].init = 1;
>  	}
>  
>  	val = 0x4 | action;
>  
>  	/* pull up/down */
> -	vlv_iosf_sb_write(dev_priv, IOSF_PORT_GPIO_NC, pad, val);
> +	vlv_iosf_sb_write(dev_priv, port, pad, val);
>  	mutex_unlock(&dev_priv->sb_lock);
>  
>  out:
> -- 
> 2.1.4

-- 
Ville Syrjälä
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Re: [PATCH 3/8] drm/i915/dsi: do not define VLV gpio pad registers separately

[Ville Syrjälä]

On Thu, Mar 17, 2016 at 05:04:41PM +0200, Jani Nikula wrote:
> They seem to be all just function register offset + 8. No functional
> changes, apart from saving some space.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 41 +++++++++++-------------------
>  1 file changed, 15 insertions(+), 26 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> index 765dd5cd23ac..5e4d92491de7 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> @@ -59,49 +59,38 @@ static inline struct vbt_panel *to_vbt_panel(struct drm_panel *panel)
>  #define NS_KHZ_RATIO 1000000
>  
>  #define GPI0_NC_0_HV_DDI0_HPD           0x4130

The naming is rather inconsistent here. The first register for
each pad should always be called foo_PCONF0,

Alternatively we could leave out the PCONF0 here and think of
these as base offsets for the block of registers for each pad.

> -#define GPIO_NC_0_HV_DDI0_PAD           0x4138
>  #define GPIO_NC_1_HV_DDI0_DDC_SDA       0x4120
> -#define GPIO_NC_1_HV_DDI0_DDC_SDA_PAD   0x4128
>  #define GPIO_NC_2_HV_DDI0_DDC_SCL       0x4110
> -#define GPIO_NC_2_HV_DDI0_DDC_SCL_PAD   0x4118
>  #define GPIO_NC_3_PANEL0_VDDEN          0x4140
> -#define GPIO_NC_3_PANEL0_VDDEN_PAD      0x4148
>  #define GPIO_NC_4_PANEL0_BLKEN          0x4150
> -#define GPIO_NC_4_PANEL0_BLKEN_PAD      0x4158
>  #define GPIO_NC_5_PANEL0_BLKCTL         0x4160
> -#define GPIO_NC_5_PANEL0_BLKCTL_PAD     0x4168
>  #define GPIO_NC_6_PCONF0                0x4180
> -#define GPIO_NC_6_PAD                   0x4188
>  #define GPIO_NC_7_PCONF0                0x4190
> -#define GPIO_NC_7_PAD                   0x4198
>  #define GPIO_NC_8_PCONF0                0x4170
> -#define GPIO_NC_8_PAD                   0x4178
>  #define GPIO_NC_9_PCONF0                0x4100
> -#define GPIO_NC_9_PAD                   0x4108
>  #define GPIO_NC_10_PCONF0               0x40E0
> -#define GPIO_NC_10_PAD                  0x40E8
>  #define GPIO_NC_11_PCONF0               0x40F0
> -#define GPIO_NC_11_PAD                  0x40F8
> +
> +#define VLV_FUNCTION_TO_PAD_REG(reg) ((reg) + 8)

I might do something like this (assuming the "base" approach
I listed before is adopted):
#define VLV_GPIO_PCONF0(base) (base)
#define VLV_GPIO_PAD_VAL(base) ((base) + 8)

those would match the spec better. Especially there's nothing called a
function reg listed in configdb, so calling pconf0 that just creates
unwarranted confusion IMO.

>  
>  struct gpio_table {
>  	u16 function_reg;
> -	u16 pad_reg;
>  	u8 init;
>  };
>  
>  static struct gpio_table gtable[] = {
> -	{ GPI0_NC_0_HV_DDI0_HPD, GPIO_NC_0_HV_DDI0_PAD, 0 },
> -	{ GPIO_NC_1_HV_DDI0_DDC_SDA, GPIO_NC_1_HV_DDI0_DDC_SDA_PAD, 0 },
> -	{ GPIO_NC_2_HV_DDI0_DDC_SCL, GPIO_NC_2_HV_DDI0_DDC_SCL_PAD, 0 },
> -	{ GPIO_NC_3_PANEL0_VDDEN, GPIO_NC_3_PANEL0_VDDEN_PAD, 0 },
> -	{ GPIO_NC_4_PANEL0_BLKEN, GPIO_NC_4_PANEL0_BLKEN_PAD, 0 },
> -	{ GPIO_NC_5_PANEL0_BLKCTL, GPIO_NC_5_PANEL0_BLKCTL_PAD, 0 },
> -	{ GPIO_NC_6_PCONF0, GPIO_NC_6_PAD, 0 },
> -	{ GPIO_NC_7_PCONF0, GPIO_NC_7_PAD, 0 },
> -	{ GPIO_NC_8_PCONF0, GPIO_NC_8_PAD, 0 },
> -	{ GPIO_NC_9_PCONF0, GPIO_NC_9_PAD, 0 },
> -	{ GPIO_NC_10_PCONF0, GPIO_NC_10_PAD, 0},
> -	{ GPIO_NC_11_PCONF0, GPIO_NC_11_PAD, 0}
> +	{ GPI0_NC_0_HV_DDI0_HPD, 0 },
> +	{ GPIO_NC_1_HV_DDI0_DDC_SDA, 0 },
> +	{ GPIO_NC_2_HV_DDI0_DDC_SCL, 0 },
> +	{ GPIO_NC_3_PANEL0_VDDEN, 0 },
> +	{ GPIO_NC_4_PANEL0_BLKEN, 0 },
> +	{ GPIO_NC_5_PANEL0_BLKCTL, 0 },
> +	{ GPIO_NC_6_PCONF0, 0 },
> +	{ GPIO_NC_7_PCONF0, 0 },
> +	{ GPIO_NC_8_PCONF0, 0 },
> +	{ GPIO_NC_9_PCONF0, 0 },
> +	{ GPIO_NC_10_PCONF0, 0},
> +	{ GPIO_NC_11_PCONF0, 0}
>  };
>  
>  static inline enum port intel_dsi_seq_port_to_port(u8 port)
> @@ -242,7 +231,7 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
>  	}
>  
>  	function = gtable[gpio_index].function_reg;
> -	pad = gtable[gpio_index].pad_reg;
> +	pad = VLV_FUNCTION_TO_PAD_REG(function);
>  
>  	mutex_lock(&dev_priv->sb_lock);
>  	if (!gtable[gpio_index].init) {
> -- 
> 2.1.4

-- 
Ville Syrjälä
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✗ Fi.CI.BAT: failure for drm/i915/dsi: improved gpio element support for vlv/chv

[Patchwork]

== Series Details ==

Series: drm/i915/dsi: improved gpio element support for vlv/chv
URL   : https://patchwork.freedesktop.org/series/4578/
State : failure

== Summary ==

Series 4578v1 drm/i915/dsi: improved gpio element support for vlv/chv
http://patchwork.freedesktop.org/api/1.0/series/4578/revisions/1/mbox/

Test gem_ringfill:
        Subgroup basic-default-s3:
                dmesg-warn -> PASS       (skl-nuci5)
Test gem_storedw_loop:
        Subgroup basic-default:
                dmesg-warn -> PASS       (skl-nuci5)
Test gem_sync:
        Subgroup basic-vebox:
                dmesg-warn -> PASS       (skl-nuci5)
Test kms_flip:
        Subgroup basic-flip-vs-wf_vblank:
                pass       -> DMESG-WARN (hsw-gt2)
                pass       -> DMESG-WARN (hsw-brixbox)
        Subgroup basic-plain-flip:
                pass       -> DMESG-WARN (hsw-gt2)
Test kms_frontbuffer_tracking:
        Subgroup basic:
                dmesg-warn -> PASS       (hsw-gt2)
Test kms_pipe_crc_basic:
        Subgroup read-crc-pipe-a-frame-sequence:
                dmesg-warn -> PASS       (hsw-gt2)
        Subgroup suspend-read-crc-pipe-a:
                pass       -> FAIL       (snb-dellxps)
        Subgroup suspend-read-crc-pipe-c:
                dmesg-warn -> PASS       (bsw-nuc-2)
                skip       -> FAIL       (snb-dellxps)
Test pm_rpm:
        Subgroup basic-pci-d3-state:
                pass       -> DMESG-WARN (bsw-nuc-2)
        Subgroup basic-rte:
                dmesg-warn -> PASS       (snb-dellxps)

bdw-ultra        total:194  pass:172  dwarn:1   dfail:0   fail:0   skip:21 
bsw-nuc-2        total:194  pass:155  dwarn:2   dfail:0   fail:0   skip:37 
hsw-brixbox      total:194  pass:170  dwarn:2   dfail:0   fail:0   skip:22 
hsw-gt2          total:194  pass:174  dwarn:3   dfail:0   fail:0   skip:17 
ivb-t430s        total:194  pass:168  dwarn:1   dfail:0   fail:0   skip:25 
skl-i5k-2        total:194  pass:170  dwarn:1   dfail:0   fail:0   skip:23 
skl-i7k-2        total:194  pass:170  dwarn:1   dfail:0   fail:0   skip:23 
skl-nuci5        total:194  pass:182  dwarn:1   dfail:0   fail:0   skip:11 
snb-dellxps      total:160  pass:129  dwarn:1   dfail:0   fail:2   skip:27 

Results at /archive/results/CI_IGT_test/Patchwork_1635/

10e913a48ca36790da9b58bed8729598ea79ebdb drm-intel-nightly: 2016y-03m-17d-13h-22m-41s UTC integration manifest
a117fd2feecb7d5126c2c6ffd2ae09ce31bfce58 drm/i915/dsi: add support for gpio elements on CHV
425dcb32b23619dd0a30ff2c98aad14774896a0b drm/i915/chv: add more IOSF port definitions
8d37a18dd4bd6ee2f04724aaea35a971694f1315 drm/i915/dsi: add support for sequence block v3 gpio for VLV
403f6ab67b17658d93ab8c6b28efe9a9bf6cd376 drm/i915/dsi: clean up the VLV gpio table and definitions
2ad819889304fa566ad330ec459ea9b973e92c3b drm/i915/dsi: abstract VLV gpio element execution to a separate function
e5ee0ebeb04ff73c5e38f2dc47bd1c392fc06ad9 drm/i915/dsi: do not define VLV gpio pad registers separately
e2f83ea1f84d3e22032d57e773e77a2688bcd9f5 drm/i915/dsi: add support for DSI sequence block v2 gpio element
54ab00ef1c616e09763dc138d040769154d0290a drm/i915/dsi: refer to gpio index instead of gpio to avoid confusion

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