[PATCH v5 0/5] ARM: at91: pm: add ULP1 mode support

[PATCH v5 0/5] ARM: at91: pm: add ULP1 mode support

[Wenyou Yang]

The ULP1 (Ultra Low-power mode 1) is introduced by SAMA5D2.

In order to achieve the lowest power consumption, in the ULP1 mode,
all the clocks are shut off, inclusive the embedded 12MHz RC oscillator.

The fast startup signal is used as a wake up source for ULP1 mode.
As soon as the wake up event is asserted, the embedded 12MHz RC
oscillator restarts automatically, which fast startup signal
to trigger the PMC to wake up the system from the ULP1 mode can be
configured via DT.

Changes in v5:
 - to improve the scalability, rework the DT expression part, use
   the child nodes to describe the wake-up input and its active level.
 - due to the DT property expression change, update the binding
   document.
 - due to the DT property expression change, update the fast restart
   node's property.

Changes in v4:
 - add Acked-by tag.
 - add fast_restart node to the DT file.

Changes in v3:
 - use 0 and 1, not string, to define the trigger active polarity.
 - update the property description.

Changes in v2:
 - fix label pm_exit to ulp_exit.
 - shorten the pmc-fast-startup property's name.
 - use the value property, instead of bool property for high
   or low triggered.
 - change the property name and property description.

Wenyou Yang (5):
  ARM: at91: pm: create a separate procedure for the ULP0 mode
  ARM: at91: pm: add ULP1 mode support
  ARM: at91: pm: configure PMC fast startup signals
  Documentation: atmel-pmc: add DT bindings for fast startup
  ARM: at91/dt: sama5d2_xplained: add fast_restart node

 .../devicetree/bindings/arm/atmel-pmc.txt          |   52 +++++++
 arch/arm/boot/dts/at91-sama5d2_xplained.dts        |   19 +++
 arch/arm/mach-at91/pm.c                            |   82 +++++++++-
 arch/arm/mach-at91/pm.h                            |    7 +
 arch/arm/mach-at91/pm_suspend.S                    |  158 +++++++++++++++++---
 include/linux/clk/at91_pmc.h                       |   18 +++
 6 files changed, 311 insertions(+), 25 deletions(-)

-- 
1.7.9.5

[PATCH v5 0/5] ARM: at91: pm: add ULP1 mode support

[Wenyou Yang]

The ULP1 (Ultra Low-power mode 1) is introduced by SAMA5D2.

In order to achieve the lowest power consumption, in the ULP1 mode,
all the clocks are shut off, inclusive the embedded 12MHz RC oscillator.

The fast startup signal is used as a wake up source for ULP1 mode.
As soon as the wake up event is asserted, the embedded 12MHz RC
oscillator restarts automatically, which fast startup signal
to trigger the PMC to wake up the system from the ULP1 mode can be
configured via DT.

Changes in v5:
 - to improve the scalability, rework the DT expression part, use
   the child nodes to describe the wake-up input and its active level.
 - due to the DT property expression change, update the binding
   document.
 - due to the DT property expression change, update the fast restart
   node's property.

Changes in v4:
 - add Acked-by tag.
 - add fast_restart node to the DT file.

Changes in v3:
 - use 0 and 1, not string, to define the trigger active polarity.
 - update the property description.

Changes in v2:
 - fix label pm_exit to ulp_exit.
 - shorten the pmc-fast-startup property's name.
 - use the value property, instead of bool property for high
   or low triggered.
 - change the property name and property description.

Wenyou Yang (5):
  ARM: at91: pm: create a separate procedure for the ULP0 mode
  ARM: at91: pm: add ULP1 mode support
  ARM: at91: pm: configure PMC fast startup signals
  Documentation: atmel-pmc: add DT bindings for fast startup
  ARM: at91/dt: sama5d2_xplained: add fast_restart node

 .../devicetree/bindings/arm/atmel-pmc.txt          |   52 +++++++
 arch/arm/boot/dts/at91-sama5d2_xplained.dts        |   19 +++
 arch/arm/mach-at91/pm.c                            |   82 +++++++++-
 arch/arm/mach-at91/pm.h                            |    7 +
 arch/arm/mach-at91/pm_suspend.S                    |  158 +++++++++++++++++---
 include/linux/clk/at91_pmc.h                       |   18 +++
 6 files changed, 311 insertions(+), 25 deletions(-)

-- 
1.7.9.5

[PATCH v5 0/5] ARM: at91: pm: add ULP1 mode support

[Wenyou Yang]

The ULP1 (Ultra Low-power mode 1) is introduced by SAMA5D2.

In order to achieve the lowest power consumption, in the ULP1 mode,
all the clocks are shut off, inclusive the embedded 12MHz RC oscillator.

The fast startup signal is used as a wake up source for ULP1 mode.
As soon as the wake up event is asserted, the embedded 12MHz RC
oscillator restarts automatically, which fast startup signal
to trigger the PMC to wake up the system from the ULP1 mode can be
configured via DT.

Changes in v5:
 - to improve the scalability, rework the DT expression part, use
   the child nodes to describe the wake-up input and its active level.
 - due to the DT property expression change, update the binding
   document.
 - due to the DT property expression change, update the fast restart
   node's property.

Changes in v4:
 - add Acked-by tag.
 - add fast_restart node to the DT file.

Changes in v3:
 - use 0 and 1, not string, to define the trigger active polarity.
 - update the property description.

Changes in v2:
 - fix label pm_exit to ulp_exit.
 - shorten the pmc-fast-startup property's name.
 - use the value property, instead of bool property for high
   or low triggered.
 - change the property name and property description.

Wenyou Yang (5):
  ARM: at91: pm: create a separate procedure for the ULP0 mode
  ARM: at91: pm: add ULP1 mode support
  ARM: at91: pm: configure PMC fast startup signals
  Documentation: atmel-pmc: add DT bindings for fast startup
  ARM: at91/dt: sama5d2_xplained: add fast_restart node

 .../devicetree/bindings/arm/atmel-pmc.txt          |   52 +++++++
 arch/arm/boot/dts/at91-sama5d2_xplained.dts        |   19 +++
 arch/arm/mach-at91/pm.c                            |   82 +++++++++-
 arch/arm/mach-at91/pm.h                            |    7 +
 arch/arm/mach-at91/pm_suspend.S                    |  158 +++++++++++++++++---
 include/linux/clk/at91_pmc.h                       |   18 +++
 6 files changed, 311 insertions(+), 25 deletions(-)

-- 
1.7.9.5

[PATCH v5 1/5] ARM: at91: pm: create a separate procedure for the ULP0 mode

[Wenyou Yang]

To make the code more legible and prepare to add the ULP1 mode
support in the future, create a separate procedure for the ULP0 mode.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
---

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/arm/mach-at91/pm_suspend.S |   65 ++++++++++++++++++++++++---------------
 1 file changed, 40 insertions(+), 25 deletions(-)

diff --git a/arch/arm/mach-at91/pm_suspend.S b/arch/arm/mach-at91/pm_suspend.S
index a25defd..5fcffdc 100644
--- a/arch/arm/mach-at91/pm_suspend.S
+++ b/arch/arm/mach-at91/pm_suspend.S
@@ -107,7 +107,7 @@ ENTRY(at91_pm_suspend_in_sram)
 
 	ldr	r0, .pm_mode
 	tst	r0, #AT91_PM_SLOW_CLOCK
-	beq	skip_disable_main_clock
+	beq	standby_mode
 
 	ldr	pmc, .pmc_base
 
@@ -131,32 +131,13 @@ ENTRY(at91_pm_suspend_in_sram)
 	orr	tmp1, tmp1, #(1 << 29)		/* bit 29 always set */
 	str	tmp1, [pmc, #AT91_CKGR_PLLAR]
 
-	/* Turn off the main oscillator */
-	ldr	tmp1, [pmc, #AT91_CKGR_MOR]
-	bic	tmp1, tmp1, #AT91_PMC_MOSCEN
-	orr	tmp1, tmp1, #AT91_PMC_KEY
-	str	tmp1, [pmc, #AT91_CKGR_MOR]
-
-skip_disable_main_clock:
-	ldr	pmc, .pmc_base
-
-	/* Wait for interrupt */
-	at91_cpu_idle
-
-	ldr	r0, .pm_mode
-	tst	r0, #AT91_PM_SLOW_CLOCK
-	beq	skip_enable_main_clock
+ulp0_mode:
+	bl	at91_pm_ulp0_mode
+	b	ulp_exit
 
+ulp_exit:
 	ldr	pmc, .pmc_base
 
-	/* Turn on the main oscillator */
-	ldr	tmp1, [pmc, #AT91_CKGR_MOR]
-	orr	tmp1, tmp1, #AT91_PMC_MOSCEN
-	orr	tmp1, tmp1, #AT91_PMC_KEY
-	str	tmp1, [pmc, #AT91_CKGR_MOR]
-
-	wait_moscrdy
-
 	/* Restore PLLA setting */
 	ldr	tmp1, .saved_pllar
 	str	tmp1, [pmc, #AT91_CKGR_PLLAR]
@@ -177,7 +158,15 @@ skip_disable_main_clock:
 
 	wait_mckrdy
 
-skip_enable_main_clock:
+	b	pm_exit
+
+standby_mode:
+	ldr	pmc, .pmc_base
+
+	/* Wait for interrupt */
+	at91_cpu_idle
+
+pm_exit:
 	/* Exit the self-refresh mode */
 	mov	r0, #SRAMC_SELF_FRESH_EXIT
 	bl	at91_sramc_self_refresh
@@ -311,6 +300,32 @@ exit_sramc_sf:
 	mov	pc, lr
 ENDPROC(at91_sramc_self_refresh)
 
+/*
+ * void at91_pm_ulp0_mode(void)
+ */
+ENTRY(at91_pm_ulp0_mode)
+	ldr	pmc, .pmc_base
+
+	/* Turn off the crystal oscillator */
+	ldr	tmp1, [pmc, #AT91_CKGR_MOR]
+	bic	tmp1, tmp1, #AT91_PMC_MOSCEN
+	orr	tmp1, tmp1, #AT91_PMC_KEY
+	str	tmp1, [pmc, #AT91_CKGR_MOR]
+
+	/* Wait for interrupt */
+	at91_cpu_idle
+
+	/* Turn on the crystal oscillator */
+	ldr	tmp1, [pmc, #AT91_CKGR_MOR]
+	orr	tmp1, tmp1, #AT91_PMC_MOSCEN
+	orr	tmp1, tmp1, #AT91_PMC_KEY
+	str	tmp1, [pmc, #AT91_CKGR_MOR]
+
+	wait_moscrdy
+
+	mov	pc, lr
+ENDPROC(at91_pm_ulp0_mode)
+
 .pmc_base:
 	.word 0
 .sramc_base:
-- 
1.7.9.5

[PATCH v5 1/5] ARM: at91: pm: create a separate procedure for the ULP0 mode

[Wenyou Yang]

To make the code more legible and prepare to add the ULP1 mode
support in the future, create a separate procedure for the ULP0 mode.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
---

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/arm/mach-at91/pm_suspend.S |   65 ++++++++++++++++++++++++---------------
 1 file changed, 40 insertions(+), 25 deletions(-)

diff --git a/arch/arm/mach-at91/pm_suspend.S b/arch/arm/mach-at91/pm_suspend.S
index a25defd..5fcffdc 100644
--- a/arch/arm/mach-at91/pm_suspend.S
+++ b/arch/arm/mach-at91/pm_suspend.S
@@ -107,7 +107,7 @@ ENTRY(at91_pm_suspend_in_sram)
 
 	ldr	r0, .pm_mode
 	tst	r0, #AT91_PM_SLOW_CLOCK
-	beq	skip_disable_main_clock
+	beq	standby_mode
 
 	ldr	pmc, .pmc_base
 
@@ -131,32 +131,13 @@ ENTRY(at91_pm_suspend_in_sram)
 	orr	tmp1, tmp1, #(1 << 29)		/* bit 29 always set */
 	str	tmp1, [pmc, #AT91_CKGR_PLLAR]
 
-	/* Turn off the main oscillator */
-	ldr	tmp1, [pmc, #AT91_CKGR_MOR]
-	bic	tmp1, tmp1, #AT91_PMC_MOSCEN
-	orr	tmp1, tmp1, #AT91_PMC_KEY
-	str	tmp1, [pmc, #AT91_CKGR_MOR]
-
-skip_disable_main_clock:
-	ldr	pmc, .pmc_base
-
-	/* Wait for interrupt */
-	at91_cpu_idle
-
-	ldr	r0, .pm_mode
-	tst	r0, #AT91_PM_SLOW_CLOCK
-	beq	skip_enable_main_clock
+ulp0_mode:
+	bl	at91_pm_ulp0_mode
+	b	ulp_exit
 
+ulp_exit:
 	ldr	pmc, .pmc_base
 
-	/* Turn on the main oscillator */
-	ldr	tmp1, [pmc, #AT91_CKGR_MOR]
-	orr	tmp1, tmp1, #AT91_PMC_MOSCEN
-	orr	tmp1, tmp1, #AT91_PMC_KEY
-	str	tmp1, [pmc, #AT91_CKGR_MOR]
-
-	wait_moscrdy
-
 	/* Restore PLLA setting */
 	ldr	tmp1, .saved_pllar
 	str	tmp1, [pmc, #AT91_CKGR_PLLAR]
@@ -177,7 +158,15 @@ skip_disable_main_clock:
 
 	wait_mckrdy
 
-skip_enable_main_clock:
+	b	pm_exit
+
+standby_mode:
+	ldr	pmc, .pmc_base
+
+	/* Wait for interrupt */
+	at91_cpu_idle
+
+pm_exit:
 	/* Exit the self-refresh mode */
 	mov	r0, #SRAMC_SELF_FRESH_EXIT
 	bl	at91_sramc_self_refresh
@@ -311,6 +300,32 @@ exit_sramc_sf:
 	mov	pc, lr
 ENDPROC(at91_sramc_self_refresh)
 
+/*
+ * void at91_pm_ulp0_mode(void)
+ */
+ENTRY(at91_pm_ulp0_mode)
+	ldr	pmc, .pmc_base
+
+	/* Turn off the crystal oscillator */
+	ldr	tmp1, [pmc, #AT91_CKGR_MOR]
+	bic	tmp1, tmp1, #AT91_PMC_MOSCEN
+	orr	tmp1, tmp1, #AT91_PMC_KEY
+	str	tmp1, [pmc, #AT91_CKGR_MOR]
+
+	/* Wait for interrupt */
+	at91_cpu_idle
+
+	/* Turn on the crystal oscillator */
+	ldr	tmp1, [pmc, #AT91_CKGR_MOR]
+	orr	tmp1, tmp1, #AT91_PMC_MOSCEN
+	orr	tmp1, tmp1, #AT91_PMC_KEY
+	str	tmp1, [pmc, #AT91_CKGR_MOR]
+
+	wait_moscrdy
+
+	mov	pc, lr
+ENDPROC(at91_pm_ulp0_mode)
+
 .pmc_base:
 	.word 0
 .sramc_base:
-- 
1.7.9.5

[PATCH v5 1/5] ARM: at91: pm: create a separate procedure for the ULP0 mode

[Wenyou Yang]

To make the code more legible and prepare to add the ULP1 mode
support in the future, create a separate procedure for the ULP0 mode.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
---

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/arm/mach-at91/pm_suspend.S |   65 ++++++++++++++++++++++++---------------
 1 file changed, 40 insertions(+), 25 deletions(-)

diff --git a/arch/arm/mach-at91/pm_suspend.S b/arch/arm/mach-at91/pm_suspend.S
index a25defd..5fcffdc 100644
--- a/arch/arm/mach-at91/pm_suspend.S
+++ b/arch/arm/mach-at91/pm_suspend.S
@@ -107,7 +107,7 @@ ENTRY(at91_pm_suspend_in_sram)
 
 	ldr	r0, .pm_mode
 	tst	r0, #AT91_PM_SLOW_CLOCK
-	beq	skip_disable_main_clock
+	beq	standby_mode
 
 	ldr	pmc, .pmc_base
 
@@ -131,32 +131,13 @@ ENTRY(at91_pm_suspend_in_sram)
 	orr	tmp1, tmp1, #(1 << 29)		/* bit 29 always set */
 	str	tmp1, [pmc, #AT91_CKGR_PLLAR]
 
-	/* Turn off the main oscillator */
-	ldr	tmp1, [pmc, #AT91_CKGR_MOR]
-	bic	tmp1, tmp1, #AT91_PMC_MOSCEN
-	orr	tmp1, tmp1, #AT91_PMC_KEY
-	str	tmp1, [pmc, #AT91_CKGR_MOR]
-
-skip_disable_main_clock:
-	ldr	pmc, .pmc_base
-
-	/* Wait for interrupt */
-	at91_cpu_idle
-
-	ldr	r0, .pm_mode
-	tst	r0, #AT91_PM_SLOW_CLOCK
-	beq	skip_enable_main_clock
+ulp0_mode:
+	bl	at91_pm_ulp0_mode
+	b	ulp_exit
 
+ulp_exit:
 	ldr	pmc, .pmc_base
 
-	/* Turn on the main oscillator */
-	ldr	tmp1, [pmc, #AT91_CKGR_MOR]
-	orr	tmp1, tmp1, #AT91_PMC_MOSCEN
-	orr	tmp1, tmp1, #AT91_PMC_KEY
-	str	tmp1, [pmc, #AT91_CKGR_MOR]
-
-	wait_moscrdy
-
 	/* Restore PLLA setting */
 	ldr	tmp1, .saved_pllar
 	str	tmp1, [pmc, #AT91_CKGR_PLLAR]
@@ -177,7 +158,15 @@ skip_disable_main_clock:
 
 	wait_mckrdy
 
-skip_enable_main_clock:
+	b	pm_exit
+
+standby_mode:
+	ldr	pmc, .pmc_base
+
+	/* Wait for interrupt */
+	at91_cpu_idle
+
+pm_exit:
 	/* Exit the self-refresh mode */
 	mov	r0, #SRAMC_SELF_FRESH_EXIT
 	bl	at91_sramc_self_refresh
@@ -311,6 +300,32 @@ exit_sramc_sf:
 	mov	pc, lr
 ENDPROC(at91_sramc_self_refresh)
 
+/*
+ * void at91_pm_ulp0_mode(void)
+ */
+ENTRY(at91_pm_ulp0_mode)
+	ldr	pmc, .pmc_base
+
+	/* Turn off the crystal oscillator */
+	ldr	tmp1, [pmc, #AT91_CKGR_MOR]
+	bic	tmp1, tmp1, #AT91_PMC_MOSCEN
+	orr	tmp1, tmp1, #AT91_PMC_KEY
+	str	tmp1, [pmc, #AT91_CKGR_MOR]
+
+	/* Wait for interrupt */
+	at91_cpu_idle
+
+	/* Turn on the crystal oscillator */
+	ldr	tmp1, [pmc, #AT91_CKGR_MOR]
+	orr	tmp1, tmp1, #AT91_PMC_MOSCEN
+	orr	tmp1, tmp1, #AT91_PMC_KEY
+	str	tmp1, [pmc, #AT91_CKGR_MOR]
+
+	wait_moscrdy
+
+	mov	pc, lr
+ENDPROC(at91_pm_ulp0_mode)
+
 .pmc_base:
 	.word 0
 .sramc_base:
-- 
1.7.9.5

[PATCH v5 2/5] ARM: at91: pm: add ULP1 mode support

[Wenyou Yang]

The ULP1 (Ultra Low-power mode 1) is introduced by SAMA5D2.

In the ULP1 mode, all the clocks are shut off, inclusive the embedded
12MHz RC oscillator, so as to achieve the lowest power consumption
with the system in retention mode and able to resume on the wake up
events. As soon as the wake up event is asserted, the embedded 12MHz
RC oscillator restarts automatically.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
---

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
 - fix label pm_exit to ulp_exit.

 arch/arm/mach-at91/pm.c         |   16 ++++++-
 arch/arm/mach-at91/pm.h         |    7 +++
 arch/arm/mach-at91/pm_suspend.S |   97 +++++++++++++++++++++++++++++++++++++++
 include/linux/clk/at91_pmc.h    |    4 ++
 4 files changed, 122 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index f062701..5c2db34 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -36,6 +36,11 @@
 #include "generic.h"
 #include "pm.h"
 
+#define ULP0_MODE	0x00
+#define ULP1_MODE	0x11
+
+#define SAMA5D2_PMC_VERSION	0x20540
+
 static void __iomem *pmc;
 
 /*
@@ -52,6 +57,7 @@ extern void at91_pinctrl_gpio_resume(void);
 static struct {
 	unsigned long uhp_udp_mask;
 	int memctrl;
+	u32 ulp_mode;
 } at91_pm_data;
 
 void __iomem *at91_ramc_base[2];
@@ -141,8 +147,11 @@ static void at91_pm_suspend(suspend_state_t state)
 {
 	unsigned int pm_data = at91_pm_data.memctrl;
 
-	pm_data |= (state == PM_SUSPEND_MEM) ?
-				AT91_PM_MODE(AT91_PM_SLOW_CLOCK) : 0;
+	if (state == PM_SUSPEND_MEM) {
+		pm_data |= AT91_PM_MODE(AT91_PM_SLOW_CLOCK);
+		if (at91_pm_data.ulp_mode == ULP1_MODE)
+			pm_data |= AT91_PM_ULP(AT91_PM_ULP1_MODE);
+	}
 
 	flush_cache_all();
 	outer_disable();
@@ -497,4 +506,7 @@ void __init sama5_pm_init(void)
 	at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP;
 	at91_pm_data.memctrl = AT91_MEMCTRL_DDRSDR;
 	at91_pm_init(NULL);
+
+	if (readl(pmc + AT91_PMC_VERSION) >= SAMA5D2_PMC_VERSION)
+		at91_pm_data.ulp_mode = ULP1_MODE;
 }
diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h
index 3fcf881..2e76745 100644
--- a/arch/arm/mach-at91/pm.h
+++ b/arch/arm/mach-at91/pm.h
@@ -39,4 +39,11 @@ extern void __iomem *at91_ramc_base[];
 
 #define	AT91_PM_SLOW_CLOCK	0x01
 
+#define AT91_PM_ULP_OFFSET	5
+#define AT91_PM_ULP_MASK	0x03
+#define AT91_PM_ULP(x)		(((x) & AT91_PM_ULP_MASK) << AT91_PM_ULP_OFFSET)
+
+#define AT91_PM_ULP0_MODE	0x00
+#define AT91_PM_ULP1_MODE	0x01
+
 #endif
diff --git a/arch/arm/mach-at91/pm_suspend.S b/arch/arm/mach-at91/pm_suspend.S
index 5fcffdc..f2a5c4b 100644
--- a/arch/arm/mach-at91/pm_suspend.S
+++ b/arch/arm/mach-at91/pm_suspend.S
@@ -41,6 +41,15 @@ tmp2	.req	r5
 	.endm
 
 /*
+ * Wait for main oscillator selection is done
+ */
+	.macro wait_moscsels
+1:	ldr	tmp1, [pmc, #AT91_PMC_SR]
+	tst	tmp1, #AT91_PMC_MOSCSELS
+	beq	1b
+	.endm
+
+/*
  * Wait until PLLA has locked.
  */
 	.macro wait_pllalock
@@ -101,6 +110,10 @@ ENTRY(at91_pm_suspend_in_sram)
 	and	r0, r0, #AT91_PM_MODE_MASK
 	str	r0, .pm_mode
 
+	lsr	r0, r3, #AT91_PM_ULP_OFFSET
+	and	r0, r0, #AT91_PM_ULP_MASK
+	str	r0, .ulp_mode
+
 	/* Active the self-refresh mode */
 	mov	r0, #SRAMC_SELF_FRESH_ACTIVE
 	bl	at91_sramc_self_refresh
@@ -131,6 +144,13 @@ ENTRY(at91_pm_suspend_in_sram)
 	orr	tmp1, tmp1, #(1 << 29)		/* bit 29 always set */
 	str	tmp1, [pmc, #AT91_CKGR_PLLAR]
 
+	ldr	r0, .ulp_mode
+	tst	r0, #AT91_PM_ULP1_MODE
+	beq	ulp0_mode
+
+	bl	at91_pm_ulp1_mode
+	b	ulp_exit
+
 ulp0_mode:
 	bl	at91_pm_ulp0_mode
 	b	ulp_exit
@@ -326,6 +346,81 @@ ENTRY(at91_pm_ulp0_mode)
 	mov	pc, lr
 ENDPROC(at91_pm_ulp0_mode)
 
+/*
+ * void at91_pm_ulp1_mode(void)
+ */
+ENTRY(at91_pm_ulp1_mode)
+	ldr	pmc, .pmc_base
+
+	/* Switch the main clock source to 12-MHz RC oscillator */
+	ldr	tmp1, [pmc, #AT91_CKGR_MOR]
+	bic	tmp1, tmp1, #AT91_PMC_MOSCSEL
+	bic	tmp1, tmp1, #AT91_PMC_KEY_MASK
+	orr	tmp1, tmp1, #AT91_PMC_KEY
+	str	tmp1, [pmc, #AT91_CKGR_MOR]
+
+	wait_moscsels
+
+	/* Disable the crystal oscillator */
+	ldr	tmp1, [pmc, #AT91_CKGR_MOR]
+	bic	tmp1, tmp1, #AT91_PMC_MOSCEN
+	bic	tmp1, tmp1, #AT91_PMC_KEY_MASK
+	orr	tmp1, tmp1, #AT91_PMC_KEY
+	str	tmp1, [pmc, #AT91_CKGR_MOR]
+
+	/* Switch the master clock source to main clock */
+	ldr	tmp1, [pmc, #AT91_PMC_MCKR]
+	bic	tmp1, tmp1, #AT91_PMC_CSS
+	orr	tmp1, tmp1, #AT91_PMC_CSS_MAIN
+	str	tmp1, [pmc, #AT91_PMC_MCKR]
+
+	wait_mckrdy
+
+	/* Enter the ULP1 mode by set WAITMODE bit in CKGR_MOR */
+	ldr	tmp1, [pmc, #AT91_CKGR_MOR]
+	orr	tmp1, tmp1, #AT91_PMC_WAITMODE
+	bic	tmp1, tmp1, #AT91_PMC_KEY_MASK
+	orr	tmp1, tmp1, #AT91_PMC_KEY
+	str	tmp1, [pmc, #AT91_CKGR_MOR]
+
+	wait_mckrdy
+
+	/* Enable the crystal oscillator */
+	ldr	tmp1, [pmc, #AT91_CKGR_MOR]
+	orr	tmp1, tmp1, #AT91_PMC_MOSCEN
+	bic	tmp1, tmp1, #AT91_PMC_KEY_MASK
+	orr	tmp1, tmp1, #AT91_PMC_KEY
+	str	tmp1, [pmc, #AT91_CKGR_MOR]
+
+	wait_moscrdy
+
+	/* Switch the master clock source to slow clock */
+	ldr	tmp1, [pmc, #AT91_PMC_MCKR]
+	bic	tmp1, tmp1, #AT91_PMC_CSS
+	str	tmp1, [pmc, #AT91_PMC_MCKR]
+
+	wait_mckrdy
+
+	/* Switch main clock source to crystal oscillator */
+	ldr	tmp1, [pmc, #AT91_CKGR_MOR]
+	orr	tmp1, tmp1, #AT91_PMC_MOSCSEL
+	bic	tmp1, tmp1, #AT91_PMC_KEY_MASK
+	orr	tmp1, tmp1, #AT91_PMC_KEY
+	str	tmp1, [pmc, #AT91_CKGR_MOR]
+
+	wait_moscsels
+
+	/* Switch the master clock source to main clock */
+	ldr	tmp1, [pmc, #AT91_PMC_MCKR]
+	bic	tmp1, tmp1, #AT91_PMC_CSS
+	orr	tmp1, tmp1, #AT91_PMC_CSS_MAIN
+	str	tmp1, [pmc, #AT91_PMC_MCKR]
+
+	wait_mckrdy
+
+	mov	pc, lr
+ENDPROC(at91_pm_ulp1_mode)
+
 .pmc_base:
 	.word 0
 .sramc_base:
@@ -336,6 +431,8 @@ ENDPROC(at91_pm_ulp0_mode)
 	.word 0
 .pm_mode:
 	.word 0
+.ulp_mode:
+	.word 0
 .saved_mckr:
 	.word 0
 .saved_pllar:
diff --git a/include/linux/clk/at91_pmc.h b/include/linux/clk/at91_pmc.h
index 17f413b..4afd891 100644
--- a/include/linux/clk/at91_pmc.h
+++ b/include/linux/clk/at91_pmc.h
@@ -47,8 +47,10 @@
 #define	AT91_CKGR_MOR		0x20			/* Main Oscillator Register [not on SAM9RL] */
 #define		AT91_PMC_MOSCEN		(1    <<  0)		/* Main Oscillator Enable */
 #define		AT91_PMC_OSCBYPASS	(1    <<  1)		/* Oscillator Bypass */
+#define		AT91_PMC_WAITMODE	(1    <<  2)		/* Wait Mode Command */
 #define		AT91_PMC_MOSCRCEN	(1    <<  3)		/* Main On-Chip RC Oscillator Enable [some SAM9] */
 #define		AT91_PMC_OSCOUNT	(0xff <<  8)		/* Main Oscillator Start-up Time */
+#define		AT91_PMC_KEY_MASK	(0xff << 16)
 #define		AT91_PMC_KEY		(0x37 << 16)		/* MOR Writing Key */
 #define		AT91_PMC_MOSCSEL	(1    << 24)		/* Main Oscillator Selection [some SAM9] */
 #define		AT91_PMC_CFDEN		(1    << 25)		/* Clock Failure Detector Enable [some SAM9] */
@@ -166,6 +168,8 @@
 #define		AT91_PMC_WPVS		(0x1  <<  0)		/* Write Protect Violation Status */
 #define		AT91_PMC_WPVSRC		(0xffff  <<  8)		/* Write Protect Violation Source */
 
+#define AT91_PMC_VERSION	0xfc
+
 #define AT91_PMC_PCER1		0x100			/* Peripheral Clock Enable Register 1 [SAMA5 only]*/
 #define AT91_PMC_PCDR1		0x104			/* Peripheral Clock Enable Register 1 */
 #define AT91_PMC_PCSR1		0x108			/* Peripheral Clock Enable Register 1 */
-- 
1.7.9.5

[PATCH v5 2/5] ARM: at91: pm: add ULP1 mode support

[Wenyou Yang]

The ULP1 (Ultra Low-power mode 1) is introduced by SAMA5D2.

In the ULP1 mode, all the clocks are shut off, inclusive the embedded
12MHz RC oscillator, so as to achieve the lowest power consumption
with the system in retention mode and able to resume on the wake up
events. As soon as the wake up event is asserted, the embedded 12MHz
RC oscillator restarts automatically.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
---

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
 - fix label pm_exit to ulp_exit.

 arch/arm/mach-at91/pm.c         |   16 ++++++-
 arch/arm/mach-at91/pm.h         |    7 +++
 arch/arm/mach-at91/pm_suspend.S |   97 +++++++++++++++++++++++++++++++++++++++
 include/linux/clk/at91_pmc.h    |    4 ++
 4 files changed, 122 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index f062701..5c2db34 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -36,6 +36,11 @@
 #include "generic.h"
 #include "pm.h"
 
+#define ULP0_MODE	0x00
+#define ULP1_MODE	0x11
+
+#define SAMA5D2_PMC_VERSION	0x20540
+
 static void __iomem *pmc;
 
 /*
@@ -52,6 +57,7 @@ extern void at91_pinctrl_gpio_resume(void);
 static struct {
 	unsigned long uhp_udp_mask;
 	int memctrl;
+	u32 ulp_mode;
 } at91_pm_data;
 
 void __iomem *at91_ramc_base[2];
@@ -141,8 +147,11 @@ static void at91_pm_suspend(suspend_state_t state)
 {
 	unsigned int pm_data = at91_pm_data.memctrl;
 
-	pm_data |= (state == PM_SUSPEND_MEM) ?
-				AT91_PM_MODE(AT91_PM_SLOW_CLOCK) : 0;
+	if (state == PM_SUSPEND_MEM) {
+		pm_data |= AT91_PM_MODE(AT91_PM_SLOW_CLOCK);
+		if (at91_pm_data.ulp_mode == ULP1_MODE)
+			pm_data |= AT91_PM_ULP(AT91_PM_ULP1_MODE);
+	}
 
 	flush_cache_all();
 	outer_disable();
@@ -497,4 +506,7 @@ void __init sama5_pm_init(void)
 	at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP;
 	at91_pm_data.memctrl = AT91_MEMCTRL_DDRSDR;
 	at91_pm_init(NULL);
+
+	if (readl(pmc + AT91_PMC_VERSION) >= SAMA5D2_PMC_VERSION)
+		at91_pm_data.ulp_mode = ULP1_MODE;
 }
diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h
index 3fcf881..2e76745 100644
--- a/arch/arm/mach-at91/pm.h
+++ b/arch/arm/mach-at91/pm.h
@@ -39,4 +39,11 @@ extern void __iomem *at91_ramc_base[];
 
 #define	AT91_PM_SLOW_CLOCK	0x01
 
+#define AT91_PM_ULP_OFFSET	5
+#define AT91_PM_ULP_MASK	0x03
+#define AT91_PM_ULP(x)		(((x) & AT91_PM_ULP_MASK) << AT91_PM_ULP_OFFSET)
+
+#define AT91_PM_ULP0_MODE	0x00
+#define AT91_PM_ULP1_MODE	0x01
+
 #endif
diff --git a/arch/arm/mach-at91/pm_suspend.S b/arch/arm/mach-at91/pm_suspend.S
index 5fcffdc..f2a5c4b 100644
--- a/arch/arm/mach-at91/pm_suspend.S
+++ b/arch/arm/mach-at91/pm_suspend.S
@@ -41,6 +41,15 @@ tmp2	.req	r5
 	.endm
 
 /*
+ * Wait for main oscillator selection is done
+ */
+	.macro wait_moscsels
+1:	ldr	tmp1, [pmc, #AT91_PMC_SR]
+	tst	tmp1, #AT91_PMC_MOSCSELS
+	beq	1b
+	.endm
+
+/*
  * Wait until PLLA has locked.
  */
 	.macro wait_pllalock
@@ -101,6 +110,10 @@ ENTRY(at91_pm_suspend_in_sram)
 	and	r0, r0, #AT91_PM_MODE_MASK
 	str	r0, .pm_mode
 
+	lsr	r0, r3, #AT91_PM_ULP_OFFSET
+	and	r0, r0, #AT91_PM_ULP_MASK
+	str	r0, .ulp_mode
+
 	/* Active the self-refresh mode */
 	mov	r0, #SRAMC_SELF_FRESH_ACTIVE
 	bl	at91_sramc_self_refresh
@@ -131,6 +144,13 @@ ENTRY(at91_pm_suspend_in_sram)
 	orr	tmp1, tmp1, #(1 << 29)		/* bit 29 always set */
 	str	tmp1, [pmc, #AT91_CKGR_PLLAR]
 
+	ldr	r0, .ulp_mode
+	tst	r0, #AT91_PM_ULP1_MODE
+	beq	ulp0_mode
+
+	bl	at91_pm_ulp1_mode
+	b	ulp_exit
+
 ulp0_mode:
 	bl	at91_pm_ulp0_mode
 	b	ulp_exit
@@ -326,6 +346,81 @@ ENTRY(at91_pm_ulp0_mode)
 	mov	pc, lr
 ENDPROC(at91_pm_ulp0_mode)
 
+/*
+ * void at91_pm_ulp1_mode(void)
+ */
+ENTRY(at91_pm_ulp1_mode)
+	ldr	pmc, .pmc_base
+
+	/* Switch the main clock source to 12-MHz RC oscillator */
+	ldr	tmp1, [pmc, #AT91_CKGR_MOR]
+	bic	tmp1, tmp1, #AT91_PMC_MOSCSEL
+	bic	tmp1, tmp1, #AT91_PMC_KEY_MASK
+	orr	tmp1, tmp1, #AT91_PMC_KEY
+	str	tmp1, [pmc, #AT91_CKGR_MOR]
+
+	wait_moscsels
+
+	/* Disable the crystal oscillator */
+	ldr	tmp1, [pmc, #AT91_CKGR_MOR]
+	bic	tmp1, tmp1, #AT91_PMC_MOSCEN
+	bic	tmp1, tmp1, #AT91_PMC_KEY_MASK
+	orr	tmp1, tmp1, #AT91_PMC_KEY
+	str	tmp1, [pmc, #AT91_CKGR_MOR]
+
+	/* Switch the master clock source to main clock */
+	ldr	tmp1, [pmc, #AT91_PMC_MCKR]
+	bic	tmp1, tmp1, #AT91_PMC_CSS
+	orr	tmp1, tmp1, #AT91_PMC_CSS_MAIN
+	str	tmp1, [pmc, #AT91_PMC_MCKR]
+
+	wait_mckrdy
+
+	/* Enter the ULP1 mode by set WAITMODE bit in CKGR_MOR */
+	ldr	tmp1, [pmc, #AT91_CKGR_MOR]
+	orr	tmp1, tmp1, #AT91_PMC_WAITMODE
+	bic	tmp1, tmp1, #AT91_PMC_KEY_MASK
+	orr	tmp1, tmp1, #AT91_PMC_KEY
+	str	tmp1, [pmc, #AT91_CKGR_MOR]
+
+	wait_mckrdy
+
+	/* Enable the crystal oscillator */
+	ldr	tmp1, [pmc, #AT91_CKGR_MOR]
+	orr	tmp1, tmp1, #AT91_PMC_MOSCEN
+	bic	tmp1, tmp1, #AT91_PMC_KEY_MASK
+	orr	tmp1, tmp1, #AT91_PMC_KEY
+	str	tmp1, [pmc, #AT91_CKGR_MOR]
+
+	wait_moscrdy
+
+	/* Switch the master clock source to slow clock */
+	ldr	tmp1, [pmc, #AT91_PMC_MCKR]
+	bic	tmp1, tmp1, #AT91_PMC_CSS
+	str	tmp1, [pmc, #AT91_PMC_MCKR]
+
+	wait_mckrdy
+
+	/* Switch main clock source to crystal oscillator */
+	ldr	tmp1, [pmc, #AT91_CKGR_MOR]
+	orr	tmp1, tmp1, #AT91_PMC_MOSCSEL
+	bic	tmp1, tmp1, #AT91_PMC_KEY_MASK
+	orr	tmp1, tmp1, #AT91_PMC_KEY
+	str	tmp1, [pmc, #AT91_CKGR_MOR]
+
+	wait_moscsels
+
+	/* Switch the master clock source to main clock */
+	ldr	tmp1, [pmc, #AT91_PMC_MCKR]
+	bic	tmp1, tmp1, #AT91_PMC_CSS
+	orr	tmp1, tmp1, #AT91_PMC_CSS_MAIN
+	str	tmp1, [pmc, #AT91_PMC_MCKR]
+
+	wait_mckrdy
+
+	mov	pc, lr
+ENDPROC(at91_pm_ulp1_mode)
+
 .pmc_base:
 	.word 0
 .sramc_base:
@@ -336,6 +431,8 @@ ENDPROC(at91_pm_ulp0_mode)
 	.word 0
 .pm_mode:
 	.word 0
+.ulp_mode:
+	.word 0
 .saved_mckr:
 	.word 0
 .saved_pllar:
diff --git a/include/linux/clk/at91_pmc.h b/include/linux/clk/at91_pmc.h
index 17f413b..4afd891 100644
--- a/include/linux/clk/at91_pmc.h
+++ b/include/linux/clk/at91_pmc.h
@@ -47,8 +47,10 @@
 #define	AT91_CKGR_MOR		0x20			/* Main Oscillator Register [not on SAM9RL] */
 #define		AT91_PMC_MOSCEN		(1    <<  0)		/* Main Oscillator Enable */
 #define		AT91_PMC_OSCBYPASS	(1    <<  1)		/* Oscillator Bypass */
+#define		AT91_PMC_WAITMODE	(1    <<  2)		/* Wait Mode Command */
 #define		AT91_PMC_MOSCRCEN	(1    <<  3)		/* Main On-Chip RC Oscillator Enable [some SAM9] */
 #define		AT91_PMC_OSCOUNT	(0xff <<  8)		/* Main Oscillator Start-up Time */
+#define		AT91_PMC_KEY_MASK	(0xff << 16)
 #define		AT91_PMC_KEY		(0x37 << 16)		/* MOR Writing Key */
 #define		AT91_PMC_MOSCSEL	(1    << 24)		/* Main Oscillator Selection [some SAM9] */
 #define		AT91_PMC_CFDEN		(1    << 25)		/* Clock Failure Detector Enable [some SAM9] */
@@ -166,6 +168,8 @@
 #define		AT91_PMC_WPVS		(0x1  <<  0)		/* Write Protect Violation Status */
 #define		AT91_PMC_WPVSRC		(0xffff  <<  8)		/* Write Protect Violation Source */
 
+#define AT91_PMC_VERSION	0xfc
+
 #define AT91_PMC_PCER1		0x100			/* Peripheral Clock Enable Register 1 [SAMA5 only]*/
 #define AT91_PMC_PCDR1		0x104			/* Peripheral Clock Enable Register 1 */
 #define AT91_PMC_PCSR1		0x108			/* Peripheral Clock Enable Register 1 */
-- 
1.7.9.5

[PATCH v5 2/5] ARM: at91: pm: add ULP1 mode support

[Wenyou Yang]

The ULP1 (Ultra Low-power mode 1) is introduced by SAMA5D2.

In the ULP1 mode, all the clocks are shut off, inclusive the embedded
12MHz RC oscillator, so as to achieve the lowest power consumption
with the system in retention mode and able to resume on the wake up
events. As soon as the wake up event is asserted, the embedded 12MHz
RC oscillator restarts automatically.

Signed-off-by: Wenyou Yang <wenyou.yang-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org>
---

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
 - fix label pm_exit to ulp_exit.

 arch/arm/mach-at91/pm.c         |   16 ++++++-
 arch/arm/mach-at91/pm.h         |    7 +++
 arch/arm/mach-at91/pm_suspend.S |   97 +++++++++++++++++++++++++++++++++++++++
 include/linux/clk/at91_pmc.h    |    4 ++
 4 files changed, 122 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index f062701..5c2db34 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -36,6 +36,11 @@
 #include "generic.h"
 #include "pm.h"
 
+#define ULP0_MODE	0x00
+#define ULP1_MODE	0x11
+
+#define SAMA5D2_PMC_VERSION	0x20540
+
 static void __iomem *pmc;
 
 /*
@@ -52,6 +57,7 @@ extern void at91_pinctrl_gpio_resume(void);
 static struct {
 	unsigned long uhp_udp_mask;
 	int memctrl;
+	u32 ulp_mode;
 } at91_pm_data;
 
 void __iomem *at91_ramc_base[2];
@@ -141,8 +147,11 @@ static void at91_pm_suspend(suspend_state_t state)
 {
 	unsigned int pm_data = at91_pm_data.memctrl;
 
-	pm_data |= (state == PM_SUSPEND_MEM) ?
-				AT91_PM_MODE(AT91_PM_SLOW_CLOCK) : 0;
+	if (state == PM_SUSPEND_MEM) {
+		pm_data |= AT91_PM_MODE(AT91_PM_SLOW_CLOCK);
+		if (at91_pm_data.ulp_mode == ULP1_MODE)
+			pm_data |= AT91_PM_ULP(AT91_PM_ULP1_MODE);
+	}
 
 	flush_cache_all();
 	outer_disable();
@@ -497,4 +506,7 @@ void __init sama5_pm_init(void)
 	at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP;
 	at91_pm_data.memctrl = AT91_MEMCTRL_DDRSDR;
 	at91_pm_init(NULL);
+
+	if (readl(pmc + AT91_PMC_VERSION) >= SAMA5D2_PMC_VERSION)
+		at91_pm_data.ulp_mode = ULP1_MODE;
 }
diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h
index 3fcf881..2e76745 100644
--- a/arch/arm/mach-at91/pm.h
+++ b/arch/arm/mach-at91/pm.h
@@ -39,4 +39,11 @@ extern void __iomem *at91_ramc_base[];
 
 #define	AT91_PM_SLOW_CLOCK	0x01
 
+#define AT91_PM_ULP_OFFSET	5
+#define AT91_PM_ULP_MASK	0x03
+#define AT91_PM_ULP(x)		(((x) & AT91_PM_ULP_MASK) << AT91_PM_ULP_OFFSET)
+
+#define AT91_PM_ULP0_MODE	0x00
+#define AT91_PM_ULP1_MODE	0x01
+
 #endif
diff --git a/arch/arm/mach-at91/pm_suspend.S b/arch/arm/mach-at91/pm_suspend.S
index 5fcffdc..f2a5c4b 100644
--- a/arch/arm/mach-at91/pm_suspend.S
+++ b/arch/arm/mach-at91/pm_suspend.S
@@ -41,6 +41,15 @@ tmp2	.req	r5
 	.endm
 
 /*
+ * Wait for main oscillator selection is done
+ */
+	.macro wait_moscsels
+1:	ldr	tmp1, [pmc, #AT91_PMC_SR]
+	tst	tmp1, #AT91_PMC_MOSCSELS
+	beq	1b
+	.endm
+
+/*
  * Wait until PLLA has locked.
  */
 	.macro wait_pllalock
@@ -101,6 +110,10 @@ ENTRY(at91_pm_suspend_in_sram)
 	and	r0, r0, #AT91_PM_MODE_MASK
 	str	r0, .pm_mode
 
+	lsr	r0, r3, #AT91_PM_ULP_OFFSET
+	and	r0, r0, #AT91_PM_ULP_MASK
+	str	r0, .ulp_mode
+
 	/* Active the self-refresh mode */
 	mov	r0, #SRAMC_SELF_FRESH_ACTIVE
 	bl	at91_sramc_self_refresh
@@ -131,6 +144,13 @@ ENTRY(at91_pm_suspend_in_sram)
 	orr	tmp1, tmp1, #(1 << 29)		/* bit 29 always set */
 	str	tmp1, [pmc, #AT91_CKGR_PLLAR]
 
+	ldr	r0, .ulp_mode
+	tst	r0, #AT91_PM_ULP1_MODE
+	beq	ulp0_mode
+
+	bl	at91_pm_ulp1_mode
+	b	ulp_exit
+
 ulp0_mode:
 	bl	at91_pm_ulp0_mode
 	b	ulp_exit
@@ -326,6 +346,81 @@ ENTRY(at91_pm_ulp0_mode)
 	mov	pc, lr
 ENDPROC(at91_pm_ulp0_mode)
 
+/*
+ * void at91_pm_ulp1_mode(void)
+ */
+ENTRY(at91_pm_ulp1_mode)
+	ldr	pmc, .pmc_base
+
+	/* Switch the main clock source to 12-MHz RC oscillator */
+	ldr	tmp1, [pmc, #AT91_CKGR_MOR]
+	bic	tmp1, tmp1, #AT91_PMC_MOSCSEL
+	bic	tmp1, tmp1, #AT91_PMC_KEY_MASK
+	orr	tmp1, tmp1, #AT91_PMC_KEY
+	str	tmp1, [pmc, #AT91_CKGR_MOR]
+
+	wait_moscsels
+
+	/* Disable the crystal oscillator */
+	ldr	tmp1, [pmc, #AT91_CKGR_MOR]
+	bic	tmp1, tmp1, #AT91_PMC_MOSCEN
+	bic	tmp1, tmp1, #AT91_PMC_KEY_MASK
+	orr	tmp1, tmp1, #AT91_PMC_KEY
+	str	tmp1, [pmc, #AT91_CKGR_MOR]
+
+	/* Switch the master clock source to main clock */
+	ldr	tmp1, [pmc, #AT91_PMC_MCKR]
+	bic	tmp1, tmp1, #AT91_PMC_CSS
+	orr	tmp1, tmp1, #AT91_PMC_CSS_MAIN
+	str	tmp1, [pmc, #AT91_PMC_MCKR]
+
+	wait_mckrdy
+
+	/* Enter the ULP1 mode by set WAITMODE bit in CKGR_MOR */
+	ldr	tmp1, [pmc, #AT91_CKGR_MOR]
+	orr	tmp1, tmp1, #AT91_PMC_WAITMODE
+	bic	tmp1, tmp1, #AT91_PMC_KEY_MASK
+	orr	tmp1, tmp1, #AT91_PMC_KEY
+	str	tmp1, [pmc, #AT91_CKGR_MOR]
+
+	wait_mckrdy
+
+	/* Enable the crystal oscillator */
+	ldr	tmp1, [pmc, #AT91_CKGR_MOR]
+	orr	tmp1, tmp1, #AT91_PMC_MOSCEN
+	bic	tmp1, tmp1, #AT91_PMC_KEY_MASK
+	orr	tmp1, tmp1, #AT91_PMC_KEY
+	str	tmp1, [pmc, #AT91_CKGR_MOR]
+
+	wait_moscrdy
+
+	/* Switch the master clock source to slow clock */
+	ldr	tmp1, [pmc, #AT91_PMC_MCKR]
+	bic	tmp1, tmp1, #AT91_PMC_CSS
+	str	tmp1, [pmc, #AT91_PMC_MCKR]
+
+	wait_mckrdy
+
+	/* Switch main clock source to crystal oscillator */
+	ldr	tmp1, [pmc, #AT91_CKGR_MOR]
+	orr	tmp1, tmp1, #AT91_PMC_MOSCSEL
+	bic	tmp1, tmp1, #AT91_PMC_KEY_MASK
+	orr	tmp1, tmp1, #AT91_PMC_KEY
+	str	tmp1, [pmc, #AT91_CKGR_MOR]
+
+	wait_moscsels
+
+	/* Switch the master clock source to main clock */
+	ldr	tmp1, [pmc, #AT91_PMC_MCKR]
+	bic	tmp1, tmp1, #AT91_PMC_CSS
+	orr	tmp1, tmp1, #AT91_PMC_CSS_MAIN
+	str	tmp1, [pmc, #AT91_PMC_MCKR]
+
+	wait_mckrdy
+
+	mov	pc, lr
+ENDPROC(at91_pm_ulp1_mode)
+
 .pmc_base:
 	.word 0
 .sramc_base:
@@ -336,6 +431,8 @@ ENDPROC(at91_pm_ulp0_mode)
 	.word 0
 .pm_mode:
 	.word 0
+.ulp_mode:
+	.word 0
 .saved_mckr:
 	.word 0
 .saved_pllar:
diff --git a/include/linux/clk/at91_pmc.h b/include/linux/clk/at91_pmc.h
index 17f413b..4afd891 100644
--- a/include/linux/clk/at91_pmc.h
+++ b/include/linux/clk/at91_pmc.h
@@ -47,8 +47,10 @@
 #define	AT91_CKGR_MOR		0x20			/* Main Oscillator Register [not on SAM9RL] */
 #define		AT91_PMC_MOSCEN		(1    <<  0)		/* Main Oscillator Enable */
 #define		AT91_PMC_OSCBYPASS	(1    <<  1)		/* Oscillator Bypass */
+#define		AT91_PMC_WAITMODE	(1    <<  2)		/* Wait Mode Command */
 #define		AT91_PMC_MOSCRCEN	(1    <<  3)		/* Main On-Chip RC Oscillator Enable [some SAM9] */
 #define		AT91_PMC_OSCOUNT	(0xff <<  8)		/* Main Oscillator Start-up Time */
+#define		AT91_PMC_KEY_MASK	(0xff << 16)
 #define		AT91_PMC_KEY		(0x37 << 16)		/* MOR Writing Key */
 #define		AT91_PMC_MOSCSEL	(1    << 24)		/* Main Oscillator Selection [some SAM9] */
 #define		AT91_PMC_CFDEN		(1    << 25)		/* Clock Failure Detector Enable [some SAM9] */
@@ -166,6 +168,8 @@
 #define		AT91_PMC_WPVS		(0x1  <<  0)		/* Write Protect Violation Status */
 #define		AT91_PMC_WPVSRC		(0xffff  <<  8)		/* Write Protect Violation Source */
 
+#define AT91_PMC_VERSION	0xfc
+
 #define AT91_PMC_PCER1		0x100			/* Peripheral Clock Enable Register 1 [SAMA5 only]*/
 #define AT91_PMC_PCDR1		0x104			/* Peripheral Clock Enable Register 1 */
 #define AT91_PMC_PCSR1		0x108			/* Peripheral Clock Enable Register 1 */
-- 
1.7.9.5

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[PATCH v5 3/5] ARM: at91: pm: configure PMC fast startup signals

[Wenyou Yang]

The fast startup signal is used as wake up sources for ULP1 mode.
As soon as a fast startup signal is asserted, the embedded 12 MHz
RC oscillator restarts automatically.

This patch is to configure the fast startup signals, which signal
is enabled to trigger the PMC to wake up the system from ULP1 mode
should be configured via the DT.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
---

Changes in v5:
 - to improve the scalability, rework the DT expression part, use
   the child nodes to describe the wake-up input and its active level.

Changes in v4: None
Changes in v3:
 - use 0 and 1, not string, to define the trigger active polarity.

Changes in v2:
 - shorten the pmc-fast-startup property's name.
 - use the value property, instead of bool property for high
   or low triggered.

 arch/arm/mach-at91/pm.c      |   66 ++++++++++++++++++++++++++++++++++++++++++
 include/linux/clk/at91_pmc.h |   14 +++++++++
 2 files changed, 80 insertions(+)

diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index 5c2db34..29895f1 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -24,6 +24,8 @@
 #include <linux/platform_device.h>
 #include <linux/io.h>
 #include <linux/clk/at91_pmc.h>
+#include <linux/mfd/syscon.h>
+#include <linux/regmap.h>
 
 #include <asm/irq.h>
 #include <linux/atomic.h>
@@ -461,6 +463,68 @@ static void __init at91_pm_init(void (*pm_idle)(void))
 		pr_info("AT91: PM not supported, due to no SRAM allocated\n");
 }
 
+static int __init at91_pmc_fast_startup_init(void)
+{
+	struct device_node *np, *cnp;
+	struct regmap *regmap;
+	u32 input, input_mask;
+	u32 mode = 0, polarity = 0;
+
+	np = of_find_compatible_node(NULL, NULL,
+				     "atmel,sama5d2-pmc-fast-startup");
+	if (!np)
+		return -ENODEV;
+
+	regmap = syscon_node_to_regmap(of_get_parent(np));
+	if (IS_ERR(regmap)) {
+		pr_info("AT91: failed to find PMC fast startup node\n");
+		return PTR_ERR(regmap);
+	}
+
+	for_each_child_of_node(np, cnp) {
+		if (of_property_read_u32(cnp, "reg", &input)) {
+			pr_warn("AT91: reg property is missing for %s\n",
+				cnp->full_name);
+			continue;
+		}
+
+		input_mask = 1 << input;
+		if (!(input_mask & AT91_PMC_FS_INPUT_MASK)) {
+			pr_warn("AT91: wake-up input %d out of range\n", input);
+			continue;
+		}
+		mode |= input_mask;
+
+		if (of_property_read_bool(cnp, "atmel,wakeup-active-high"))
+			polarity |= input_mask;
+	}
+
+	if (of_property_read_bool(np, "atmel,wakeup-rtc-timer"))
+		mode |= AT91_PMC_RTCAL;
+
+	if (of_property_read_bool(np, "atmel,wakeup-usb-resume"))
+		mode |= AT91_PMC_USBAL;
+
+	if (of_property_read_bool(np, "atmel,wakeup-sdmmc-cd"))
+		mode |= AT91_PMC_SDMMC_CD;
+
+	if (of_property_read_bool(np, "atmel,wakeup-rxlp-match"))
+		mode |= AT91_PMC_RXLP_MCE;
+
+	if (of_property_read_bool(np, "atmel,wakeup-acc-comparison"))
+		mode |= AT91_PMC_ACC_CE;
+
+	pr_debug("AT91: mode = 0x%x, ploarity = 0%x\n", mode, polarity);
+
+	regmap_write(regmap, AT91_PMC_FSMR, mode);
+
+	regmap_write(regmap, AT91_PMC_FSPR, polarity);
+
+	of_node_put(np);
+
+	return 0;
+}
+
 void __init at91rm9200_pm_init(void)
 {
 	at91_dt_ramc();
@@ -509,4 +573,6 @@ void __init sama5_pm_init(void)
 
 	if (readl(pmc + AT91_PMC_VERSION) >= SAMA5D2_PMC_VERSION)
 		at91_pm_data.ulp_mode = ULP1_MODE;
+
+	at91_pmc_fast_startup_init();
 }
diff --git a/include/linux/clk/at91_pmc.h b/include/linux/clk/at91_pmc.h
index 4afd891..4b942c5 100644
--- a/include/linux/clk/at91_pmc.h
+++ b/include/linux/clk/at91_pmc.h
@@ -168,6 +168,20 @@
 #define		AT91_PMC_WPVS		(0x1  <<  0)		/* Write Protect Violation Status */
 #define		AT91_PMC_WPVSRC		(0xffff  <<  8)		/* Write Protect Violation Source */
 
+#define AT91_PMC_FSMR		0x70		/* Fast Startup Mode Register */
+#define AT91_PMC_FSTT(n)	(0x1 << n)
+#define AT91_PMC_RTCAL		BIT(17)		/* RTC Alarm Enable */
+#define AT91_PMC_USBAL		BIT(18)		/* USB Resume Enable */
+#define AT91_PMC_SDMMC_CD	BIT(19)		/* SDMMC Card Detect Enable */
+#define AT91_PMC_LPM		BIT(20)		/* Low-power Mode */
+#define AT91_PMC_RXLP_MCE	BIT(24)		/* Backup UART Receive Enable */
+#define AT91_PMC_ACC_CE		BIT(25)		/* ACC Enable */
+
+#define AT91_PMC_FSPR		0x74		/* Fast Startup Polarity Reg */
+#define AT91_PMC_FSTP(n)	(0x1 << n)
+
+#define AT91_PMC_FS_INPUT_MASK  0x7ff
+
 #define AT91_PMC_VERSION	0xfc
 
 #define AT91_PMC_PCER1		0x100			/* Peripheral Clock Enable Register 1 [SAMA5 only]*/
-- 
1.7.9.5

[PATCH v5 3/5] ARM: at91: pm: configure PMC fast startup signals

[Wenyou Yang]

The fast startup signal is used as wake up sources for ULP1 mode.
As soon as a fast startup signal is asserted, the embedded 12 MHz
RC oscillator restarts automatically.

This patch is to configure the fast startup signals, which signal
is enabled to trigger the PMC to wake up the system from ULP1 mode
should be configured via the DT.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
---

Changes in v5:
 - to improve the scalability, rework the DT expression part, use
   the child nodes to describe the wake-up input and its active level.

Changes in v4: None
Changes in v3:
 - use 0 and 1, not string, to define the trigger active polarity.

Changes in v2:
 - shorten the pmc-fast-startup property's name.
 - use the value property, instead of bool property for high
   or low triggered.

 arch/arm/mach-at91/pm.c      |   66 ++++++++++++++++++++++++++++++++++++++++++
 include/linux/clk/at91_pmc.h |   14 +++++++++
 2 files changed, 80 insertions(+)

diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index 5c2db34..29895f1 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -24,6 +24,8 @@
 #include <linux/platform_device.h>
 #include <linux/io.h>
 #include <linux/clk/at91_pmc.h>
+#include <linux/mfd/syscon.h>
+#include <linux/regmap.h>
 
 #include <asm/irq.h>
 #include <linux/atomic.h>
@@ -461,6 +463,68 @@ static void __init at91_pm_init(void (*pm_idle)(void))
 		pr_info("AT91: PM not supported, due to no SRAM allocated\n");
 }
 
+static int __init at91_pmc_fast_startup_init(void)
+{
+	struct device_node *np, *cnp;
+	struct regmap *regmap;
+	u32 input, input_mask;
+	u32 mode = 0, polarity = 0;
+
+	np = of_find_compatible_node(NULL, NULL,
+				     "atmel,sama5d2-pmc-fast-startup");
+	if (!np)
+		return -ENODEV;
+
+	regmap = syscon_node_to_regmap(of_get_parent(np));
+	if (IS_ERR(regmap)) {
+		pr_info("AT91: failed to find PMC fast startup node\n");
+		return PTR_ERR(regmap);
+	}
+
+	for_each_child_of_node(np, cnp) {
+		if (of_property_read_u32(cnp, "reg", &input)) {
+			pr_warn("AT91: reg property is missing for %s\n",
+				cnp->full_name);
+			continue;
+		}
+
+		input_mask = 1 << input;
+		if (!(input_mask & AT91_PMC_FS_INPUT_MASK)) {
+			pr_warn("AT91: wake-up input %d out of range\n", input);
+			continue;
+		}
+		mode |= input_mask;
+
+		if (of_property_read_bool(cnp, "atmel,wakeup-active-high"))
+			polarity |= input_mask;
+	}
+
+	if (of_property_read_bool(np, "atmel,wakeup-rtc-timer"))
+		mode |= AT91_PMC_RTCAL;
+
+	if (of_property_read_bool(np, "atmel,wakeup-usb-resume"))
+		mode |= AT91_PMC_USBAL;
+
+	if (of_property_read_bool(np, "atmel,wakeup-sdmmc-cd"))
+		mode |= AT91_PMC_SDMMC_CD;
+
+	if (of_property_read_bool(np, "atmel,wakeup-rxlp-match"))
+		mode |= AT91_PMC_RXLP_MCE;
+
+	if (of_property_read_bool(np, "atmel,wakeup-acc-comparison"))
+		mode |= AT91_PMC_ACC_CE;
+
+	pr_debug("AT91: mode = 0x%x, ploarity = 0%x\n", mode, polarity);
+
+	regmap_write(regmap, AT91_PMC_FSMR, mode);
+
+	regmap_write(regmap, AT91_PMC_FSPR, polarity);
+
+	of_node_put(np);
+
+	return 0;
+}
+
 void __init at91rm9200_pm_init(void)
 {
 	at91_dt_ramc();
@@ -509,4 +573,6 @@ void __init sama5_pm_init(void)
 
 	if (readl(pmc + AT91_PMC_VERSION) >= SAMA5D2_PMC_VERSION)
 		at91_pm_data.ulp_mode = ULP1_MODE;
+
+	at91_pmc_fast_startup_init();
 }
diff --git a/include/linux/clk/at91_pmc.h b/include/linux/clk/at91_pmc.h
index 4afd891..4b942c5 100644
--- a/include/linux/clk/at91_pmc.h
+++ b/include/linux/clk/at91_pmc.h
@@ -168,6 +168,20 @@
 #define		AT91_PMC_WPVS		(0x1  <<  0)		/* Write Protect Violation Status */
 #define		AT91_PMC_WPVSRC		(0xffff  <<  8)		/* Write Protect Violation Source */
 
+#define AT91_PMC_FSMR		0x70		/* Fast Startup Mode Register */
+#define AT91_PMC_FSTT(n)	(0x1 << n)
+#define AT91_PMC_RTCAL		BIT(17)		/* RTC Alarm Enable */
+#define AT91_PMC_USBAL		BIT(18)		/* USB Resume Enable */
+#define AT91_PMC_SDMMC_CD	BIT(19)		/* SDMMC Card Detect Enable */
+#define AT91_PMC_LPM		BIT(20)		/* Low-power Mode */
+#define AT91_PMC_RXLP_MCE	BIT(24)		/* Backup UART Receive Enable */
+#define AT91_PMC_ACC_CE		BIT(25)		/* ACC Enable */
+
+#define AT91_PMC_FSPR		0x74		/* Fast Startup Polarity Reg */
+#define AT91_PMC_FSTP(n)	(0x1 << n)
+
+#define AT91_PMC_FS_INPUT_MASK  0x7ff
+
 #define AT91_PMC_VERSION	0xfc
 
 #define AT91_PMC_PCER1		0x100			/* Peripheral Clock Enable Register 1 [SAMA5 only]*/
-- 
1.7.9.5

[PATCH v5 3/5] ARM: at91: pm: configure PMC fast startup signals

[Wenyou Yang]

The fast startup signal is used as wake up sources for ULP1 mode.
As soon as a fast startup signal is asserted, the embedded 12 MHz
RC oscillator restarts automatically.

This patch is to configure the fast startup signals, which signal
is enabled to trigger the PMC to wake up the system from ULP1 mode
should be configured via the DT.

Signed-off-by: Wenyou Yang <wenyou.yang-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org>
---

Changes in v5:
 - to improve the scalability, rework the DT expression part, use
   the child nodes to describe the wake-up input and its active level.

Changes in v4: None
Changes in v3:
 - use 0 and 1, not string, to define the trigger active polarity.

Changes in v2:
 - shorten the pmc-fast-startup property's name.
 - use the value property, instead of bool property for high
   or low triggered.

 arch/arm/mach-at91/pm.c      |   66 ++++++++++++++++++++++++++++++++++++++++++
 include/linux/clk/at91_pmc.h |   14 +++++++++
 2 files changed, 80 insertions(+)

diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index 5c2db34..29895f1 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -24,6 +24,8 @@
 #include <linux/platform_device.h>
 #include <linux/io.h>
 #include <linux/clk/at91_pmc.h>
+#include <linux/mfd/syscon.h>
+#include <linux/regmap.h>
 
 #include <asm/irq.h>
 #include <linux/atomic.h>
@@ -461,6 +463,68 @@ static void __init at91_pm_init(void (*pm_idle)(void))
 		pr_info("AT91: PM not supported, due to no SRAM allocated\n");
 }
 
+static int __init at91_pmc_fast_startup_init(void)
+{
+	struct device_node *np, *cnp;
+	struct regmap *regmap;
+	u32 input, input_mask;
+	u32 mode = 0, polarity = 0;
+
+	np = of_find_compatible_node(NULL, NULL,
+				     "atmel,sama5d2-pmc-fast-startup");
+	if (!np)
+		return -ENODEV;
+
+	regmap = syscon_node_to_regmap(of_get_parent(np));
+	if (IS_ERR(regmap)) {
+		pr_info("AT91: failed to find PMC fast startup node\n");
+		return PTR_ERR(regmap);
+	}
+
+	for_each_child_of_node(np, cnp) {
+		if (of_property_read_u32(cnp, "reg", &input)) {
+			pr_warn("AT91: reg property is missing for %s\n",
+				cnp->full_name);
+			continue;
+		}
+
+		input_mask = 1 << input;
+		if (!(input_mask & AT91_PMC_FS_INPUT_MASK)) {
+			pr_warn("AT91: wake-up input %d out of range\n", input);
+			continue;
+		}
+		mode |= input_mask;
+
+		if (of_property_read_bool(cnp, "atmel,wakeup-active-high"))
+			polarity |= input_mask;
+	}
+
+	if (of_property_read_bool(np, "atmel,wakeup-rtc-timer"))
+		mode |= AT91_PMC_RTCAL;
+
+	if (of_property_read_bool(np, "atmel,wakeup-usb-resume"))
+		mode |= AT91_PMC_USBAL;
+
+	if (of_property_read_bool(np, "atmel,wakeup-sdmmc-cd"))
+		mode |= AT91_PMC_SDMMC_CD;
+
+	if (of_property_read_bool(np, "atmel,wakeup-rxlp-match"))
+		mode |= AT91_PMC_RXLP_MCE;
+
+	if (of_property_read_bool(np, "atmel,wakeup-acc-comparison"))
+		mode |= AT91_PMC_ACC_CE;
+
+	pr_debug("AT91: mode = 0x%x, ploarity = 0%x\n", mode, polarity);
+
+	regmap_write(regmap, AT91_PMC_FSMR, mode);
+
+	regmap_write(regmap, AT91_PMC_FSPR, polarity);
+
+	of_node_put(np);
+
+	return 0;
+}
+
 void __init at91rm9200_pm_init(void)
 {
 	at91_dt_ramc();
@@ -509,4 +573,6 @@ void __init sama5_pm_init(void)
 
 	if (readl(pmc + AT91_PMC_VERSION) >= SAMA5D2_PMC_VERSION)
 		at91_pm_data.ulp_mode = ULP1_MODE;
+
+	at91_pmc_fast_startup_init();
 }
diff --git a/include/linux/clk/at91_pmc.h b/include/linux/clk/at91_pmc.h
index 4afd891..4b942c5 100644
--- a/include/linux/clk/at91_pmc.h
+++ b/include/linux/clk/at91_pmc.h
@@ -168,6 +168,20 @@
 #define		AT91_PMC_WPVS		(0x1  <<  0)		/* Write Protect Violation Status */
 #define		AT91_PMC_WPVSRC		(0xffff  <<  8)		/* Write Protect Violation Source */
 
+#define AT91_PMC_FSMR		0x70		/* Fast Startup Mode Register */
+#define AT91_PMC_FSTT(n)	(0x1 << n)
+#define AT91_PMC_RTCAL		BIT(17)		/* RTC Alarm Enable */
+#define AT91_PMC_USBAL		BIT(18)		/* USB Resume Enable */
+#define AT91_PMC_SDMMC_CD	BIT(19)		/* SDMMC Card Detect Enable */
+#define AT91_PMC_LPM		BIT(20)		/* Low-power Mode */
+#define AT91_PMC_RXLP_MCE	BIT(24)		/* Backup UART Receive Enable */
+#define AT91_PMC_ACC_CE		BIT(25)		/* ACC Enable */
+
+#define AT91_PMC_FSPR		0x74		/* Fast Startup Polarity Reg */
+#define AT91_PMC_FSTP(n)	(0x1 << n)
+
+#define AT91_PMC_FS_INPUT_MASK  0x7ff
+
 #define AT91_PMC_VERSION	0xfc
 
 #define AT91_PMC_PCER1		0x100			/* Peripheral Clock Enable Register 1 [SAMA5 only]*/
-- 
1.7.9.5

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[PATCH v5 4/5] Documentation: atmel-pmc: add DT bindings for fast startup

[Wenyou Yang]

Add DT bindings to configurate the PMC_FSMR and PMC_FSPR registers
to trigger a fast restart signal to PMC.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Acked-by: Rob Herring <robh+dt@kernel.org>
---

Changes in v5:
 - due to the DT property expression change, update the binding
   document.

Changes in v4:
 - add Acked-by tag.

Changes in v3:
 - update the property description.

Changes in v2:
 - change the property name and property description.

 .../devicetree/bindings/arm/atmel-pmc.txt          |   52 ++++++++++++++++++++
 1 file changed, 52 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/atmel-pmc.txt b/Documentation/devicetree/bindings/arm/atmel-pmc.txt
index 795cc78..76fdc66 100644
--- a/Documentation/devicetree/bindings/arm/atmel-pmc.txt
+++ b/Documentation/devicetree/bindings/arm/atmel-pmc.txt
@@ -12,3 +12,55 @@ Examples:
 		compatible = "atmel,at91rm9200-pmc";
 		reg = <0xfffffc00 0x100>;
 	};
+
+PMC Fast Startup Signals
+
+The PMC Fast Start Signals are used as the wake up source to trigger the PMC
+to wake up the system from the ULP1 mode.
+
+required properties:
+- compatible: should be "atmel,sama5d2-pmc-fast-startup".
+
+optional properties:
+- atmel,wakeup-rtc-timer: boolean to enable RTC alarm wake-up.
+- atmel,wakeup-usb-resume: boolean to enable USB resume wake-up.
+- atmel,wakeup-sdmmc-cd: boolean to enable SDMMC card detect wake-up.
+- atmel,wakeup-rxlp-match: boolean to enable RXLP matching condition wake-up.
+- atmel,wakeup-acc-comparison: boolean to enable ACC comparison wake-up.
+
+The node contains child nodes for each wake-up input pin that the platform uses.
+
+Input nodes
+
+Required properties:
+- reg: should contain the wake-up input index [0 - 10], to enable
+  the corresponding wake-up input.
+
+Optional properties:
+- atmel,wakeup-active-high: boolean to declare the corresponding wake-up
+  input described by the child be active high.
+  The default is to be active low.
+
+Example:
+
+	pmc: pmc@f0014000 {
+		compatible = "atmel,sama5d2-pmc";
+		reg = <0xf0014000 0x160>;
+
+		pmc_fast_restart {
+			compatible = "atmel,sama5d2-pmc-fast-startup";
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			atmel,wakeup-rtc-timer;
+
+			wkpin: input@0 {
+				reg = <0>;
+			};
+
+			gmac_wol: input@10 {
+				reg = <10>;
+				atmel,wakeup-active-high;
+			};
+		};
+	};
-- 
1.7.9.5

[PATCH v5 4/5] Documentation: atmel-pmc: add DT bindings for fast startup

[Wenyou Yang]

Add DT bindings to configurate the PMC_FSMR and PMC_FSPR registers
to trigger a fast restart signal to PMC.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Acked-by: Rob Herring <robh+dt@kernel.org>
---

Changes in v5:
 - due to the DT property expression change, update the binding
   document.

Changes in v4:
 - add Acked-by tag.

Changes in v3:
 - update the property description.

Changes in v2:
 - change the property name and property description.

 .../devicetree/bindings/arm/atmel-pmc.txt          |   52 ++++++++++++++++++++
 1 file changed, 52 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/atmel-pmc.txt b/Documentation/devicetree/bindings/arm/atmel-pmc.txt
index 795cc78..76fdc66 100644
--- a/Documentation/devicetree/bindings/arm/atmel-pmc.txt
+++ b/Documentation/devicetree/bindings/arm/atmel-pmc.txt
@@ -12,3 +12,55 @@ Examples:
 		compatible = "atmel,at91rm9200-pmc";
 		reg = <0xfffffc00 0x100>;
 	};
+
+PMC Fast Startup Signals
+
+The PMC Fast Start Signals are used as the wake up source to trigger the PMC
+to wake up the system from the ULP1 mode.
+
+required properties:
+- compatible: should be "atmel,sama5d2-pmc-fast-startup".
+
+optional properties:
+- atmel,wakeup-rtc-timer: boolean to enable RTC alarm wake-up.
+- atmel,wakeup-usb-resume: boolean to enable USB resume wake-up.
+- atmel,wakeup-sdmmc-cd: boolean to enable SDMMC card detect wake-up.
+- atmel,wakeup-rxlp-match: boolean to enable RXLP matching condition wake-up.
+- atmel,wakeup-acc-comparison: boolean to enable ACC comparison wake-up.
+
+The node contains child nodes for each wake-up input pin that the platform uses.
+
+Input nodes
+
+Required properties:
+- reg: should contain the wake-up input index [0 - 10], to enable
+  the corresponding wake-up input.
+
+Optional properties:
+- atmel,wakeup-active-high: boolean to declare the corresponding wake-up
+  input described by the child be active high.
+  The default is to be active low.
+
+Example:
+
+	pmc: pmc at f0014000 {
+		compatible = "atmel,sama5d2-pmc";
+		reg = <0xf0014000 0x160>;
+
+		pmc_fast_restart {
+			compatible = "atmel,sama5d2-pmc-fast-startup";
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			atmel,wakeup-rtc-timer;
+
+			wkpin: input at 0 {
+				reg = <0>;
+			};
+
+			gmac_wol: input at 10 {
+				reg = <10>;
+				atmel,wakeup-active-high;
+			};
+		};
+	};
-- 
1.7.9.5

[PATCH v5 4/5] Documentation: atmel-pmc: add DT bindings for fast startup

[Wenyou Yang]

Add DT bindings to configurate the PMC_FSMR and PMC_FSPR registers
to trigger a fast restart signal to PMC.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Acked-by: Rob Herring <robh+dt@kernel.org>
---

Changes in v5:
 - due to the DT property expression change, update the binding
   document.

Changes in v4:
 - add Acked-by tag.

Changes in v3:
 - update the property description.

Changes in v2:
 - change the property name and property description.

 .../devicetree/bindings/arm/atmel-pmc.txt          |   52 ++++++++++++++++++++
 1 file changed, 52 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/atmel-pmc.txt b/Documentation/devicetree/bindings/arm/atmel-pmc.txt
index 795cc78..76fdc66 100644
--- a/Documentation/devicetree/bindings/arm/atmel-pmc.txt
+++ b/Documentation/devicetree/bindings/arm/atmel-pmc.txt
@@ -12,3 +12,55 @@ Examples:
 		compatible = "atmel,at91rm9200-pmc";
 		reg = <0xfffffc00 0x100>;
 	};
+
+PMC Fast Startup Signals
+
+The PMC Fast Start Signals are used as the wake up source to trigger the PMC
+to wake up the system from the ULP1 mode.
+
+required properties:
+- compatible: should be "atmel,sama5d2-pmc-fast-startup".
+
+optional properties:
+- atmel,wakeup-rtc-timer: boolean to enable RTC alarm wake-up.
+- atmel,wakeup-usb-resume: boolean to enable USB resume wake-up.
+- atmel,wakeup-sdmmc-cd: boolean to enable SDMMC card detect wake-up.
+- atmel,wakeup-rxlp-match: boolean to enable RXLP matching condition wake-up.
+- atmel,wakeup-acc-comparison: boolean to enable ACC comparison wake-up.
+
+The node contains child nodes for each wake-up input pin that the platform uses.
+
+Input nodes
+
+Required properties:
+- reg: should contain the wake-up input index [0 - 10], to enable
+  the corresponding wake-up input.
+
+Optional properties:
+- atmel,wakeup-active-high: boolean to declare the corresponding wake-up
+  input described by the child be active high.
+  The default is to be active low.
+
+Example:
+
+	pmc: pmc@f0014000 {
+		compatible = "atmel,sama5d2-pmc";
+		reg = <0xf0014000 0x160>;
+
+		pmc_fast_restart {
+			compatible = "atmel,sama5d2-pmc-fast-startup";
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			atmel,wakeup-rtc-timer;
+
+			wkpin: input@0 {
+				reg = <0>;
+			};
+
+			gmac_wol: input@10 {
+				reg = <10>;
+				atmel,wakeup-active-high;
+			};
+		};
+	};
-- 
1.7.9.5

[PATCH v5 5/5] ARM: at91/dt: sama5d2_xplained: add fast_restart node

[Wenyou Yang]

Add fast_restart node as a pmc's child node to support fast startup
signal configuration.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
---

Changes in v5:
 - due to the DT property expression change, update the fast restart
   node's property.

Changes in v4:
 - add fast_restart node to the DT file.

Changes in v3: None
Changes in v2: None

 arch/arm/boot/dts/at91-sama5d2_xplained.dts |   19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/arch/arm/boot/dts/at91-sama5d2_xplained.dts b/arch/arm/boot/dts/at91-sama5d2_xplained.dts
index 21c780f..31df6e8 100644
--- a/arch/arm/boot/dts/at91-sama5d2_xplained.dts
+++ b/arch/arm/boot/dts/at91-sama5d2_xplained.dts
@@ -110,6 +110,25 @@
 		};
 
 		apb {
+			pmc: pmc@f0014000 {
+				pmc_fast_restart {
+					compatible = "atmel,sama5d2-pmc-fast-startup";
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					atmel,wakeup-rtc-timer;
+
+					wkpin: input@0 {
+						reg = <0>;
+					};
+
+					gmac_wol: input@10 {
+						reg = <10>;
+						atmel,wakeup-active-high;
+					};
+				};
+			};
+
 			spi0: spi@f8000000 {
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_spi0_default>;
-- 
1.7.9.5

[PATCH v5 5/5] ARM: at91/dt: sama5d2_xplained: add fast_restart node

[Wenyou Yang]

Add fast_restart node as a pmc's child node to support fast startup
signal configuration.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
---

Changes in v5:
 - due to the DT property expression change, update the fast restart
   node's property.

Changes in v4:
 - add fast_restart node to the DT file.

Changes in v3: None
Changes in v2: None

 arch/arm/boot/dts/at91-sama5d2_xplained.dts |   19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/arch/arm/boot/dts/at91-sama5d2_xplained.dts b/arch/arm/boot/dts/at91-sama5d2_xplained.dts
index 21c780f..31df6e8 100644
--- a/arch/arm/boot/dts/at91-sama5d2_xplained.dts
+++ b/arch/arm/boot/dts/at91-sama5d2_xplained.dts
@@ -110,6 +110,25 @@
 		};
 
 		apb {
+			pmc: pmc at f0014000 {
+				pmc_fast_restart {
+					compatible = "atmel,sama5d2-pmc-fast-startup";
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					atmel,wakeup-rtc-timer;
+
+					wkpin: input at 0 {
+						reg = <0>;
+					};
+
+					gmac_wol: input at 10 {
+						reg = <10>;
+						atmel,wakeup-active-high;
+					};
+				};
+			};
+
 			spi0: spi at f8000000 {
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_spi0_default>;
-- 
1.7.9.5

[PATCH v5 5/5] ARM: at91/dt: sama5d2_xplained: add fast_restart node

[Wenyou Yang]

Add fast_restart node as a pmc's child node to support fast startup
signal configuration.

Signed-off-by: Wenyou Yang <wenyou.yang-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org>
---

Changes in v5:
 - due to the DT property expression change, update the fast restart
   node's property.

Changes in v4:
 - add fast_restart node to the DT file.

Changes in v3: None
Changes in v2: None

 arch/arm/boot/dts/at91-sama5d2_xplained.dts |   19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/arch/arm/boot/dts/at91-sama5d2_xplained.dts b/arch/arm/boot/dts/at91-sama5d2_xplained.dts
index 21c780f..31df6e8 100644
--- a/arch/arm/boot/dts/at91-sama5d2_xplained.dts
+++ b/arch/arm/boot/dts/at91-sama5d2_xplained.dts
@@ -110,6 +110,25 @@
 		};
 
 		apb {
+			pmc: pmc@f0014000 {
+				pmc_fast_restart {
+					compatible = "atmel,sama5d2-pmc-fast-startup";
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					atmel,wakeup-rtc-timer;
+
+					wkpin: input@0 {
+						reg = <0>;
+					};
+
+					gmac_wol: input@10 {
+						reg = <10>;
+						atmel,wakeup-active-high;
+					};
+				};
+			};
+
 			spi0: spi@f8000000 {
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_spi0_default>;
-- 
1.7.9.5

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Re: [PATCH v5 1/5] ARM: at91: pm: create a separate procedure for the ULP0 mode

[Alexandre Belloni]

On 16/03/2016 at 14:58:05 +0800, Wenyou Yang wrote :
> To make the code more legible and prepare to add the ULP1 mode
> support in the future, create a separate procedure for the ULP0 mode.
> 
> Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>

> ---
> 
> Changes in v5: None
> Changes in v4: None
> Changes in v3: None
> Changes in v2: None
> 
>  arch/arm/mach-at91/pm_suspend.S |   65 ++++++++++++++++++++++++---------------
>  1 file changed, 40 insertions(+), 25 deletions(-)
> 
> diff --git a/arch/arm/mach-at91/pm_suspend.S b/arch/arm/mach-at91/pm_suspend.S
> index a25defd..5fcffdc 100644
> --- a/arch/arm/mach-at91/pm_suspend.S
> +++ b/arch/arm/mach-at91/pm_suspend.S
> @@ -107,7 +107,7 @@ ENTRY(at91_pm_suspend_in_sram)
>  
>  	ldr	r0, .pm_mode
>  	tst	r0, #AT91_PM_SLOW_CLOCK
> -	beq	skip_disable_main_clock
> +	beq	standby_mode
>  
>  	ldr	pmc, .pmc_base
>  
> @@ -131,32 +131,13 @@ ENTRY(at91_pm_suspend_in_sram)
>  	orr	tmp1, tmp1, #(1 << 29)		/* bit 29 always set */
>  	str	tmp1, [pmc, #AT91_CKGR_PLLAR]
>  
> -	/* Turn off the main oscillator */
> -	ldr	tmp1, [pmc, #AT91_CKGR_MOR]
> -	bic	tmp1, tmp1, #AT91_PMC_MOSCEN
> -	orr	tmp1, tmp1, #AT91_PMC_KEY
> -	str	tmp1, [pmc, #AT91_CKGR_MOR]
> -
> -skip_disable_main_clock:
> -	ldr	pmc, .pmc_base
> -
> -	/* Wait for interrupt */
> -	at91_cpu_idle
> -
> -	ldr	r0, .pm_mode
> -	tst	r0, #AT91_PM_SLOW_CLOCK
> -	beq	skip_enable_main_clock
> +ulp0_mode:
> +	bl	at91_pm_ulp0_mode
> +	b	ulp_exit
>  
> +ulp_exit:
>  	ldr	pmc, .pmc_base
>  
> -	/* Turn on the main oscillator */
> -	ldr	tmp1, [pmc, #AT91_CKGR_MOR]
> -	orr	tmp1, tmp1, #AT91_PMC_MOSCEN
> -	orr	tmp1, tmp1, #AT91_PMC_KEY
> -	str	tmp1, [pmc, #AT91_CKGR_MOR]
> -
> -	wait_moscrdy
> -
>  	/* Restore PLLA setting */
>  	ldr	tmp1, .saved_pllar
>  	str	tmp1, [pmc, #AT91_CKGR_PLLAR]
> @@ -177,7 +158,15 @@ skip_disable_main_clock:
>  
>  	wait_mckrdy
>  
> -skip_enable_main_clock:
> +	b	pm_exit
> +
> +standby_mode:
> +	ldr	pmc, .pmc_base
> +
> +	/* Wait for interrupt */
> +	at91_cpu_idle
> +
> +pm_exit:
>  	/* Exit the self-refresh mode */
>  	mov	r0, #SRAMC_SELF_FRESH_EXIT
>  	bl	at91_sramc_self_refresh
> @@ -311,6 +300,32 @@ exit_sramc_sf:
>  	mov	pc, lr
>  ENDPROC(at91_sramc_self_refresh)
>  
> +/*
> + * void at91_pm_ulp0_mode(void)
> + */
> +ENTRY(at91_pm_ulp0_mode)
> +	ldr	pmc, .pmc_base
> +
> +	/* Turn off the crystal oscillator */
> +	ldr	tmp1, [pmc, #AT91_CKGR_MOR]
> +	bic	tmp1, tmp1, #AT91_PMC_MOSCEN
> +	orr	tmp1, tmp1, #AT91_PMC_KEY
> +	str	tmp1, [pmc, #AT91_CKGR_MOR]
> +
> +	/* Wait for interrupt */
> +	at91_cpu_idle
> +
> +	/* Turn on the crystal oscillator */
> +	ldr	tmp1, [pmc, #AT91_CKGR_MOR]
> +	orr	tmp1, tmp1, #AT91_PMC_MOSCEN
> +	orr	tmp1, tmp1, #AT91_PMC_KEY
> +	str	tmp1, [pmc, #AT91_CKGR_MOR]
> +
> +	wait_moscrdy
> +
> +	mov	pc, lr
> +ENDPROC(at91_pm_ulp0_mode)
> +
>  .pmc_base:
>  	.word 0
>  .sramc_base:
> -- 
> 1.7.9.5
> 

-- 
Alexandre Belloni, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

[PATCH v5 1/5] ARM: at91: pm: create a separate procedure for the ULP0 mode

[Alexandre Belloni]

On 16/03/2016 at 14:58:05 +0800, Wenyou Yang wrote :
> To make the code more legible and prepare to add the ULP1 mode
> support in the future, create a separate procedure for the ULP0 mode.
> 
> Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>

> ---
> 
> Changes in v5: None
> Changes in v4: None
> Changes in v3: None
> Changes in v2: None
> 
>  arch/arm/mach-at91/pm_suspend.S |   65 ++++++++++++++++++++++++---------------
>  1 file changed, 40 insertions(+), 25 deletions(-)
> 
> diff --git a/arch/arm/mach-at91/pm_suspend.S b/arch/arm/mach-at91/pm_suspend.S
> index a25defd..5fcffdc 100644
> --- a/arch/arm/mach-at91/pm_suspend.S
> +++ b/arch/arm/mach-at91/pm_suspend.S
> @@ -107,7 +107,7 @@ ENTRY(at91_pm_suspend_in_sram)
>  
>  	ldr	r0, .pm_mode
>  	tst	r0, #AT91_PM_SLOW_CLOCK
> -	beq	skip_disable_main_clock
> +	beq	standby_mode
>  
>  	ldr	pmc, .pmc_base
>  
> @@ -131,32 +131,13 @@ ENTRY(at91_pm_suspend_in_sram)
>  	orr	tmp1, tmp1, #(1 << 29)		/* bit 29 always set */
>  	str	tmp1, [pmc, #AT91_CKGR_PLLAR]
>  
> -	/* Turn off the main oscillator */
> -	ldr	tmp1, [pmc, #AT91_CKGR_MOR]
> -	bic	tmp1, tmp1, #AT91_PMC_MOSCEN
> -	orr	tmp1, tmp1, #AT91_PMC_KEY
> -	str	tmp1, [pmc, #AT91_CKGR_MOR]
> -
> -skip_disable_main_clock:
> -	ldr	pmc, .pmc_base
> -
> -	/* Wait for interrupt */
> -	at91_cpu_idle
> -
> -	ldr	r0, .pm_mode
> -	tst	r0, #AT91_PM_SLOW_CLOCK
> -	beq	skip_enable_main_clock
> +ulp0_mode:
> +	bl	at91_pm_ulp0_mode
> +	b	ulp_exit
>  
> +ulp_exit:
>  	ldr	pmc, .pmc_base
>  
> -	/* Turn on the main oscillator */
> -	ldr	tmp1, [pmc, #AT91_CKGR_MOR]
> -	orr	tmp1, tmp1, #AT91_PMC_MOSCEN
> -	orr	tmp1, tmp1, #AT91_PMC_KEY
> -	str	tmp1, [pmc, #AT91_CKGR_MOR]
> -
> -	wait_moscrdy
> -
>  	/* Restore PLLA setting */
>  	ldr	tmp1, .saved_pllar
>  	str	tmp1, [pmc, #AT91_CKGR_PLLAR]
> @@ -177,7 +158,15 @@ skip_disable_main_clock:
>  
>  	wait_mckrdy
>  
> -skip_enable_main_clock:
> +	b	pm_exit
> +
> +standby_mode:
> +	ldr	pmc, .pmc_base
> +
> +	/* Wait for interrupt */
> +	at91_cpu_idle
> +
> +pm_exit:
>  	/* Exit the self-refresh mode */
>  	mov	r0, #SRAMC_SELF_FRESH_EXIT
>  	bl	at91_sramc_self_refresh
> @@ -311,6 +300,32 @@ exit_sramc_sf:
>  	mov	pc, lr
>  ENDPROC(at91_sramc_self_refresh)
>  
> +/*
> + * void at91_pm_ulp0_mode(void)
> + */
> +ENTRY(at91_pm_ulp0_mode)
> +	ldr	pmc, .pmc_base
> +
> +	/* Turn off the crystal oscillator */
> +	ldr	tmp1, [pmc, #AT91_CKGR_MOR]
> +	bic	tmp1, tmp1, #AT91_PMC_MOSCEN
> +	orr	tmp1, tmp1, #AT91_PMC_KEY
> +	str	tmp1, [pmc, #AT91_CKGR_MOR]
> +
> +	/* Wait for interrupt */
> +	at91_cpu_idle
> +
> +	/* Turn on the crystal oscillator */
> +	ldr	tmp1, [pmc, #AT91_CKGR_MOR]
> +	orr	tmp1, tmp1, #AT91_PMC_MOSCEN
> +	orr	tmp1, tmp1, #AT91_PMC_KEY
> +	str	tmp1, [pmc, #AT91_CKGR_MOR]
> +
> +	wait_moscrdy
> +
> +	mov	pc, lr
> +ENDPROC(at91_pm_ulp0_mode)
> +
>  .pmc_base:
>  	.word 0
>  .sramc_base:
> -- 
> 1.7.9.5
> 

-- 
Alexandre Belloni, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

Re: [PATCH v5 2/5] ARM: at91: pm: add ULP1 mode support

[Alexandre Belloni]

On 16/03/2016 at 14:58:06 +0800, Wenyou Yang wrote :
> @@ -497,4 +506,7 @@ void __init sama5_pm_init(void)
>  	at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP;
>  	at91_pm_data.memctrl = AT91_MEMCTRL_DDRSDR;
>  	at91_pm_init(NULL);
> +
> +	if (readl(pmc + AT91_PMC_VERSION) >= SAMA5D2_PMC_VERSION)

I would not use that. Instead, I would create a new function,
sama5d2_pm_init() and call it from sama5.c with a new
sama5d2_dt_device_init and a new DT_MACHINE.

> +		at91_pm_data.ulp_mode = ULP1_MODE;
>  }
> diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h
> index 3fcf881..2e76745 100644
> --- a/arch/arm/mach-at91/pm.h
> +++ b/arch/arm/mach-at91/pm.h
> @@ -39,4 +39,11 @@ extern void __iomem *at91_ramc_base[];
>  
>  #define	AT91_PM_SLOW_CLOCK	0x01
>  
> +#define AT91_PM_ULP_OFFSET	5
> +#define AT91_PM_ULP_MASK	0x03
> +#define AT91_PM_ULP(x)		(((x) & AT91_PM_ULP_MASK) << AT91_PM_ULP_OFFSET)
> +
> +#define AT91_PM_ULP0_MODE	0x00
> +#define AT91_PM_ULP1_MODE	0x01
> +
>  #endif
> diff --git a/arch/arm/mach-at91/pm_suspend.S b/arch/arm/mach-at91/pm_suspend.S
> index 5fcffdc..f2a5c4b 100644
> --- a/arch/arm/mach-at91/pm_suspend.S
> +++ b/arch/arm/mach-at91/pm_suspend.S
> @@ -41,6 +41,15 @@ tmp2	.req	r5
>  	.endm
>  
>  /*
> + * Wait for main oscillator selection is done
> + */
> +	.macro wait_moscsels
> +1:	ldr	tmp1, [pmc, #AT91_PMC_SR]
> +	tst	tmp1, #AT91_PMC_MOSCSELS
> +	beq	1b
> +	.endm
> +
> +/*
>   * Wait until PLLA has locked.
>   */
>  	.macro wait_pllalock
> @@ -101,6 +110,10 @@ ENTRY(at91_pm_suspend_in_sram)
>  	and	r0, r0, #AT91_PM_MODE_MASK
>  	str	r0, .pm_mode
>  
> +	lsr	r0, r3, #AT91_PM_ULP_OFFSET
> +	and	r0, r0, #AT91_PM_ULP_MASK
> +	str	r0, .ulp_mode
> +
>  	/* Active the self-refresh mode */
>  	mov	r0, #SRAMC_SELF_FRESH_ACTIVE
>  	bl	at91_sramc_self_refresh
> @@ -131,6 +144,13 @@ ENTRY(at91_pm_suspend_in_sram)
>  	orr	tmp1, tmp1, #(1 << 29)		/* bit 29 always set */
>  	str	tmp1, [pmc, #AT91_CKGR_PLLAR]
>  
> +	ldr	r0, .ulp_mode
> +	tst	r0, #AT91_PM_ULP1_MODE
> +	beq	ulp0_mode
> +
> +	bl	at91_pm_ulp1_mode
> +	b	ulp_exit
> +
>  ulp0_mode:
>  	bl	at91_pm_ulp0_mode
>  	b	ulp_exit
> @@ -326,6 +346,81 @@ ENTRY(at91_pm_ulp0_mode)
>  	mov	pc, lr
>  ENDPROC(at91_pm_ulp0_mode)
>  
> +/*
> + * void at91_pm_ulp1_mode(void)
> + */
> +ENTRY(at91_pm_ulp1_mode)
> +	ldr	pmc, .pmc_base
> +
> +	/* Switch the main clock source to 12-MHz RC oscillator */
> +	ldr	tmp1, [pmc, #AT91_CKGR_MOR]
> +	bic	tmp1, tmp1, #AT91_PMC_MOSCSEL
> +	bic	tmp1, tmp1, #AT91_PMC_KEY_MASK
> +	orr	tmp1, tmp1, #AT91_PMC_KEY
> +	str	tmp1, [pmc, #AT91_CKGR_MOR]
> +
> +	wait_moscsels
> +
> +	/* Disable the crystal oscillator */
> +	ldr	tmp1, [pmc, #AT91_CKGR_MOR]
> +	bic	tmp1, tmp1, #AT91_PMC_MOSCEN
> +	bic	tmp1, tmp1, #AT91_PMC_KEY_MASK
> +	orr	tmp1, tmp1, #AT91_PMC_KEY
> +	str	tmp1, [pmc, #AT91_CKGR_MOR]
> +
> +	/* Switch the master clock source to main clock */
> +	ldr	tmp1, [pmc, #AT91_PMC_MCKR]
> +	bic	tmp1, tmp1, #AT91_PMC_CSS
> +	orr	tmp1, tmp1, #AT91_PMC_CSS_MAIN
> +	str	tmp1, [pmc, #AT91_PMC_MCKR]
> +
> +	wait_mckrdy
> +
> +	/* Enter the ULP1 mode by set WAITMODE bit in CKGR_MOR */
> +	ldr	tmp1, [pmc, #AT91_CKGR_MOR]
> +	orr	tmp1, tmp1, #AT91_PMC_WAITMODE
> +	bic	tmp1, tmp1, #AT91_PMC_KEY_MASK
> +	orr	tmp1, tmp1, #AT91_PMC_KEY
> +	str	tmp1, [pmc, #AT91_CKGR_MOR]
> +
> +	wait_mckrdy
> +
> +	/* Enable the crystal oscillator */
> +	ldr	tmp1, [pmc, #AT91_CKGR_MOR]
> +	orr	tmp1, tmp1, #AT91_PMC_MOSCEN
> +	bic	tmp1, tmp1, #AT91_PMC_KEY_MASK
> +	orr	tmp1, tmp1, #AT91_PMC_KEY
> +	str	tmp1, [pmc, #AT91_CKGR_MOR]
> +

This will badly fail on the platforms that don't populate a crystal for
the main clock or use the bypass. I think wee need to have at least a
comment or save the previous state and restore it.


-- 
Alexandre Belloni, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

[PATCH v5 2/5] ARM: at91: pm: add ULP1 mode support

[Alexandre Belloni]

On 16/03/2016 at 14:58:06 +0800, Wenyou Yang wrote :
> @@ -497,4 +506,7 @@ void __init sama5_pm_init(void)
>  	at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP;
>  	at91_pm_data.memctrl = AT91_MEMCTRL_DDRSDR;
>  	at91_pm_init(NULL);
> +
> +	if (readl(pmc + AT91_PMC_VERSION) >= SAMA5D2_PMC_VERSION)

I would not use that. Instead, I would create a new function,
sama5d2_pm_init() and call it from sama5.c with a new
sama5d2_dt_device_init and a new DT_MACHINE.

> +		at91_pm_data.ulp_mode = ULP1_MODE;
>  }
> diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h
> index 3fcf881..2e76745 100644
> --- a/arch/arm/mach-at91/pm.h
> +++ b/arch/arm/mach-at91/pm.h
> @@ -39,4 +39,11 @@ extern void __iomem *at91_ramc_base[];
>  
>  #define	AT91_PM_SLOW_CLOCK	0x01
>  
> +#define AT91_PM_ULP_OFFSET	5
> +#define AT91_PM_ULP_MASK	0x03
> +#define AT91_PM_ULP(x)		(((x) & AT91_PM_ULP_MASK) << AT91_PM_ULP_OFFSET)
> +
> +#define AT91_PM_ULP0_MODE	0x00
> +#define AT91_PM_ULP1_MODE	0x01
> +
>  #endif
> diff --git a/arch/arm/mach-at91/pm_suspend.S b/arch/arm/mach-at91/pm_suspend.S
> index 5fcffdc..f2a5c4b 100644
> --- a/arch/arm/mach-at91/pm_suspend.S
> +++ b/arch/arm/mach-at91/pm_suspend.S
> @@ -41,6 +41,15 @@ tmp2	.req	r5
>  	.endm
>  
>  /*
> + * Wait for main oscillator selection is done
> + */
> +	.macro wait_moscsels
> +1:	ldr	tmp1, [pmc, #AT91_PMC_SR]
> +	tst	tmp1, #AT91_PMC_MOSCSELS
> +	beq	1b
> +	.endm
> +
> +/*
>   * Wait until PLLA has locked.
>   */
>  	.macro wait_pllalock
> @@ -101,6 +110,10 @@ ENTRY(at91_pm_suspend_in_sram)
>  	and	r0, r0, #AT91_PM_MODE_MASK
>  	str	r0, .pm_mode
>  
> +	lsr	r0, r3, #AT91_PM_ULP_OFFSET
> +	and	r0, r0, #AT91_PM_ULP_MASK
> +	str	r0, .ulp_mode
> +
>  	/* Active the self-refresh mode */
>  	mov	r0, #SRAMC_SELF_FRESH_ACTIVE
>  	bl	at91_sramc_self_refresh
> @@ -131,6 +144,13 @@ ENTRY(at91_pm_suspend_in_sram)
>  	orr	tmp1, tmp1, #(1 << 29)		/* bit 29 always set */
>  	str	tmp1, [pmc, #AT91_CKGR_PLLAR]
>  
> +	ldr	r0, .ulp_mode
> +	tst	r0, #AT91_PM_ULP1_MODE
> +	beq	ulp0_mode
> +
> +	bl	at91_pm_ulp1_mode
> +	b	ulp_exit
> +
>  ulp0_mode:
>  	bl	at91_pm_ulp0_mode
>  	b	ulp_exit
> @@ -326,6 +346,81 @@ ENTRY(at91_pm_ulp0_mode)
>  	mov	pc, lr
>  ENDPROC(at91_pm_ulp0_mode)
>  
> +/*
> + * void at91_pm_ulp1_mode(void)
> + */
> +ENTRY(at91_pm_ulp1_mode)
> +	ldr	pmc, .pmc_base
> +
> +	/* Switch the main clock source to 12-MHz RC oscillator */
> +	ldr	tmp1, [pmc, #AT91_CKGR_MOR]
> +	bic	tmp1, tmp1, #AT91_PMC_MOSCSEL
> +	bic	tmp1, tmp1, #AT91_PMC_KEY_MASK
> +	orr	tmp1, tmp1, #AT91_PMC_KEY
> +	str	tmp1, [pmc, #AT91_CKGR_MOR]
> +
> +	wait_moscsels
> +
> +	/* Disable the crystal oscillator */
> +	ldr	tmp1, [pmc, #AT91_CKGR_MOR]
> +	bic	tmp1, tmp1, #AT91_PMC_MOSCEN
> +	bic	tmp1, tmp1, #AT91_PMC_KEY_MASK
> +	orr	tmp1, tmp1, #AT91_PMC_KEY
> +	str	tmp1, [pmc, #AT91_CKGR_MOR]
> +
> +	/* Switch the master clock source to main clock */
> +	ldr	tmp1, [pmc, #AT91_PMC_MCKR]
> +	bic	tmp1, tmp1, #AT91_PMC_CSS
> +	orr	tmp1, tmp1, #AT91_PMC_CSS_MAIN
> +	str	tmp1, [pmc, #AT91_PMC_MCKR]
> +
> +	wait_mckrdy
> +
> +	/* Enter the ULP1 mode by set WAITMODE bit in CKGR_MOR */
> +	ldr	tmp1, [pmc, #AT91_CKGR_MOR]
> +	orr	tmp1, tmp1, #AT91_PMC_WAITMODE
> +	bic	tmp1, tmp1, #AT91_PMC_KEY_MASK
> +	orr	tmp1, tmp1, #AT91_PMC_KEY
> +	str	tmp1, [pmc, #AT91_CKGR_MOR]
> +
> +	wait_mckrdy
> +
> +	/* Enable the crystal oscillator */
> +	ldr	tmp1, [pmc, #AT91_CKGR_MOR]
> +	orr	tmp1, tmp1, #AT91_PMC_MOSCEN
> +	bic	tmp1, tmp1, #AT91_PMC_KEY_MASK
> +	orr	tmp1, tmp1, #AT91_PMC_KEY
> +	str	tmp1, [pmc, #AT91_CKGR_MOR]
> +

This will badly fail on the platforms that don't populate a crystal for
the main clock or use the bypass. I think wee need to have at least a
comment or save the previous state and restore it.


-- 
Alexandre Belloni, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

Re: [PATCH v5 3/5] ARM: at91: pm: configure PMC fast startup signals

[Alexandre Belloni]

On 16/03/2016 at 14:58:07 +0800, Wenyou Yang wrote :
> The fast startup signal is used as wake up sources for ULP1 mode.
> As soon as a fast startup signal is asserted, the embedded 12 MHz
> RC oscillator restarts automatically.
> 
> This patch is to configure the fast startup signals, which signal
> is enabled to trigger the PMC to wake up the system from ULP1 mode
> should be configured via the DT.
> 
> Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>

I would actually avoid doing that from the PMC driver and do that
configuration from the aic5 driver. It has all the information you need,
it knows what kind of level or edge is needed to wake up and what are
the wakeup interrupts to enable. This will allow you to stop introducing
a new binding. Also, this will avoid discrepancies between what is
configured in the DT and what the user really wants (for exemple
differences between the edge direction configured for the PIOBu in
userspace versus what is in the device tree or wakeonlan
activation/deactivation).

You can get the PMC syscon from irq-atmel-aic5.c and then use a table to
map the hwirq to the offset in PMC_FSMR. Use it in aic5_set_type to set
the polarity and then in aic5_suspend to enable the wakeup.

Maybe we could even go further and avoid ulp1 if no ulp1 compatbile
wakeup sources are defined but there are ulp0 wakeup sources.


-- 
Alexandre Belloni, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

[PATCH v5 3/5] ARM: at91: pm: configure PMC fast startup signals

[Alexandre Belloni]

On 16/03/2016 at 14:58:07 +0800, Wenyou Yang wrote :
> The fast startup signal is used as wake up sources for ULP1 mode.
> As soon as a fast startup signal is asserted, the embedded 12 MHz
> RC oscillator restarts automatically.
> 
> This patch is to configure the fast startup signals, which signal
> is enabled to trigger the PMC to wake up the system from ULP1 mode
> should be configured via the DT.
> 
> Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>

I would actually avoid doing that from the PMC driver and do that
configuration from the aic5 driver. It has all the information you need,
it knows what kind of level or edge is needed to wake up and what are
the wakeup interrupts to enable. This will allow you to stop introducing
a new binding. Also, this will avoid discrepancies between what is
configured in the DT and what the user really wants (for exemple
differences between the edge direction configured for the PIOBu in
userspace versus what is in the device tree or wakeonlan
activation/deactivation).

You can get the PMC syscon from irq-atmel-aic5.c and then use a table to
map the hwirq to the offset in PMC_FSMR. Use it in aic5_set_type to set
the polarity and then in aic5_suspend to enable the wakeup.

Maybe we could even go further and avoid ulp1 if no ulp1 compatbile
wakeup sources are defined but there are ulp0 wakeup sources.


-- 
Alexandre Belloni, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

RE: [PATCH v5 3/5] ARM: at91: pm: configure PMC fast startup signals

[Yang, Wenyou]

SGkgQWxleGFuZHJlLA0KDQo+IC0tLS0tT3JpZ2luYWwgTWVzc2FnZS0tLS0tDQo+IEZyb206IEFs
ZXhhbmRyZSBCZWxsb25pIFttYWlsdG86YWxleGFuZHJlLmJlbGxvbmlAZnJlZS1lbGVjdHJvbnMu
Y29tXQ0KPiBTZW50OiAyMDE2xOoz1MIxOMjVIDE6MTUNCj4gVG86IFlhbmcsIFdlbnlvdSA8V2Vu
eW91LllhbmdAYXRtZWwuY29tPg0KPiBDYzogRmVycmUsIE5pY29sYXMgPE5pY29sYXMuRkVSUkVA
YXRtZWwuY29tPjsgSmVhbi1DaHJpc3RvcGhlIFBsYWduaW9sLQ0KPiBWaWxsYXJkIDxwbGFnbmlv
akBqY3Jvc29mdC5jb20+OyBSdXNzZWxsIEtpbmcgPGxpbnV4QGFybS5saW51eC5vcmcudWs+OyBs
aW51eC0NCj4ga2VybmVsQHZnZXIua2VybmVsLm9yZzsgZGV2aWNldHJlZUB2Z2VyLmtlcm5lbC5v
cmc7IGxpbnV4LWFybS0NCj4ga2VybmVsQGxpc3RzLmluZnJhZGVhZC5vcmc7IGxpbnV4LWNsa0B2
Z2VyLmtlcm5lbC5vcmc7IFJvYiBIZXJyaW5nDQo+IDxyb2JoK2R0QGtlcm5lbC5vcmc+OyBQYXdl
bCBNb2xsIDxwYXdlbC5tb2xsQGFybS5jb20+OyBNYXJrIEJyb3duDQo+IDxicm9vbmllQGtlcm5l
bC5vcmc+OyBJYW4gQ2FtcGJlbGwgPGlqYytkZXZpY2V0cmVlQGhlbGxpb24ub3JnLnVrPjsgS3Vt
YXINCj4gR2FsYSA8Z2FsYWtAY29kZWF1cm9yYS5vcmc+DQo+IFN1YmplY3Q6IFJlOiBbUEFUQ0gg
djUgMy81XSBBUk06IGF0OTE6IHBtOiBjb25maWd1cmUgUE1DIGZhc3Qgc3RhcnR1cCBzaWduYWxz
DQo+IA0KPiBPbiAxNi8wMy8yMDE2IGF0IDE0OjU4OjA3ICswODAwLCBXZW55b3UgWWFuZyB3cm90
ZSA6DQo+ID4gVGhlIGZhc3Qgc3RhcnR1cCBzaWduYWwgaXMgdXNlZCBhcyB3YWtlIHVwIHNvdXJj
ZXMgZm9yIFVMUDEgbW9kZS4NCj4gPiBBcyBzb29uIGFzIGEgZmFzdCBzdGFydHVwIHNpZ25hbCBp
cyBhc3NlcnRlZCwgdGhlIGVtYmVkZGVkIDEyIE1IeiBSQw0KPiA+IG9zY2lsbGF0b3IgcmVzdGFy
dHMgYXV0b21hdGljYWxseS4NCj4gPg0KPiA+IFRoaXMgcGF0Y2ggaXMgdG8gY29uZmlndXJlIHRo
ZSBmYXN0IHN0YXJ0dXAgc2lnbmFscywgd2hpY2ggc2lnbmFsIGlzDQo+ID4gZW5hYmxlZCB0byB0
cmlnZ2VyIHRoZSBQTUMgdG8gd2FrZSB1cCB0aGUgc3lzdGVtIGZyb20gVUxQMSBtb2RlIHNob3Vs
ZA0KPiA+IGJlIGNvbmZpZ3VyZWQgdmlhIHRoZSBEVC4NCj4gPg0KPiA+IFNpZ25lZC1vZmYtYnk6
IFdlbnlvdSBZYW5nIDx3ZW55b3UueWFuZ0BhdG1lbC5jb20+DQo+IA0KPiBJIHdvdWxkIGFjdHVh
bGx5IGF2b2lkIGRvaW5nIHRoYXQgZnJvbSB0aGUgUE1DIGRyaXZlciBhbmQgZG8gdGhhdCBjb25m
aWd1cmF0aW9uDQo+IGZyb20gdGhlIGFpYzUgZHJpdmVyLiBJdCBoYXMgYWxsIHRoZSBpbmZvcm1h
dGlvbiB5b3UgbmVlZCwgaXQga25vd3Mgd2hhdCBraW5kIG9mIGxldmVsDQo+IG9yIGVkZ2UgaXMg
bmVlZGVkIHRvIHdha2UgdXAgYW5kIHdoYXQgYXJlIHRoZSB3YWtldXAgaW50ZXJydXB0cyB0byBl
bmFibGUuIFRoaXMNCj4gd2lsbCBhbGxvdyB5b3UgdG8gc3RvcCBpbnRyb2R1Y2luZyBhIG5ldyBi
aW5kaW5nLiBBbHNvLCB0aGlzIHdpbGwgYXZvaWQgZGlzY3JlcGFuY2llcw0KPiBiZXR3ZWVuIHdo
YXQgaXMgY29uZmlndXJlZCBpbiB0aGUgRFQgYW5kIHdoYXQgdGhlIHVzZXIgcmVhbGx5IHdhbnRz
IChmb3IgZXhlbXBsZQ0KPiBkaWZmZXJlbmNlcyBiZXR3ZWVuIHRoZSBlZGdlIGRpcmVjdGlvbiBj
b25maWd1cmVkIGZvciB0aGUgUElPQnUgaW4gdXNlcnNwYWNlDQo+IHZlcnN1cyB3aGF0IGlzIGlu
IHRoZSBkZXZpY2UgdHJlZSBvciB3YWtlb25sYW4gYWN0aXZhdGlvbi9kZWFjdGl2YXRpb24pLg0K
DQpUaGFuayB5b3UgZm9yIHlvdXIgZmVlZGJhY2suDQoNCkJ1dCBzb21lIHdha2UtdXBzIHN1Y2gg
YXMgV0tVUCBwaW4sIEFDQ19DRSwgUlhMUF9NQ0UsIGRvbid0IGhhdmUgdGhlIGNvcnJlc3BvbmRp
bmcNCmludGVycnVwdCBudW1iZXIuIE1vcmVvdmVyLCBJIHRoaW5rLCB0aGUgVUxQMSBpcyB2ZXJ5
IGRpZmZlcmVudCBmb3JtIHRoZSBVTFAwLCBpdCBpcyBub3Qgd29rZW4NCnVwIGJ5IHRoZSBpbnRl
cnJ1cHQuIEl0IGlzIGZhbGxlbiBzbGVlcCBhbmQgd29rZW4gdXAgYnkgdGhlIHNvbWUgbWVjaGFu
aXNtIGluIHRoZSBQTUMuIA0KDQpNYXliZSBJIHdhcyB3cm9uZy4gSSBzdGlsbCB0aGluayB0aGUg
YWljNSBkcml2ZXIgc2hvdWxkIGJlIGRldm90ZWQgb24gdGhlIEFJQzUncyBiZWhhdmlvcnMuIA0K
DQo+IA0KPiBZb3UgY2FuIGdldCB0aGUgUE1DIHN5c2NvbiBmcm9tIGlycS1hdG1lbC1haWM1LmMg
YW5kIHRoZW4gdXNlIGEgdGFibGUgdG8gbWFwDQo+IHRoZSBod2lycSB0byB0aGUgb2Zmc2V0IGlu
IFBNQ19GU01SLiBVc2UgaXQgaW4gYWljNV9zZXRfdHlwZSB0byBzZXQgdGhlIHBvbGFyaXR5DQo+
IGFuZCB0aGVuIGluIGFpYzVfc3VzcGVuZCB0byBlbmFibGUgdGhlIHdha2V1cC4NCj4gDQo+IE1h
eWJlIHdlIGNvdWxkIGV2ZW4gZ28gZnVydGhlciBhbmQgYXZvaWQgdWxwMSBpZiBubyB1bHAxIGNv
bXBhdGJpbGUgd2FrZXVwDQo+IHNvdXJjZXMgYXJlIGRlZmluZWQgYnV0IHRoZXJlIGFyZSB1bHAw
IHdha2V1cCBzb3VyY2VzLg0KPiANCj4gDQo+IC0tDQo+IEFsZXhhbmRyZSBCZWxsb25pLCBGcmVl
IEVsZWN0cm9ucw0KPiBFbWJlZGRlZCBMaW51eCwgS2VybmVsIGFuZCBBbmRyb2lkIGVuZ2luZWVy
aW5nIGh0dHA6Ly9mcmVlLWVsZWN0cm9ucy5jb20NCg0KDQpCZXN0IFJlZ2FyZHMsDQpXZW55b3Ug
WWFuZw0K

[PATCH v5 3/5] ARM: at91: pm: configure PMC fast startup signals

[Yang, Wenyou]

Hi Alexandre,

> -----Original Message-----
> From: Alexandre Belloni [mailto:alexandre.belloni at free-electrons.com]
> Sent: 2016?3?18? 1:15
> To: Yang, Wenyou <Wenyou.Yang@atmel.com>
> Cc: Ferre, Nicolas <Nicolas.FERRE@atmel.com>; Jean-Christophe Plagniol-
> Villard <plagnioj@jcrosoft.com>; Russell King <linux@arm.linux.org.uk>; linux-
> kernel at vger.kernel.org; devicetree at vger.kernel.org; linux-arm-
> kernel at lists.infradead.org; linux-clk at vger.kernel.org; Rob Herring
> <robh+dt@kernel.org>; Pawel Moll <pawel.moll@arm.com>; Mark Brown
> <broonie@kernel.org>; Ian Campbell <ijc+devicetree@hellion.org.uk>; Kumar
> Gala <galak@codeaurora.org>
> Subject: Re: [PATCH v5 3/5] ARM: at91: pm: configure PMC fast startup signals
> 
> On 16/03/2016 at 14:58:07 +0800, Wenyou Yang wrote :
> > The fast startup signal is used as wake up sources for ULP1 mode.
> > As soon as a fast startup signal is asserted, the embedded 12 MHz RC
> > oscillator restarts automatically.
> >
> > This patch is to configure the fast startup signals, which signal is
> > enabled to trigger the PMC to wake up the system from ULP1 mode should
> > be configured via the DT.
> >
> > Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
> 
> I would actually avoid doing that from the PMC driver and do that configuration
> from the aic5 driver. It has all the information you need, it knows what kind of level
> or edge is needed to wake up and what are the wakeup interrupts to enable. This
> will allow you to stop introducing a new binding. Also, this will avoid discrepancies
> between what is configured in the DT and what the user really wants (for exemple
> differences between the edge direction configured for the PIOBu in userspace
> versus what is in the device tree or wakeonlan activation/deactivation).

Thank you for your feedback.

But some wake-ups such as WKUP pin, ACC_CE, RXLP_MCE, don't have the corresponding
interrupt number. Moreover, I think, the ULP1 is very different form the ULP0, it is not woken
up by the interrupt. It is fallen sleep and woken up by the some mechanism in the PMC. 

Maybe I was wrong. I still think the aic5 driver should be devoted on the AIC5's behaviors. 

> 
> You can get the PMC syscon from irq-atmel-aic5.c and then use a table to map
> the hwirq to the offset in PMC_FSMR. Use it in aic5_set_type to set the polarity
> and then in aic5_suspend to enable the wakeup.
> 
> Maybe we could even go further and avoid ulp1 if no ulp1 compatbile wakeup
> sources are defined but there are ulp0 wakeup sources.
> 
> 
> --
> Alexandre Belloni, Free Electrons
> Embedded Linux, Kernel and Android engineering http://free-electrons.com


Best Regards,
Wenyou Yang

RE: [PATCH v5 3/5] ARM: at91: pm: configure PMC fast startup signals

[Yang, Wenyou]

Hi Alexandre,

> -----Original Message-----
> From: Alexandre Belloni [mailto:alexandre.belloni@free-electrons.com]
> Sent: 2016年3月18日 1:15
> To: Yang, Wenyou <Wenyou.Yang@atmel.com>
> Cc: Ferre, Nicolas <Nicolas.FERRE@atmel.com>; Jean-Christophe Plagniol-
> Villard <plagnioj@jcrosoft.com>; Russell King <linux@arm.linux.org.uk>; linux-
> kernel@vger.kernel.org; devicetree@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org; linux-clk@vger.kernel.org; Rob Herring
> <robh+dt@kernel.org>; Pawel Moll <pawel.moll@arm.com>; Mark Brown
> <broonie@kernel.org>; Ian Campbell <ijc+devicetree@hellion.org.uk>; Kumar
> Gala <galak@codeaurora.org>
> Subject: Re: [PATCH v5 3/5] ARM: at91: pm: configure PMC fast startup signals
> 
> On 16/03/2016 at 14:58:07 +0800, Wenyou Yang wrote :
> > The fast startup signal is used as wake up sources for ULP1 mode.
> > As soon as a fast startup signal is asserted, the embedded 12 MHz RC
> > oscillator restarts automatically.
> >
> > This patch is to configure the fast startup signals, which signal is
> > enabled to trigger the PMC to wake up the system from ULP1 mode should
> > be configured via the DT.
> >
> > Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
> 
> I would actually avoid doing that from the PMC driver and do that configuration
> from the aic5 driver. It has all the information you need, it knows what kind of level
> or edge is needed to wake up and what are the wakeup interrupts to enable. This
> will allow you to stop introducing a new binding. Also, this will avoid discrepancies
> between what is configured in the DT and what the user really wants (for exemple
> differences between the edge direction configured for the PIOBu in userspace
> versus what is in the device tree or wakeonlan activation/deactivation).

Thank you for your feedback.

But some wake-ups such as WKUP pin, ACC_CE, RXLP_MCE, don't have the corresponding
interrupt number. Moreover, I think, the ULP1 is very different form the ULP0, it is not woken
up by the interrupt. It is fallen sleep and woken up by the some mechanism in the PMC. 

Maybe I was wrong. I still think the aic5 driver should be devoted on the AIC5's behaviors. 

> 
> You can get the PMC syscon from irq-atmel-aic5.c and then use a table to map
> the hwirq to the offset in PMC_FSMR. Use it in aic5_set_type to set the polarity
> and then in aic5_suspend to enable the wakeup.
> 
> Maybe we could even go further and avoid ulp1 if no ulp1 compatbile wakeup
> sources are defined but there are ulp0 wakeup sources.
> 
> 
> --
> Alexandre Belloni, Free Electrons
> Embedded Linux, Kernel and Android engineering http://free-electrons.com


Best Regards,
Wenyou Yang

Re: [PATCH v5 3/5] ARM: at91: pm: configure PMC fast startup signals

[Alexandre Belloni]

On 21/03/2016 at 02:24:32 +0000, Yang, Wenyou wrote :
> Hi Alexandre,
> 
> > -----Original Message-----
> > From: Alexandre Belloni [mailto:alexandre.belloni@free-electrons.com]
> > Sent: 2016年3月18日 1:15
> > To: Yang, Wenyou <Wenyou.Yang@atmel.com>
> > Cc: Ferre, Nicolas <Nicolas.FERRE@atmel.com>; Jean-Christophe Plagniol-
> > Villard <plagnioj@jcrosoft.com>; Russell King <linux@arm.linux.org.uk>; linux-
> > kernel@vger.kernel.org; devicetree@vger.kernel.org; linux-arm-
> > kernel@lists.infradead.org; linux-clk@vger.kernel.org; Rob Herring
> > <robh+dt@kernel.org>; Pawel Moll <pawel.moll@arm.com>; Mark Brown
> > <broonie@kernel.org>; Ian Campbell <ijc+devicetree@hellion.org.uk>; Kumar
> > Gala <galak@codeaurora.org>
> > Subject: Re: [PATCH v5 3/5] ARM: at91: pm: configure PMC fast startup signals
> > 
> > On 16/03/2016 at 14:58:07 +0800, Wenyou Yang wrote :
> > > The fast startup signal is used as wake up sources for ULP1 mode.
> > > As soon as a fast startup signal is asserted, the embedded 12 MHz RC
> > > oscillator restarts automatically.
> > >
> > > This patch is to configure the fast startup signals, which signal is
> > > enabled to trigger the PMC to wake up the system from ULP1 mode should
> > > be configured via the DT.
> > >
> > > Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
> > 
> > I would actually avoid doing that from the PMC driver and do that configuration
> > from the aic5 driver. It has all the information you need, it knows what kind of level
> > or edge is needed to wake up and what are the wakeup interrupts to enable. This
> > will allow you to stop introducing a new binding. Also, this will avoid discrepancies
> > between what is configured in the DT and what the user really wants (for exemple
> > differences between the edge direction configured for the PIOBu in userspace
> > versus what is in the device tree or wakeonlan activation/deactivation).
> 
> Thank you for your feedback.
> 
> But some wake-ups such as WKUP pin, ACC_CE, RXLP_MCE, don't have the corresponding

The WKUP pin can be configured from the shdwc driver, ACC_CE from the
ACC driver, RXLP_MCE, from the RXLP driver because you will need
drivers for those at some point anyway.

> interrupt number. Moreover, I think, the ULP1 is very different form the ULP0, it is not woken
> up by the interrupt. It is fallen sleep and woken up by the some mechanism in the PMC. 
> 

Well, we don't really care about the mechanism. We only care about how
the user is able to configure the wakeup sources.

With your patch set, what happens when no ULP1 sources are defined but
there are ULP0 sources? What happens when there are both ULP1 and ULP0
sources?

What would be good is to use ULP1 when only ULP1 sources are set up and
ULP0 in the other cases. This will greatly help the user. Also, what I'm
suggesting actually allows to change the ULP1 sources at runtime from
devices that are actually used which is quite better than setting them
up statically from DT.


-- 
Alexandre Belloni, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

[PATCH v5 3/5] ARM: at91: pm: configure PMC fast startup signals

[Alexandre Belloni]

On 21/03/2016 at 02:24:32 +0000, Yang, Wenyou wrote :
> Hi Alexandre,
> 
> > -----Original Message-----
> > From: Alexandre Belloni [mailto:alexandre.belloni at free-electrons.com]
> > Sent: 2016?3?18? 1:15
> > To: Yang, Wenyou <Wenyou.Yang@atmel.com>
> > Cc: Ferre, Nicolas <Nicolas.FERRE@atmel.com>; Jean-Christophe Plagniol-
> > Villard <plagnioj@jcrosoft.com>; Russell King <linux@arm.linux.org.uk>; linux-
> > kernel at vger.kernel.org; devicetree at vger.kernel.org; linux-arm-
> > kernel at lists.infradead.org; linux-clk at vger.kernel.org; Rob Herring
> > <robh+dt@kernel.org>; Pawel Moll <pawel.moll@arm.com>; Mark Brown
> > <broonie@kernel.org>; Ian Campbell <ijc+devicetree@hellion.org.uk>; Kumar
> > Gala <galak@codeaurora.org>
> > Subject: Re: [PATCH v5 3/5] ARM: at91: pm: configure PMC fast startup signals
> > 
> > On 16/03/2016 at 14:58:07 +0800, Wenyou Yang wrote :
> > > The fast startup signal is used as wake up sources for ULP1 mode.
> > > As soon as a fast startup signal is asserted, the embedded 12 MHz RC
> > > oscillator restarts automatically.
> > >
> > > This patch is to configure the fast startup signals, which signal is
> > > enabled to trigger the PMC to wake up the system from ULP1 mode should
> > > be configured via the DT.
> > >
> > > Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
> > 
> > I would actually avoid doing that from the PMC driver and do that configuration
> > from the aic5 driver. It has all the information you need, it knows what kind of level
> > or edge is needed to wake up and what are the wakeup interrupts to enable. This
> > will allow you to stop introducing a new binding. Also, this will avoid discrepancies
> > between what is configured in the DT and what the user really wants (for exemple
> > differences between the edge direction configured for the PIOBu in userspace
> > versus what is in the device tree or wakeonlan activation/deactivation).
> 
> Thank you for your feedback.
> 
> But some wake-ups such as WKUP pin, ACC_CE, RXLP_MCE, don't have the corresponding

The WKUP pin can be configured from the shdwc driver, ACC_CE from the
ACC driver, RXLP_MCE, from the RXLP driver because you will need
drivers for those at some point anyway.

> interrupt number. Moreover, I think, the ULP1 is very different form the ULP0, it is not woken
> up by the interrupt. It is fallen sleep and woken up by the some mechanism in the PMC. 
> 

Well, we don't really care about the mechanism. We only care about how
the user is able to configure the wakeup sources.

With your patch set, what happens when no ULP1 sources are defined but
there are ULP0 sources? What happens when there are both ULP1 and ULP0
sources?

What would be good is to use ULP1 when only ULP1 sources are set up and
ULP0 in the other cases. This will greatly help the user. Also, what I'm
suggesting actually allows to change the ULP1 sources at runtime from
devices that are actually used which is quite better than setting them
up statically from DT.


-- 
Alexandre Belloni, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

Re: [PATCH v5 3/5] ARM: at91: pm: configure PMC fast startup signals

[Alexandre Belloni]

On 21/03/2016 at 02:24:32 +0000, Yang, Wenyou wrote :
> Hi Alexandre,
> 
> > -----Original Message-----
> > From: Alexandre Belloni [mailto:alexandre.belloni-wi1+55ScJUtKEb57/3fJTGGXanvQGlWp@public.gmane.orgm]
> > Sent: 2016年3月18日 1:15
> > To: Yang, Wenyou <Wenyou.Yang-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org>
> > Cc: Ferre, Nicolas <Nicolas.FERRE-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org>; Jean-Christophe Plagniol-
> > Villard <plagnioj-sclMFOaUSTBWk0Htik3J/w@public.gmane.org>; Russell King <linux-lFZ/pmaqli4g9kffE6ERjg@public.gmane.orguk>; linux-
> > kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; linux-arm-
> > kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org; linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; Rob Herring
> > <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>; Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org>; Mark Brown
> > <broonie-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>; Ian Campbell <ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org>; Kumar
> > Gala <galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
> > Subject: Re: [PATCH v5 3/5] ARM: at91: pm: configure PMC fast startup signals
> > 
> > On 16/03/2016 at 14:58:07 +0800, Wenyou Yang wrote :
> > > The fast startup signal is used as wake up sources for ULP1 mode.
> > > As soon as a fast startup signal is asserted, the embedded 12 MHz RC
> > > oscillator restarts automatically.
> > >
> > > This patch is to configure the fast startup signals, which signal is
> > > enabled to trigger the PMC to wake up the system from ULP1 mode should
> > > be configured via the DT.
> > >
> > > Signed-off-by: Wenyou Yang <wenyou.yang-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org>
> > 
> > I would actually avoid doing that from the PMC driver and do that configuration
> > from the aic5 driver. It has all the information you need, it knows what kind of level
> > or edge is needed to wake up and what are the wakeup interrupts to enable. This
> > will allow you to stop introducing a new binding. Also, this will avoid discrepancies
> > between what is configured in the DT and what the user really wants (for exemple
> > differences between the edge direction configured for the PIOBu in userspace
> > versus what is in the device tree or wakeonlan activation/deactivation).
> 
> Thank you for your feedback.
> 
> But some wake-ups such as WKUP pin, ACC_CE, RXLP_MCE, don't have the corresponding

The WKUP pin can be configured from the shdwc driver, ACC_CE from the
ACC driver, RXLP_MCE, from the RXLP driver because you will need
drivers for those at some point anyway.

> interrupt number. Moreover, I think, the ULP1 is very different form the ULP0, it is not woken
> up by the interrupt. It is fallen sleep and woken up by the some mechanism in the PMC. 
> 

Well, we don't really care about the mechanism. We only care about how
the user is able to configure the wakeup sources.

With your patch set, what happens when no ULP1 sources are defined but
there are ULP0 sources? What happens when there are both ULP1 and ULP0
sources?

What would be good is to use ULP1 when only ULP1 sources are set up and
ULP0 in the other cases. This will greatly help the user. Also, what I'm
suggesting actually allows to change the ULP1 sources at runtime from
devices that are actually used which is quite better than setting them
up statically from DT.


-- 
Alexandre Belloni, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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RE: [PATCH v5 3/5] ARM: at91: pm: configure PMC fast startup signals

[Yang, Wenyou]

SGkgQWxleGFuZHJlLA0KDQo+IC0tLS0tT3JpZ2luYWwgTWVzc2FnZS0tLS0tDQo+IEZyb206IEFs
ZXhhbmRyZSBCZWxsb25pIFttYWlsdG86YWxleGFuZHJlLmJlbGxvbmlAZnJlZS1lbGVjdHJvbnMu
Y29tXQ0KPiBTZW50OiAyMDE25bm0M+aciDI05pelIDE5OjI1DQo+IFRvOiBZYW5nLCBXZW55b3Ug
PFdlbnlvdS5ZYW5nQGF0bWVsLmNvbT4NCj4gQ2M6IEZlcnJlLCBOaWNvbGFzIDxOaWNvbGFzLkZF
UlJFQGF0bWVsLmNvbT47IEplYW4tQ2hyaXN0b3BoZSBQbGFnbmlvbC0NCj4gVmlsbGFyZCA8cGxh
Z25pb2pAamNyb3NvZnQuY29tPjsgUnVzc2VsbCBLaW5nIDxsaW51eEBhcm0ubGludXgub3JnLnVr
PjsgbGludXgtDQo+IGtlcm5lbEB2Z2VyLmtlcm5lbC5vcmc7IGRldmljZXRyZWVAdmdlci5rZXJu
ZWwub3JnOyBsaW51eC1hcm0tDQo+IGtlcm5lbEBsaXN0cy5pbmZyYWRlYWQub3JnOyBsaW51eC1j
bGtAdmdlci5rZXJuZWwub3JnOyBSb2IgSGVycmluZw0KPiA8cm9iaCtkdEBrZXJuZWwub3JnPjsg
UGF3ZWwgTW9sbCA8cGF3ZWwubW9sbEBhcm0uY29tPjsgTWFyayBCcm93bg0KPiA8YnJvb25pZUBr
ZXJuZWwub3JnPjsgSWFuIENhbXBiZWxsIDxpamMrZGV2aWNldHJlZUBoZWxsaW9uLm9yZy51az47
IEt1bWFyDQo+IEdhbGEgPGdhbGFrQGNvZGVhdXJvcmEub3JnPg0KPiBTdWJqZWN0OiBSZTogW1BB
VENIIHY1IDMvNV0gQVJNOiBhdDkxOiBwbTogY29uZmlndXJlIFBNQyBmYXN0IHN0YXJ0dXAgc2ln
bmFscw0KPiANCj4gT24gMjEvMDMvMjAxNiBhdCAwMjoyNDozMiArMDAwMCwgWWFuZywgV2VueW91
IHdyb3RlIDoNCj4gPiBIaSBBbGV4YW5kcmUsDQo+ID4NCj4gPiA+IC0tLS0tT3JpZ2luYWwgTWVz
c2FnZS0tLS0tDQo+ID4gPiBGcm9tOiBBbGV4YW5kcmUgQmVsbG9uaQ0KPiA+ID4gW21haWx0bzph
bGV4YW5kcmUuYmVsbG9uaUBmcmVlLWVsZWN0cm9ucy5jb21dDQo+ID4gPiBTZW50OiAyMDE25bm0
M+aciDE45pelIDE6MTUNCj4gPiA+IFRvOiBZYW5nLCBXZW55b3UgPFdlbnlvdS5ZYW5nQGF0bWVs
LmNvbT4NCj4gPiA+IENjOiBGZXJyZSwgTmljb2xhcyA8Tmljb2xhcy5GRVJSRUBhdG1lbC5jb20+
OyBKZWFuLUNocmlzdG9waGUNCj4gPiA+IFBsYWduaW9sLSBWaWxsYXJkIDxwbGFnbmlvakBqY3Jv
c29mdC5jb20+OyBSdXNzZWxsIEtpbmcNCj4gPiA+IDxsaW51eEBhcm0ubGludXgub3JnLnVrPjsg
bGludXgtIGtlcm5lbEB2Z2VyLmtlcm5lbC5vcmc7DQo+ID4gPiBkZXZpY2V0cmVlQHZnZXIua2Vy
bmVsLm9yZzsgbGludXgtYXJtLSBrZXJuZWxAbGlzdHMuaW5mcmFkZWFkLm9yZzsNCj4gPiA+IGxp
bnV4LWNsa0B2Z2VyLmtlcm5lbC5vcmc7IFJvYiBIZXJyaW5nIDxyb2JoK2R0QGtlcm5lbC5vcmc+
OyBQYXdlbA0KPiA+ID4gTW9sbCA8cGF3ZWwubW9sbEBhcm0uY29tPjsgTWFyayBCcm93biA8YnJv
b25pZUBrZXJuZWwub3JnPjsgSWFuDQo+ID4gPiBDYW1wYmVsbCA8aWpjK2RldmljZXRyZWVAaGVs
bGlvbi5vcmcudWs+OyBLdW1hciBHYWxhDQo+ID4gPiA8Z2FsYWtAY29kZWF1cm9yYS5vcmc+DQo+
ID4gPiBTdWJqZWN0OiBSZTogW1BBVENIIHY1IDMvNV0gQVJNOiBhdDkxOiBwbTogY29uZmlndXJl
IFBNQyBmYXN0DQo+ID4gPiBzdGFydHVwIHNpZ25hbHMNCj4gPiA+DQo+ID4gPiBPbiAxNi8wMy8y
MDE2IGF0IDE0OjU4OjA3ICswODAwLCBXZW55b3UgWWFuZyB3cm90ZSA6DQo+ID4gPiA+IFRoZSBm
YXN0IHN0YXJ0dXAgc2lnbmFsIGlzIHVzZWQgYXMgd2FrZSB1cCBzb3VyY2VzIGZvciBVTFAxIG1v
ZGUuDQo+ID4gPiA+IEFzIHNvb24gYXMgYSBmYXN0IHN0YXJ0dXAgc2lnbmFsIGlzIGFzc2VydGVk
LCB0aGUgZW1iZWRkZWQgMTIgTUh6DQo+ID4gPiA+IFJDIG9zY2lsbGF0b3IgcmVzdGFydHMgYXV0
b21hdGljYWxseS4NCj4gPiA+ID4NCj4gPiA+ID4gVGhpcyBwYXRjaCBpcyB0byBjb25maWd1cmUg
dGhlIGZhc3Qgc3RhcnR1cCBzaWduYWxzLCB3aGljaCBzaWduYWwNCj4gPiA+ID4gaXMgZW5hYmxl
ZCB0byB0cmlnZ2VyIHRoZSBQTUMgdG8gd2FrZSB1cCB0aGUgc3lzdGVtIGZyb20gVUxQMSBtb2Rl
DQo+ID4gPiA+IHNob3VsZCBiZSBjb25maWd1cmVkIHZpYSB0aGUgRFQuDQo+ID4gPiA+DQo+ID4g
PiA+IFNpZ25lZC1vZmYtYnk6IFdlbnlvdSBZYW5nIDx3ZW55b3UueWFuZ0BhdG1lbC5jb20+DQo+
ID4gPg0KPiA+ID4gSSB3b3VsZCBhY3R1YWxseSBhdm9pZCBkb2luZyB0aGF0IGZyb20gdGhlIFBN
QyBkcml2ZXIgYW5kIGRvIHRoYXQNCj4gPiA+IGNvbmZpZ3VyYXRpb24gZnJvbSB0aGUgYWljNSBk
cml2ZXIuIEl0IGhhcyBhbGwgdGhlIGluZm9ybWF0aW9uIHlvdQ0KPiA+ID4gbmVlZCwgaXQga25v
d3Mgd2hhdCBraW5kIG9mIGxldmVsIG9yIGVkZ2UgaXMgbmVlZGVkIHRvIHdha2UgdXAgYW5kDQo+
ID4gPiB3aGF0IGFyZSB0aGUgd2FrZXVwIGludGVycnVwdHMgdG8gZW5hYmxlLiBUaGlzIHdpbGwg
YWxsb3cgeW91IHRvDQo+ID4gPiBzdG9wIGludHJvZHVjaW5nIGEgbmV3IGJpbmRpbmcuIEFsc28s
IHRoaXMgd2lsbCBhdm9pZCBkaXNjcmVwYW5jaWVzDQo+ID4gPiBiZXR3ZWVuIHdoYXQgaXMgY29u
ZmlndXJlZCBpbiB0aGUgRFQgYW5kIHdoYXQgdGhlIHVzZXIgcmVhbGx5IHdhbnRzDQo+ID4gPiAo
Zm9yIGV4ZW1wbGUgZGlmZmVyZW5jZXMgYmV0d2VlbiB0aGUgZWRnZSBkaXJlY3Rpb24gY29uZmln
dXJlZCBmb3IgdGhlIFBJT0J1DQo+IGluIHVzZXJzcGFjZSB2ZXJzdXMgd2hhdCBpcyBpbiB0aGUg
ZGV2aWNlIHRyZWUgb3Igd2FrZW9ubGFuDQo+IGFjdGl2YXRpb24vZGVhY3RpdmF0aW9uKS4NCj4g
Pg0KPiA+IFRoYW5rIHlvdSBmb3IgeW91ciBmZWVkYmFjay4NCj4gPg0KPiA+IEJ1dCBzb21lIHdh
a2UtdXBzIHN1Y2ggYXMgV0tVUCBwaW4sIEFDQ19DRSwgUlhMUF9NQ0UsIGRvbid0IGhhdmUgdGhl
DQo+ID4gY29ycmVzcG9uZGluZw0KPiANCj4gVGhlIFdLVVAgcGluIGNhbiBiZSBjb25maWd1cmVk
IGZyb20gdGhlIHNoZHdjIGRyaXZlciwgQUNDX0NFIGZyb20gdGhlIEFDQw0KPiBkcml2ZXIsIFJY
TFBfTUNFLCBmcm9tIHRoZSBSWExQIGRyaXZlciBiZWNhdXNlIHlvdSB3aWxsIG5lZWQgZHJpdmVy
cyBmb3IgdGhvc2UNCj4gYXQgc29tZSBwb2ludCBhbnl3YXkuDQo+IA0KPiA+IGludGVycnVwdCBu
dW1iZXIuIE1vcmVvdmVyLCBJIHRoaW5rLCB0aGUgVUxQMSBpcyB2ZXJ5IGRpZmZlcmVudCBmb3Jt
DQo+ID4gdGhlIFVMUDAsIGl0IGlzIG5vdCB3b2tlbiB1cCBieSB0aGUgaW50ZXJydXB0LiBJdCBp
cyBmYWxsZW4gc2xlZXAgYW5kIHdva2VuIHVwIGJ5DQo+IHRoZSBzb21lIG1lY2hhbmlzbSBpbiB0
aGUgUE1DLg0KPiA+DQo+IA0KPiBXZWxsLCB3ZSBkb24ndCByZWFsbHkgY2FyZSBhYm91dCB0aGUg
bWVjaGFuaXNtLiBXZSBvbmx5IGNhcmUgYWJvdXQgaG93IHRoZSB1c2VyDQo+IGlzIGFibGUgdG8g
Y29uZmlndXJlIHRoZSB3YWtldXAgc291cmNlcy4NCg0KVW5kZXJzdGFuZCB5b3VyIGNvbmNlcm5z
Lg0KDQo+IA0KPiBXaXRoIHlvdXIgcGF0Y2ggc2V0LCB3aGF0IGhhcHBlbnMgd2hlbiBubyBVTFAx
IHNvdXJjZXMgYXJlIGRlZmluZWQgYnV0IHRoZXJlDQo+IGFyZSBVTFAwIHNvdXJjZXM/IFdoYXQg
aGFwcGVucyB3aGVuIHRoZXJlIGFyZSBib3RoIFVMUDEgYW5kIFVMUDAgc291cmNlcz8NCg0KSSB0
aGluayB0aGVyZSBpcyBvbmx5IG9uZSBtb2RlLCBlaXRoZXIgVUxQMSBvciBVTFAwLCBpbiBhIHJ1
bnRpbWUgc3lzdGVtLg0KVGhlIFVMUDEgc291cmNlcyBhcmUgdXNlZCB0byB3YWtlIHVwIHRoZSBV
TFAxLCBhbmQgdGhlIFVMUDAgc291cmNlcyB3YWtlIHVwIHRoZSBVTFAwLA0KdGhleSBkb24ndCBt
dXR1YWxseSBlZmZlY3QgZWFjaCBvdGhlci4NCg0KSWYgc3lzdGVtIGlzIGluIHRoZSBVTFAxIG1v
ZGUsIGFuZCB0aGVyZSBhcmUgbm8gVUxQMSBzb3VyY2VzIGRlZmluZWQsIHRoZSBzeXN0ZW0gd2ls
bCBmYWlsIHRvDQpiZSB3YWtlbiB1cCwgZXZlbiB0aG91Z2ggdGhlcmUgYXJlIFVMUDAgc291cmNl
cyBkZWZpbmVkLiBUaGUgVUxQMCBzb3VyY2UgY2FuJ3Qgd2FrZSB1cCB0aGUgVUxQMS4NCg0KPiAN
Cj4gV2hhdCB3b3VsZCBiZSBnb29kIGlzIHRvIHVzZSBVTFAxIHdoZW4gb25seSBVTFAxIHNvdXJj
ZXMgYXJlIHNldCB1cCBhbmQNCj4gVUxQMCBpbiB0aGUgb3RoZXIgY2FzZXMuIFRoaXMgd2lsbCBn
cmVhdGx5IGhlbHAgdGhlIHVzZXIuIEFsc28sIHdoYXQgSSdtIHN1Z2dlc3RpbmcNCj4gYWN0dWFs
bHkgYWxsb3dzIHRvIGNoYW5nZSB0aGUgVUxQMSBzb3VyY2VzIGF0IHJ1bnRpbWUgZnJvbSBkZXZp
Y2VzIHRoYXQgYXJlDQo+IGFjdHVhbGx5IHVzZWQgd2hpY2ggaXMgcXVpdGUgYmV0dGVyIHRoYW4g
c2V0dGluZyB0aGVtIHVwIHN0YXRpY2FsbHkgZnJvbSBEVC4NCj4gDQoNCkluIHRoZSBVTFAxIG1v
ZGUsIGFsbCBjbG9ja3MgYXJlIGRpc2FibGVkLiBJdCBjYW4gZ2V0IGxvd2VyIGNvbnN1bXB0aW9u
IGFuZA0KcXVpY2tlciB3YWtlIHVwICh0aGUgcHJvY2Vzc29yIHJlc3RhcnRzIGluIGxlc3MgdGhh
biAxMHVzKSB0aGFuIFVMUDAgbW9kZS4NCg0KVGhlIG51bWJlciBvZiB3YWtlIHVwIHNvdXJjZXMg
aXMgbGltaXRlZCBhcyB3ZWxsLiBJdCBpcyB2ZXJ5IGRpZmZlcmVudCBmcm9tIFVMUDAncw0KDQoN
CkhpIE5pY29sYXMsIHdoYXQgaXMgeW91ciBvcGluaW9ucz8NCg0KDQpCZXN0IFJlZ2FyZHMsDQpX
ZW55b3UgWWFuZw0K

[PATCH v5 3/5] ARM: at91: pm: configure PMC fast startup signals

[Yang, Wenyou]

Hi Alexandre,

> -----Original Message-----
> From: Alexandre Belloni [mailto:alexandre.belloni at free-electrons.com]
> Sent: 2016?3?24? 19:25
> To: Yang, Wenyou <Wenyou.Yang@atmel.com>
> Cc: Ferre, Nicolas <Nicolas.FERRE@atmel.com>; Jean-Christophe Plagniol-
> Villard <plagnioj@jcrosoft.com>; Russell King <linux@arm.linux.org.uk>; linux-
> kernel at vger.kernel.org; devicetree at vger.kernel.org; linux-arm-
> kernel at lists.infradead.org; linux-clk at vger.kernel.org; Rob Herring
> <robh+dt@kernel.org>; Pawel Moll <pawel.moll@arm.com>; Mark Brown
> <broonie@kernel.org>; Ian Campbell <ijc+devicetree@hellion.org.uk>; Kumar
> Gala <galak@codeaurora.org>
> Subject: Re: [PATCH v5 3/5] ARM: at91: pm: configure PMC fast startup signals
> 
> On 21/03/2016 at 02:24:32 +0000, Yang, Wenyou wrote :
> > Hi Alexandre,
> >
> > > -----Original Message-----
> > > From: Alexandre Belloni
> > > [mailto:alexandre.belloni at free-electrons.com]
> > > Sent: 2016?3?18? 1:15
> > > To: Yang, Wenyou <Wenyou.Yang@atmel.com>
> > > Cc: Ferre, Nicolas <Nicolas.FERRE@atmel.com>; Jean-Christophe
> > > Plagniol- Villard <plagnioj@jcrosoft.com>; Russell King
> > > <linux@arm.linux.org.uk>; linux- kernel at vger.kernel.org;
> > > devicetree at vger.kernel.org; linux-arm- kernel at lists.infradead.org;
> > > linux-clk at vger.kernel.org; Rob Herring <robh+dt@kernel.org>; Pawel
> > > Moll <pawel.moll@arm.com>; Mark Brown <broonie@kernel.org>; Ian
> > > Campbell <ijc+devicetree@hellion.org.uk>; Kumar Gala
> > > <galak@codeaurora.org>
> > > Subject: Re: [PATCH v5 3/5] ARM: at91: pm: configure PMC fast
> > > startup signals
> > >
> > > On 16/03/2016 at 14:58:07 +0800, Wenyou Yang wrote :
> > > > The fast startup signal is used as wake up sources for ULP1 mode.
> > > > As soon as a fast startup signal is asserted, the embedded 12 MHz
> > > > RC oscillator restarts automatically.
> > > >
> > > > This patch is to configure the fast startup signals, which signal
> > > > is enabled to trigger the PMC to wake up the system from ULP1 mode
> > > > should be configured via the DT.
> > > >
> > > > Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
> > >
> > > I would actually avoid doing that from the PMC driver and do that
> > > configuration from the aic5 driver. It has all the information you
> > > need, it knows what kind of level or edge is needed to wake up and
> > > what are the wakeup interrupts to enable. This will allow you to
> > > stop introducing a new binding. Also, this will avoid discrepancies
> > > between what is configured in the DT and what the user really wants
> > > (for exemple differences between the edge direction configured for the PIOBu
> in userspace versus what is in the device tree or wakeonlan
> activation/deactivation).
> >
> > Thank you for your feedback.
> >
> > But some wake-ups such as WKUP pin, ACC_CE, RXLP_MCE, don't have the
> > corresponding
> 
> The WKUP pin can be configured from the shdwc driver, ACC_CE from the ACC
> driver, RXLP_MCE, from the RXLP driver because you will need drivers for those
> at some point anyway.
> 
> > interrupt number. Moreover, I think, the ULP1 is very different form
> > the ULP0, it is not woken up by the interrupt. It is fallen sleep and woken up by
> the some mechanism in the PMC.
> >
> 
> Well, we don't really care about the mechanism. We only care about how the user
> is able to configure the wakeup sources.

Understand your concerns.

> 
> With your patch set, what happens when no ULP1 sources are defined but there
> are ULP0 sources? What happens when there are both ULP1 and ULP0 sources?

I think there is only one mode, either ULP1 or ULP0, in a runtime system.
The ULP1 sources are used to wake up the ULP1, and the ULP0 sources wake up the ULP0,
they don't mutually effect each other.

If system is in the ULP1 mode, and there are no ULP1 sources defined, the system will fail to
be waken up, even though there are ULP0 sources defined. The ULP0 source can't wake up the ULP1.

> 
> What would be good is to use ULP1 when only ULP1 sources are set up and
> ULP0 in the other cases. This will greatly help the user. Also, what I'm suggesting
> actually allows to change the ULP1 sources at runtime from devices that are
> actually used which is quite better than setting them up statically from DT.
> 

In the ULP1 mode, all clocks are disabled. It can get lower consumption and
quicker wake up (the processor restarts in less than 10us) than ULP0 mode.

The number of wake up sources is limited as well. It is very different from ULP0's


Hi Nicolas, what is your opinions?


Best Regards,
Wenyou Yang

RE: [PATCH v5 3/5] ARM: at91: pm: configure PMC fast startup signals

[Yang, Wenyou]

Hi Alexandre,

> -----Original Message-----
> From: Alexandre Belloni [mailto:alexandre.belloni@free-electrons.com]
> Sent: 2016年3月24日 19:25
> To: Yang, Wenyou <Wenyou.Yang@atmel.com>
> Cc: Ferre, Nicolas <Nicolas.FERRE@atmel.com>; Jean-Christophe Plagniol-
> Villard <plagnioj@jcrosoft.com>; Russell King <linux@arm.linux.org.uk>; linux-
> kernel@vger.kernel.org; devicetree@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org; linux-clk@vger.kernel.org; Rob Herring
> <robh+dt@kernel.org>; Pawel Moll <pawel.moll@arm.com>; Mark Brown
> <broonie@kernel.org>; Ian Campbell <ijc+devicetree@hellion.org.uk>; Kumar
> Gala <galak@codeaurora.org>
> Subject: Re: [PATCH v5 3/5] ARM: at91: pm: configure PMC fast startup signals
> 
> On 21/03/2016 at 02:24:32 +0000, Yang, Wenyou wrote :
> > Hi Alexandre,
> >
> > > -----Original Message-----
> > > From: Alexandre Belloni
> > > [mailto:alexandre.belloni@free-electrons.com]
> > > Sent: 2016年3月18日 1:15
> > > To: Yang, Wenyou <Wenyou.Yang@atmel.com>
> > > Cc: Ferre, Nicolas <Nicolas.FERRE@atmel.com>; Jean-Christophe
> > > Plagniol- Villard <plagnioj@jcrosoft.com>; Russell King
> > > <linux@arm.linux.org.uk>; linux- kernel@vger.kernel.org;
> > > devicetree@vger.kernel.org; linux-arm- kernel@lists.infradead.org;
> > > linux-clk@vger.kernel.org; Rob Herring <robh+dt@kernel.org>; Pawel
> > > Moll <pawel.moll@arm.com>; Mark Brown <broonie@kernel.org>; Ian
> > > Campbell <ijc+devicetree@hellion.org.uk>; Kumar Gala
> > > <galak@codeaurora.org>
> > > Subject: Re: [PATCH v5 3/5] ARM: at91: pm: configure PMC fast
> > > startup signals
> > >
> > > On 16/03/2016 at 14:58:07 +0800, Wenyou Yang wrote :
> > > > The fast startup signal is used as wake up sources for ULP1 mode.
> > > > As soon as a fast startup signal is asserted, the embedded 12 MHz
> > > > RC oscillator restarts automatically.
> > > >
> > > > This patch is to configure the fast startup signals, which signal
> > > > is enabled to trigger the PMC to wake up the system from ULP1 mode
> > > > should be configured via the DT.
> > > >
> > > > Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
> > >
> > > I would actually avoid doing that from the PMC driver and do that
> > > configuration from the aic5 driver. It has all the information you
> > > need, it knows what kind of level or edge is needed to wake up and
> > > what are the wakeup interrupts to enable. This will allow you to
> > > stop introducing a new binding. Also, this will avoid discrepancies
> > > between what is configured in the DT and what the user really wants
> > > (for exemple differences between the edge direction configured for the PIOBu
> in userspace versus what is in the device tree or wakeonlan
> activation/deactivation).
> >
> > Thank you for your feedback.
> >
> > But some wake-ups such as WKUP pin, ACC_CE, RXLP_MCE, don't have the
> > corresponding
> 
> The WKUP pin can be configured from the shdwc driver, ACC_CE from the ACC
> driver, RXLP_MCE, from the RXLP driver because you will need drivers for those
> at some point anyway.
> 
> > interrupt number. Moreover, I think, the ULP1 is very different form
> > the ULP0, it is not woken up by the interrupt. It is fallen sleep and woken up by
> the some mechanism in the PMC.
> >
> 
> Well, we don't really care about the mechanism. We only care about how the user
> is able to configure the wakeup sources.

Understand your concerns.

> 
> With your patch set, what happens when no ULP1 sources are defined but there
> are ULP0 sources? What happens when there are both ULP1 and ULP0 sources?

I think there is only one mode, either ULP1 or ULP0, in a runtime system.
The ULP1 sources are used to wake up the ULP1, and the ULP0 sources wake up the ULP0,
they don't mutually effect each other.

If system is in the ULP1 mode, and there are no ULP1 sources defined, the system will fail to
be waken up, even though there are ULP0 sources defined. The ULP0 source can't wake up the ULP1.

> 
> What would be good is to use ULP1 when only ULP1 sources are set up and
> ULP0 in the other cases. This will greatly help the user. Also, what I'm suggesting
> actually allows to change the ULP1 sources at runtime from devices that are
> actually used which is quite better than setting them up statically from DT.
> 

In the ULP1 mode, all clocks are disabled. It can get lower consumption and
quicker wake up (the processor restarts in less than 10us) than ULP0 mode.

The number of wake up sources is limited as well. It is very different from ULP0's


Hi Nicolas, what is your opinions?


Best Regards,
Wenyou Yang