From: shawnguo@kernel.org (Shawn Guo)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v1 3/4] ARM: dts: vfxxx: Add OCROM and phandle entries for Vybrid SoC bus driver
Date: Fri, 1 Apr 2016 14:00:46 +0800 [thread overview]
Message-ID: <20160401060046.GG18833@tiger> (raw)
In-Reply-To: <39ab1c08dacb7fc4e36a3f3517da16d4da47710b.1457684688.git.maitysanchayan@gmail.com>
On Fri, Mar 11, 2016 at 02:29:30PM +0530, Sanchayan Maity wrote:
> Add OCROM node and introduce phandles to OCROM, MSCM and NVMEM
> OCOTP for use by the Vybrid SoC bus driver.
>
> Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
> ---
> arch/arm/boot/dts/vfxxx.dtsi | 12 +++++++++++-
> 1 file changed, 11 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/vfxxx.dtsi b/arch/arm/boot/dts/vfxxx.dtsi
> index db9157e..0dd7ad5 100644
> --- a/arch/arm/boot/dts/vfxxx.dtsi
> +++ b/arch/arm/boot/dts/vfxxx.dtsi
> @@ -87,9 +87,19 @@
> soc {
> #address-cells = <1>;
> #size-cells = <1>;
> - compatible = "simple-bus";
> + compatible = "fsl,vf610-soc-bus", "simple-bus";
> interrupt-parent = <&mscm_ir>;
> ranges;
> + fsl,rom-revision = <&ocrom 0x80>;
> + fsl,cpu-count = <&mscm_cpucfg 0x2C>;
> + fsl,l2-size = <&mscm_cpucfg 0x14>;
We need a bindings doc for these new properties and compatible.
Shawn
> + nvmem-cells = <&ocotp_cfg0>, <&ocotp_cfg1>;
> + nvmem-cell-names = "cfg0", "cfg1";
> +
> + ocrom: ocrom at 00000000 {
> + compatible = "fsl,vf610-ocrom", "syscon";
> + reg = <0x00000000 0x18000>;
> + };
>
> aips0: aips-bus at 40000000 {
> compatible = "fsl,aips-bus", "simple-bus";
> --
> 2.7.2
>
>
WARNING: multiple messages have this Message-ID (diff)
From: Shawn Guo <shawnguo-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
To: Sanchayan Maity <maitysanchayan-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: arnd-r2nGTMty4D4@public.gmane.org,
stefan-XLVq0VzYD2Y@public.gmane.org,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org,
lee.jones-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Subject: Re: [PATCH v1 3/4] ARM: dts: vfxxx: Add OCROM and phandle entries for Vybrid SoC bus driver
Date: Fri, 1 Apr 2016 14:00:46 +0800 [thread overview]
Message-ID: <20160401060046.GG18833@tiger> (raw)
In-Reply-To: <39ab1c08dacb7fc4e36a3f3517da16d4da47710b.1457684688.git.maitysanchayan-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
On Fri, Mar 11, 2016 at 02:29:30PM +0530, Sanchayan Maity wrote:
> Add OCROM node and introduce phandles to OCROM, MSCM and NVMEM
> OCOTP for use by the Vybrid SoC bus driver.
>
> Signed-off-by: Sanchayan Maity <maitysanchayan-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> ---
> arch/arm/boot/dts/vfxxx.dtsi | 12 +++++++++++-
> 1 file changed, 11 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/vfxxx.dtsi b/arch/arm/boot/dts/vfxxx.dtsi
> index db9157e..0dd7ad5 100644
> --- a/arch/arm/boot/dts/vfxxx.dtsi
> +++ b/arch/arm/boot/dts/vfxxx.dtsi
> @@ -87,9 +87,19 @@
> soc {
> #address-cells = <1>;
> #size-cells = <1>;
> - compatible = "simple-bus";
> + compatible = "fsl,vf610-soc-bus", "simple-bus";
> interrupt-parent = <&mscm_ir>;
> ranges;
> + fsl,rom-revision = <&ocrom 0x80>;
> + fsl,cpu-count = <&mscm_cpucfg 0x2C>;
> + fsl,l2-size = <&mscm_cpucfg 0x14>;
We need a bindings doc for these new properties and compatible.
Shawn
> + nvmem-cells = <&ocotp_cfg0>, <&ocotp_cfg1>;
> + nvmem-cell-names = "cfg0", "cfg1";
> +
> + ocrom: ocrom@00000000 {
> + compatible = "fsl,vf610-ocrom", "syscon";
> + reg = <0x00000000 0x18000>;
> + };
>
> aips0: aips-bus@40000000 {
> compatible = "fsl,aips-bus", "simple-bus";
> --
> 2.7.2
>
>
--
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WARNING: multiple messages have this Message-ID (diff)
From: Shawn Guo <shawnguo@kernel.org>
To: Sanchayan Maity <maitysanchayan@gmail.com>
Cc: arnd@arndb.de, stefan@agner.ch, robh+dt@kernel.org,
lee.jones@linaro.org, linux-arm-kernel@lists.infradead.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v1 3/4] ARM: dts: vfxxx: Add OCROM and phandle entries for Vybrid SoC bus driver
Date: Fri, 1 Apr 2016 14:00:46 +0800 [thread overview]
Message-ID: <20160401060046.GG18833@tiger> (raw)
In-Reply-To: <39ab1c08dacb7fc4e36a3f3517da16d4da47710b.1457684688.git.maitysanchayan@gmail.com>
On Fri, Mar 11, 2016 at 02:29:30PM +0530, Sanchayan Maity wrote:
> Add OCROM node and introduce phandles to OCROM, MSCM and NVMEM
> OCOTP for use by the Vybrid SoC bus driver.
>
> Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
> ---
> arch/arm/boot/dts/vfxxx.dtsi | 12 +++++++++++-
> 1 file changed, 11 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/vfxxx.dtsi b/arch/arm/boot/dts/vfxxx.dtsi
> index db9157e..0dd7ad5 100644
> --- a/arch/arm/boot/dts/vfxxx.dtsi
> +++ b/arch/arm/boot/dts/vfxxx.dtsi
> @@ -87,9 +87,19 @@
> soc {
> #address-cells = <1>;
> #size-cells = <1>;
> - compatible = "simple-bus";
> + compatible = "fsl,vf610-soc-bus", "simple-bus";
> interrupt-parent = <&mscm_ir>;
> ranges;
> + fsl,rom-revision = <&ocrom 0x80>;
> + fsl,cpu-count = <&mscm_cpucfg 0x2C>;
> + fsl,l2-size = <&mscm_cpucfg 0x14>;
We need a bindings doc for these new properties and compatible.
Shawn
> + nvmem-cells = <&ocotp_cfg0>, <&ocotp_cfg1>;
> + nvmem-cell-names = "cfg0", "cfg1";
> +
> + ocrom: ocrom@00000000 {
> + compatible = "fsl,vf610-ocrom", "syscon";
> + reg = <0x00000000 0x18000>;
> + };
>
> aips0: aips-bus@40000000 {
> compatible = "fsl,aips-bus", "simple-bus";
> --
> 2.7.2
>
>
next prev parent reply other threads:[~2016-04-01 6:00 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-03-11 8:59 [PATCH v1 0/4] Implement SoC bus driver for Vybrid Sanchayan Maity
2016-03-11 8:59 ` Sanchayan Maity
2016-03-11 8:59 ` Sanchayan Maity
2016-03-11 8:59 ` [PATCH v1 1/4] mfd: syscon: Introduce syscon_regmap_read_from_offset Sanchayan Maity
2016-03-11 8:59 ` Sanchayan Maity
2016-03-11 8:59 ` Sanchayan Maity
2016-03-11 8:59 ` [PATCH v1 2/4] ARM: dts: vfxxx: Add device tree node for OCOTP Sanchayan Maity
2016-03-11 8:59 ` Sanchayan Maity
2016-03-11 8:59 ` Sanchayan Maity
2016-03-11 8:59 ` [PATCH v1 3/4] ARM: dts: vfxxx: Add OCROM and phandle entries for Vybrid SoC bus driver Sanchayan Maity
2016-03-11 8:59 ` Sanchayan Maity
2016-03-11 8:59 ` Sanchayan Maity
2016-04-01 6:00 ` Shawn Guo [this message]
2016-04-01 6:00 ` Shawn Guo
2016-04-01 6:00 ` Shawn Guo
2016-04-04 8:14 ` maitysanchayan at gmail.com
2016-04-04 8:14 ` maitysanchayan
2016-03-11 8:59 ` [PATCH v1 4/4] soc: Add SoC bus driver for Freescale Vybrid Platform Sanchayan Maity
2016-03-11 8:59 ` Sanchayan Maity
2016-03-28 5:35 ` [PATCH v1 0/4] Implement SoC bus driver for Vybrid maitysanchayan at gmail.com
2016-03-28 5:35 ` maitysanchayan
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