[PATCH v5 0/2] Add ZII development board.

[PATCH v5 0/2] Add ZII development board.

[Andrew Lunn]

Rather than list empty DMA properties, this version includes an
additional patch adding quirks to the serial driver, and disabling DMA
when the vybrid compatibility string is seen.

Andrew Lunn (1):
  serial: fsl_lpuart: Add DMA quirk

Cory Tusar (1):
  ARM: dts: vf610-zii-dev: Add ZII development board.

 arch/arm/boot/dts/Makefile                |   3 +-
 arch/arm/boot/dts/vf610-zii-dev-rev-b.dts | 736 ++++++++++++++++++++++++++++++
 drivers/tty/serial/fsl_lpuart.c           |  36 +-
 3 files changed, 764 insertions(+), 11 deletions(-)
 create mode 100644 arch/arm/boot/dts/vf610-zii-dev-rev-b.dts

-- 
2.7.0

[PATCH v5 1/2] serial: fsl_lpuart: Add DMA quirk

[Andrew Lunn]

Using DMA with the vf610 and other Vybrid devices results in a corrupt
serial stream. Add a quirk to disable the use of DMA.

Refactor the existing code to add a 32 bit access quirk for the
fsl,ls1021a-lpuart.

Signed-off-by: Andrew Lunn <andrew@lunn.ch>
---
 drivers/tty/serial/fsl_lpuart.c | 36 ++++++++++++++++++++++++++----------
 1 file changed, 26 insertions(+), 10 deletions(-)

diff --git a/drivers/tty/serial/fsl_lpuart.c b/drivers/tty/serial/fsl_lpuart.c
index 3d790033744e..8d2f67b93e1f 100644
--- a/drivers/tty/serial/fsl_lpuart.c
+++ b/drivers/tty/serial/fsl_lpuart.c
@@ -257,12 +257,17 @@ struct lpuart_port {
 	struct timer_list	lpuart_timer;
 };
 
+#define QUIRK_LPUART32		BIT(0)
+#define QUIRK_NO_DMA		BIT(1)
+
 static const struct of_device_id lpuart_dt_ids[] = {
 	{
 		.compatible = "fsl,vf610-lpuart",
+		.data = (void *)QUIRK_NO_DMA,
 	},
 	{
 		.compatible = "fsl,ls1021a-lpuart",
+		.data = (void *)QUIRK_LPUART32,
 	},
 	{ /* sentinel */ }
 };
@@ -1803,7 +1808,9 @@ static struct uart_driver lpuart_reg = {
 static int lpuart_probe(struct platform_device *pdev)
 {
 	struct device_node *np = pdev->dev.of_node;
+	const struct of_device_id *match;
 	struct lpuart_port *sport;
+	kernel_ulong_t quirks;
 	struct resource *res;
 	int ret;
 
@@ -1819,7 +1826,10 @@ static int lpuart_probe(struct platform_device *pdev)
 		return ret;
 	}
 	sport->port.line = ret;
-	sport->lpuart32 = of_device_is_compatible(np, "fsl,ls1021a-lpuart");
+
+	match = of_match_node(lpuart_dt_ids, np);
+	quirks = (kernel_ulong_t)match->data;
+	sport->lpuart32 = quirks & QUIRK_LPUART32;
 
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	sport->port.membase = devm_ioremap_resource(&pdev->dev, res);
@@ -1867,15 +1877,21 @@ static int lpuart_probe(struct platform_device *pdev)
 		return ret;
 	}
 
-	sport->dma_tx_chan = dma_request_slave_channel(sport->port.dev, "tx");
-	if (!sport->dma_tx_chan)
-		dev_info(sport->port.dev, "DMA tx channel request failed, "
-				"operating without tx DMA\n");
-
-	sport->dma_rx_chan = dma_request_slave_channel(sport->port.dev, "rx");
-	if (!sport->dma_rx_chan)
-		dev_info(sport->port.dev, "DMA rx channel request failed, "
-				"operating without rx DMA\n");
+	if (quirks & QUIRK_NO_DMA) {
+		dev_info(sport->port.dev, "Not using DMA\n");
+	} else {
+		sport->dma_tx_chan = dma_request_slave_channel(
+			sport->port.dev, "tx");
+		if (!sport->dma_tx_chan)
+			dev_info(sport->port.dev,
+				 "DMA tx channel request failed, operating without tx DMA\n");
+
+		sport->dma_rx_chan = dma_request_slave_channel(
+			sport->port.dev, "rx");
+		if (!sport->dma_rx_chan)
+			dev_info(sport->port.dev,
+				 "DMA rx channel request failed, operating without rx DMA\n");
+	}
 
 	return 0;
 }
-- 
2.7.0

[PATCH v5 1/2] serial: fsl_lpuart: Add DMA quirk

[Stefan Agner]

On 2016-04-04 14:53, Andrew Lunn wrote:
> Using DMA with the vf610 and other Vybrid devices results in a corrupt
> serial stream. Add a quirk to disable the use of DMA.
> 
> Refactor the existing code to add a 32 bit access quirk for the
> fsl,ls1021a-lpuart.

Hi Andrew,

[also added Greg and Jiri, maintainers of the tty subsystem]

Well, I am not sure if that is the right approach. Quirks are usually
used to hint to issues in the hardware. However, in this case we deal
with (a) software issue(s)...

At Toradex we were carry a patch which disabled DMA by default using a
module parameter:
http://git.toradex.com/cgit/linux-toradex.git/commit/?h=toradex_vf_4.4-next&id=f5baad61b77dd4b0ac0c7beeee284e12d49ba442

This allowed to re-enable the DMA easily for testing... Not sure if that
is the better approach.

However, we are working on a re-implementation of the DMA modes, I hope
we can post some patches soon.

IMHO we can just omit adding such a disable work around, people lived
with the current situation since 3.13, one more release probably doesn't
really matter... :-)

--
Stefan


> 
> Signed-off-by: Andrew Lunn <andrew@lunn.ch>
> ---
>  drivers/tty/serial/fsl_lpuart.c | 36 ++++++++++++++++++++++++++----------
>  1 file changed, 26 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/tty/serial/fsl_lpuart.c b/drivers/tty/serial/fsl_lpuart.c
> index 3d790033744e..8d2f67b93e1f 100644
> --- a/drivers/tty/serial/fsl_lpuart.c
> +++ b/drivers/tty/serial/fsl_lpuart.c
> @@ -257,12 +257,17 @@ struct lpuart_port {
>  	struct timer_list	lpuart_timer;
>  };
>  
> +#define QUIRK_LPUART32		BIT(0)
> +#define QUIRK_NO_DMA		BIT(1)
> +
>  static const struct of_device_id lpuart_dt_ids[] = {
>  	{
>  		.compatible = "fsl,vf610-lpuart",
> +		.data = (void *)QUIRK_NO_DMA,
>  	},
>  	{
>  		.compatible = "fsl,ls1021a-lpuart",
> +		.data = (void *)QUIRK_LPUART32,
>  	},
>  	{ /* sentinel */ }
>  };
> @@ -1803,7 +1808,9 @@ static struct uart_driver lpuart_reg = {
>  static int lpuart_probe(struct platform_device *pdev)
>  {
>  	struct device_node *np = pdev->dev.of_node;
> +	const struct of_device_id *match;
>  	struct lpuart_port *sport;
> +	kernel_ulong_t quirks;
>  	struct resource *res;
>  	int ret;
>  
> @@ -1819,7 +1826,10 @@ static int lpuart_probe(struct platform_device *pdev)
>  		return ret;
>  	}
>  	sport->port.line = ret;
> -	sport->lpuart32 = of_device_is_compatible(np, "fsl,ls1021a-lpuart");
> +
> +	match = of_match_node(lpuart_dt_ids, np);
> +	quirks = (kernel_ulong_t)match->data;
> +	sport->lpuart32 = quirks & QUIRK_LPUART32;
>  
>  	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>  	sport->port.membase = devm_ioremap_resource(&pdev->dev, res);
> @@ -1867,15 +1877,21 @@ static int lpuart_probe(struct platform_device *pdev)
>  		return ret;
>  	}
>  
> -	sport->dma_tx_chan = dma_request_slave_channel(sport->port.dev, "tx");
> -	if (!sport->dma_tx_chan)
> -		dev_info(sport->port.dev, "DMA tx channel request failed, "
> -				"operating without tx DMA\n");
> -
> -	sport->dma_rx_chan = dma_request_slave_channel(sport->port.dev, "rx");
> -	if (!sport->dma_rx_chan)
> -		dev_info(sport->port.dev, "DMA rx channel request failed, "
> -				"operating without rx DMA\n");
> +	if (quirks & QUIRK_NO_DMA) {
> +		dev_info(sport->port.dev, "Not using DMA\n");
> +	} else {
> +		sport->dma_tx_chan = dma_request_slave_channel(
> +			sport->port.dev, "tx");
> +		if (!sport->dma_tx_chan)
> +			dev_info(sport->port.dev,
> +				 "DMA tx channel request failed, operating without tx DMA\n");
> +
> +		sport->dma_rx_chan = dma_request_slave_channel(
> +			sport->port.dev, "rx");
> +		if (!sport->dma_rx_chan)
> +			dev_info(sport->port.dev,
> +				 "DMA rx channel request failed, operating without rx DMA\n");
> +	}
>  
>  	return 0;
>  }

[PATCH v5 1/2] serial: fsl_lpuart: Add DMA quirk

[Andrew Lunn]

On Mon, Apr 04, 2016 at 10:01:12PM -0700, Stefan Agner wrote:
> On 2016-04-04 14:53, Andrew Lunn wrote:
> > Using DMA with the vf610 and other Vybrid devices results in a corrupt
> > serial stream. Add a quirk to disable the use of DMA.
> > 
> > Refactor the existing code to add a 32 bit access quirk for the
> > fsl,ls1021a-lpuart.
> 
> Hi Andrew,
> 
> [also added Greg and Jiri, maintainers of the tty subsystem]
> 
> Well, I am not sure if that is the right approach. Quirks are usually
> used to hint to issues in the hardware. However, in this case we deal
> with (a) software issue(s)...

I've been lazy and not investigated what is happening. I'm using the
serial port for console, so don't need performance. However, when it
does corrupt the stream, minicom tends to go crazy, and i have to
reset it to get a working console.

Have you investigated it sufficiently to be sure it is a software
issue?

> At Toradex we were carry a patch which disabled DMA by default using a
> module parameter:
> http://git.toradex.com/cgit/linux-toradex.git/commit/?h=toradex_vf_4.4-next&id=f5baad61b77dd4b0ac0c7beeee284e12d49ba442

Module parameters are frowned upon. Also, once this issue is fixed,
they often leave cruft behind, e.g. in bootloaders configuration. The
advantage of the quirk is that it purely in the driver. When the
driver is fixed, the quirk code can be cleanly removed.

> This allowed to re-enable the DMA easily for testing... Not sure if that
> is the better approach.

If you are testing, you are modifying the driver anyway. It is very
easy to remove the quirk bit to re-enable DMA.

> IMHO we can just omit adding such a disable work around, people lived
> with the current situation since 3.13, one more release probably doesn't
> really matter... :-)

People lived with it by hacking the dts file with empty dma
nodes. Compared to that, a quirk is cleaner.

       Andrew

[PATCH v5 2/2] ARM: dts: vf610-zii-dev: Add ZII development board.

[Andrew Lunn]

From: Cory Tusar <cory.tusar@pid1solutions.com>

This commit adds support for Rev. B of a Zodiac Inflight Innovations
development board, mainly intended for DSA and ARINC 429 development
work.

Signed-off-by: Cory Tusar <cory.tusar@pid1solutions.com>
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Acked-by: Stefan Agner <stefan@agner.ch>
---
v5
 Remove unit address for dsa node
 Removed newline from dsa node
 Fix switch unit address
 Add newlines to dsa child nodes before subchildren
 Renamed regulators
 Sorted node alphabetically
 Removed serial port dma workaround
 Moved status to end of usbdev0 node
 Moved pinctrl_i2c_mux_reset into i2c mux node as a hog
 flattened the iomux structure
 Sorted pinmux children

v4
 Rebase onto 4.6-rc1.

v3
 Remove unused labels
 Replace _ with - in labels.
 Added Acked-by

v2
 Add ZII Copyright
 Dual license
 Remove bootargs and extend stdout-path
 Remove address format from regulator nodes
 Remove extraneous space i2c_3 node
 Move iomuxc to end
 Remove L2 node
 Add missing gpio-controller to gpio6
 Removed unused fixed clocks
 Add an spi node
 Fix memory range
 Fix naming of GPIO i2c expanders
 Disable DMA on serial port, which appears to cause corrupt.

Documentation/devicetree/bindings/net/mdio-mux.txt says:

Required properties for child nodes:
- #address-cells = <1>;
- #size-cells = <0>;
- reg : The sub-bus number.

So i ignored the request to remove these properties.
---
 arch/arm/boot/dts/Makefile                |   3 +-
 arch/arm/boot/dts/vf610-zii-dev-rev-b.dts | 736 ++++++++++++++++++++++++++++++
 2 files changed, 738 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/boot/dts/vf610-zii-dev-rev-b.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 95c1923ce6fa..92074ff300f4 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -388,7 +388,8 @@ dtb-$(CONFIG_SOC_VF610) += \
 	vf610m4-colibri.dtb \
 	vf610-cosmic.dtb \
 	vf610m4-cosmic.dtb \
-	vf610-twr.dtb
+	vf610-twr.dtb \
+	vf610-zii-dev-rev-b.dtb
 dtb-$(CONFIG_ARCH_MXS) += \
 	imx23-evk.dtb \
 	imx23-olinuxino.dtb \
diff --git a/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts b/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts
new file mode 100644
index 000000000000..8c6c2549f49f
--- /dev/null
+++ b/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts
@@ -0,0 +1,736 @@
+/*
+ * Copyright (C) 2015, 2016 Zodiac Inflight Innovations
+ *
+ * Based on an original 'vf610-twr.dts' which is Copyright 2015,
+ * Freescale Semiconductor, Inc.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License
+ *     version 2 as published by the Free Software Foundation.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "vf610.dtsi"
+
+/ {
+	model = "ZII VF610 Development Board, Rev B";
+	compatible = "zii,vf610dev-b", "zii,vf610dev", "fsl,vf610";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory {
+		reg = <0x80000000 0x20000000>;
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+		pinctrl-0 = <&pinctrl_leds_debug>;
+		pinctrl-names = "default";
+
+		debug {
+			label = "zii:green:debug1";
+			gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "heartbeat";
+		};
+	};
+
+	mdio-mux {
+		compatible = "mdio-mux-gpio";
+		pinctrl-0 = <&pinctrl_mdio_mux>;
+		pinctrl-names = "default";
+		gpios = <&gpio0 8  GPIO_ACTIVE_HIGH
+			 &gpio0 9  GPIO_ACTIVE_HIGH
+			 &gpio0 24 GPIO_ACTIVE_HIGH
+			 &gpio0 25 GPIO_ACTIVE_HIGH>;
+		mdio-parent-bus = <&mdio1>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		mdio_mux_1: mdio at 1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		mdio_mux_2: mdio at 2 {
+			reg = <2>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		mdio_mux_4: mdio at 4 {
+			reg = <4>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		mdio_mux_8: mdio at 8 {
+			reg = <8>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+	};
+
+	dsa {
+		compatible = "marvell,dsa";
+		#address-cells = <2>;
+		#size-cells = <0>;
+		dsa,ethernet = <&fec1>;
+		dsa,mii-bus = <&mdio_mux_1>;
+
+		/* 6352 - Primary - 7 ports */
+		switch0: switch at 0-0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x00 0>;
+			eeprom-length = <512>;
+
+			port at 0 {
+				reg = <0>;
+				label = "lan0";
+			};
+
+			port at 1 {
+				reg = <1>;
+				label = "lan1";
+			};
+
+			port at 2 {
+				reg = <2>;
+				label = "lan2";
+			};
+
+			switch0port5: port at 5 {
+				reg = <5>;
+				label = "dsa";
+				phy-mode = "rgmii-txid";
+				link = <&switch1port6
+					&switch2port9>;
+
+				fixed-link {
+					speed = <1000>;
+					full-duplex;
+				};
+			};
+
+			port at 6 {
+				reg = <6>;
+				label = "cpu";
+
+				fixed-link {
+					speed = <100>;
+					full-duplex;
+				};
+			};
+
+		};
+
+		/* 6352 - Secondary - 7 ports */
+		switch1: switch at 0-1 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x00 1>;
+			eeprom-length = <512>;
+			mii-bus = <&mdio_mux_2>;
+
+			port at 0 {
+				reg = <0>;
+				label = "lan3";
+			};
+
+			port at 1 {
+				reg = <1>;
+				label = "lan4";
+			};
+
+			port at 2 {
+				reg = <2>;
+				label = "lan5";
+			};
+
+			switch1port5: port at 5 {
+				reg = <5>;
+				label = "dsa";
+				link = <&switch2port9>;
+				phy-mode = "rgmii-txid";
+
+				fixed-link {
+					speed = <1000>;
+					full-duplex;
+				};
+			};
+
+			switch1port6: port at 6 {
+				reg = <6>;
+				label = "dsa";
+				phy-mode = "rgmii-txid";
+				link = <&switch0port5>;
+
+				fixed-link {
+					speed = <1000>;
+					full-duplex;
+				};
+			};
+		};
+
+		/* 6185 - 10 ports */
+		switch2: switch at 0-2 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x00 2>;
+			mii-bus = <&mdio_mux_4>;
+
+			port at 0 {
+				reg = <0>;
+				label = "lan6";
+			};
+
+			port at 1 {
+				reg = <1>;
+				label = "lan7";
+			};
+
+			port at 2 {
+				reg = <2>;
+				label = "lan8";
+			};
+
+			port at 3 {
+				reg = <3>;
+				label = "optical3";
+
+				fixed-link {
+					speed = <1000>;
+					full-duplex;
+					link-gpios = <&gpio6 2
+						      GPIO_ACTIVE_HIGH>;
+				};
+			};
+
+			port at 4 {
+				reg = <4>;
+				label = "optical4";
+
+				fixed-link {
+					speed = <1000>;
+					full-duplex;
+					link-gpios = <&gpio6 3
+						      GPIO_ACTIVE_HIGH>;
+				};
+			};
+
+			switch2port9: port at 9 {
+				reg = <9>;
+				label = "dsa";
+				phy-mode = "rgmii-txid";
+				link = <&switch1port5
+					&switch0port5>;
+
+				fixed-link {
+					speed = <1000>;
+					full-duplex;
+				};
+			};
+		};
+	};
+
+	reg_vcc_3v3_mcu: regulator-vcc-3v3-mcu {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_3v3_mcu";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+
+	usb0_vbus: regulator-usb0-vbus {
+		compatible = "regulator-fixed";
+		pinctrl-0 = <&pinctrl_usb_vbus>;
+		regulator-name = "usb_vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		enable-active-high;
+		regulator-always-on;
+		regulator-boot-on;
+		gpio = <&gpio0 6 0>;
+	};
+
+	spi0 {
+		compatible = "spi-gpio";
+		pinctrl-0 = <&pinctrl_gpio_spi0>;
+		pinctrl-names = "default";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		gpio-sck  = <&gpio1 12 GPIO_ACTIVE_HIGH>;
+		gpio-mosi = <&gpio1 11 GPIO_ACTIVE_HIGH>;
+		gpio-miso = <&gpio1 10 GPIO_ACTIVE_HIGH>;
+		cs-gpios  = <&gpio1  9 GPIO_ACTIVE_HIGH
+			     &gpio1  8 GPIO_ACTIVE_HIGH>;
+		num-chipselects = <2>;
+
+		m25p128 at 0 {
+			compatible = "m25p128", "jedec,spi-nor";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0>;
+			spi-max-frequency = <1000000>;
+		};
+
+		at93c46d at 1 {
+			compatible = "atmel,at93c46d";
+			pinctrl-0 = <&pinctrl_gpio_e6185_eeprom_sel>;
+			pinctrl-names = "default";
+			#address-cells = <0>;
+			#size-cells = <0>;
+			reg = <1>;
+			spi-max-frequency = <500000>;
+			spi-cs-high;
+			data-size = <16>;
+			select-gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>;
+		};
+	};
+};
+
+&adc0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_adc0_ad5>;
+	vref-supply = <&reg_vcc_3v3_mcu>;
+	status = "okay";
+};
+
+&edma0 {
+	status = "okay";
+};
+
+&esdhc1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_esdhc1>;
+	bus-width = <4>;
+	status = "okay";
+};
+
+&fec0 {
+	phy-mode = "rmii";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_fec0>;
+	status = "okay";
+};
+
+&fec1 {
+	phy-mode = "rmii";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_fec1>;
+	status = "okay";
+
+	fixed-link {
+		   speed = <100>;
+		   full-duplex;
+	};
+
+	mdio1: mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "okay";
+	};
+};
+
+&i2c0 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c0>;
+	status = "okay";
+
+	gpio5: pca9554 at 20 {
+		compatible = "nxp,pca9554";
+		reg = <0x20>;
+		gpio-controller;
+		#gpio-cells = <2>;
+
+	};
+
+	gpio6: pca9554 at 22 {
+		compatible = "nxp,pca9554";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_pca9554_22>;
+		reg = <0x22>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-parent = <&gpio2>;
+		interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+	};
+
+	lm75 at 48 {
+		compatible = "national,lm75";
+		reg = <0x48>;
+	};
+
+	at24c04 at 50 {
+		compatible = "atmel,24c04";
+		reg = <0x50>;
+	};
+
+	at24c04 at 52 {
+		compatible = "atmel,24c04";
+		reg = <0x52>;
+	};
+
+	ds1682 at 6b {
+		compatible = "dallas,ds1682";
+		reg = <0x6b>;
+	};
+};
+
+&i2c1 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c1>;
+	status = "okay";
+};
+
+&i2c2 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c2>;
+	status = "okay";
+
+	tca9548 at 70 {
+		compatible = "nxp,pca9548";
+		pinctrl-0 = <&pinctrl_i2c_mux_reset>;
+		pinctrl-names = "default";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x70>;
+		reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
+
+		i2c at 0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0>;
+
+			sfp1: at24c04 at 50 {
+				compatible = "atmel,24c02";
+				reg = <0x50>;
+			};
+		};
+
+		i2c at 1 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <1>;
+
+			sfp2: at24c04 at 50 {
+				compatible = "atmel,24c02";
+				reg = <0x50>;
+			};
+		};
+
+		i2c at 2 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <2>;
+
+			sfp3: at24c04 at 50 {
+				compatible = "atmel,24c02";
+				reg = <0x50>;
+			};
+		};
+
+		i2c at 3 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <3>;
+
+			sfp4: at24c04 at 50 {
+				compatible = "atmel,24c02";
+				reg = <0x50>;
+			};
+		};
+
+		i2c at 4 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <4>;
+		};
+	};
+};
+
+&i2c3 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c3>;
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl_adc0_ad5: adc0ad5grp {
+		fsl,pins = <
+			VF610_PAD_PTC30__ADC0_SE5	0x00a1
+		>;
+	};
+
+	pinctrl_dspi0: dspi0grp {
+		fsl,pins = <
+			VF610_PAD_PTB18__DSPI0_CS1	0x1182
+			VF610_PAD_PTB19__DSPI0_CS0	0x1182
+			VF610_PAD_PTB20__DSPI0_SIN	0x1181
+			VF610_PAD_PTB21__DSPI0_SOUT	0x1182
+			VF610_PAD_PTB22__DSPI0_SCK	0x1182
+		>;
+	};
+
+	pinctrl_dspi2: dspi2grp {
+		fsl,pins = <
+			VF610_PAD_PTD31__DSPI2_CS1	0x1182
+			VF610_PAD_PTD30__DSPI2_CS0	0x1182
+			VF610_PAD_PTD29__DSPI2_SIN	0x1181
+			VF610_PAD_PTD28__DSPI2_SOUT	0x1182
+			VF610_PAD_PTD27__DSPI2_SCK	0x1182
+		>;
+	};
+
+	pinctrl_esdhc1: esdhc1grp {
+		fsl,pins = <
+			VF610_PAD_PTA24__ESDHC1_CLK	0x31ef
+			VF610_PAD_PTA25__ESDHC1_CMD	0x31ef
+			VF610_PAD_PTA26__ESDHC1_DAT0	0x31ef
+			VF610_PAD_PTA27__ESDHC1_DAT1	0x31ef
+			VF610_PAD_PTA28__ESDHC1_DATA2	0x31ef
+			VF610_PAD_PTA29__ESDHC1_DAT3	0x31ef
+			VF610_PAD_PTA7__GPIO_134	0x219d
+		>;
+	};
+
+	pinctrl_fec0: fec0grp {
+		fsl,pins = <
+			VF610_PAD_PTC0__ENET_RMII0_MDC	0x30d2
+			VF610_PAD_PTC1__ENET_RMII0_MDIO	0x30d3
+			VF610_PAD_PTC2__ENET_RMII0_CRS	0x30d1
+			VF610_PAD_PTC3__ENET_RMII0_RXD1	0x30d1
+			VF610_PAD_PTC4__ENET_RMII0_RXD0	0x30d1
+			VF610_PAD_PTC5__ENET_RMII0_RXER	0x30d1
+			VF610_PAD_PTC6__ENET_RMII0_TXD1	0x30d2
+			VF610_PAD_PTC7__ENET_RMII0_TXD0	0x30d2
+			VF610_PAD_PTC8__ENET_RMII0_TXEN	0x30d2
+		>;
+	};
+
+	pinctrl_fec1: fec1grp {
+		fsl,pins = <
+			VF610_PAD_PTA6__RMII_CLKIN		0x30d1
+			VF610_PAD_PTC9__ENET_RMII1_MDC		0x30d2
+			VF610_PAD_PTC10__ENET_RMII1_MDIO	0x30d3
+			VF610_PAD_PTC11__ENET_RMII1_CRS		0x30d1
+			VF610_PAD_PTC12__ENET_RMII1_RXD1	0x30d1
+			VF610_PAD_PTC13__ENET_RMII1_RXD0	0x30d1
+			VF610_PAD_PTC14__ENET_RMII1_RXER	0x30d1
+			VF610_PAD_PTC15__ENET_RMII1_TXD1	0x30d2
+			VF610_PAD_PTC16__ENET_RMII1_TXD0	0x30d2
+			VF610_PAD_PTC17__ENET_RMII1_TXEN	0x30d2
+		>;
+	};
+
+	pinctrl_gpio_e6185_eeprom_sel: pinctrl-gpio-e6185-eeprom-spi0 {
+		fsl,pins = <
+			VF610_PAD_PTE27__GPIO_132	0x33e2
+		>;
+	};
+
+	pinctrl_gpio_spi0: pinctrl-gpio-spi0 {
+		fsl,pins = <
+			VF610_PAD_PTB22__GPIO_44	0x33e2
+			VF610_PAD_PTB21__GPIO_43	0x33e2
+			VF610_PAD_PTB20__GPIO_42	0x33e1
+			VF610_PAD_PTB19__GPIO_41	0x33e2
+			VF610_PAD_PTB18__GPIO_40	0x33e2
+		>;
+	};
+
+	pinctrl_i2c_mux_reset: pinctrl-i2c-mux-reset {
+		fsl,pins = <
+			 VF610_PAD_PTE14__GPIO_119	0x31c2
+			 >;
+	};
+
+	pinctrl_i2c0: i2c0grp {
+		fsl,pins = <
+			VF610_PAD_PTB14__I2C0_SCL	0x37ff
+			VF610_PAD_PTB15__I2C0_SDA	0x37ff
+		>;
+	};
+
+	pinctrl_i2c1: i2c1grp {
+		fsl,pins = <
+			VF610_PAD_PTB16__I2C1_SCL	0x37ff
+			VF610_PAD_PTB17__I2C1_SDA	0x37ff
+		>;
+	};
+
+	pinctrl_i2c2: i2c2grp {
+		fsl,pins = <
+			VF610_PAD_PTA22__I2C2_SCL	0x37ff
+			VF610_PAD_PTA23__I2C2_SDA	0x37ff
+		>;
+	};
+
+	pinctrl_i2c3: i2c3grp {
+		fsl,pins = <
+			VF610_PAD_PTA30__I2C3_SCL	0x37ff
+			VF610_PAD_PTA31__I2C3_SDA	0x37ff
+		>;
+	};
+
+	pinctrl_leds_debug: pinctrl-leds-debug {
+		fsl,pins = <
+			 VF610_PAD_PTD20__GPIO_74	0x31c2
+			 >;
+	};
+
+	pinctrl_mdio_mux: pinctrl-mdio-mux {
+		fsl,pins = <
+			VF610_PAD_PTA18__GPIO_8		0x31c2
+			VF610_PAD_PTA19__GPIO_9		0x31c2
+			VF610_PAD_PTB2__GPIO_24		0x31c2
+			VF610_PAD_PTB3__GPIO_25		0x31c2
+		>;
+	};
+
+	pinctrl_pca9554_22: pinctrl-pca95540-22 {
+		fsl,pins = <
+			VF610_PAD_PTB28__GPIO_98	0x219d
+		>;
+	};
+
+	pinctrl_pwm0: pwm0grp {
+		fsl,pins = <
+			VF610_PAD_PTB0__FTM0_CH0	0x1582
+			VF610_PAD_PTB1__FTM0_CH1	0x1582
+			VF610_PAD_PTB2__FTM0_CH2	0x1582
+			VF610_PAD_PTB3__FTM0_CH3	0x1582
+		>;
+	};
+
+	pinctrl_qspi0: qspi0grp {
+		fsl,pins = <
+			VF610_PAD_PTD7__QSPI0_B_QSCK	0x31c3
+			VF610_PAD_PTD8__QSPI0_B_CS0	0x31ff
+			VF610_PAD_PTD9__QSPI0_B_DATA3	0x31c3
+			VF610_PAD_PTD10__QSPI0_B_DATA2	0x31c3
+			VF610_PAD_PTD11__QSPI0_B_DATA1	0x31c3
+			VF610_PAD_PTD12__QSPI0_B_DATA0	0x31c3
+		>;
+	};
+
+	pinctrl_uart0: uart0grp {
+		fsl,pins = <
+			VF610_PAD_PTB10__UART0_TX	0x21a2
+			VF610_PAD_PTB11__UART0_RX	0x21a1
+		>;
+	};
+
+	pinctrl_uart1: uart1grp {
+		fsl,pins = <
+			VF610_PAD_PTB23__UART1_TX	0x21a2
+			VF610_PAD_PTB24__UART1_RX	0x21a1
+		>;
+	};
+
+	pinctrl_uart2: uart2grp {
+		fsl,pins = <
+			VF610_PAD_PTD0__UART2_TX	0x21a2
+			VF610_PAD_PTD1__UART2_RX	0x21a1
+		>;
+	};
+
+	pinctrl_usb_vbus: pinctrl-usb-vbus {
+		fsl,pins = <
+			VF610_PAD_PTA16__GPIO_6	0x31c2
+		>;
+	};
+
+	pinctrl_usb0_host: usb0-host-grp {
+		fsl,pins = <
+			VF610_PAD_PTD6__GPIO_85		0x0062
+		>;
+	};
+};
+
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart0>;
+	status = "okay";
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1>;
+	status = "okay";
+};
+
+&uart2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart2>;
+	status = "okay";
+};
+
+&usbdev0 {
+	disable-over-current;
+	vbus-supply = <&usb0_vbus>;
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usbh1 {
+	disable-over-current;
+	status = "okay";
+};
+
+&usbmisc0 {
+	status = "okay";
+};
+
+&usbmisc1 {
+	status = "okay";
+};
+
+&usbphy0 {
+	status = "okay";
+};
+
+&usbphy1 {
+	status = "okay";
+};
+
-- 
2.7.0

[PATCH v5 2/2] ARM: dts: vf610-zii-dev: Add ZII development board.

[Andrew Lunn]

On Mon, Apr 04, 2016 at 11:53:12PM +0200, Andrew Lunn wrote:
> From: Cory Tusar <cory.tusar@pid1solutions.com>
> 
> This commit adds support for Rev. B of a Zodiac Inflight Innovations
> development board, mainly intended for DSA and ARINC 429 development
> work.
> 
> Signed-off-by: Cory Tusar <cory.tusar@pid1solutions.com>
> Signed-off-by: Andrew Lunn <andrew@lunn.ch>
> Acked-by: Stefan Agner <stefan@agner.ch>

Hi Shawn

It seems like the serial driver issues are not making progress.

Could you however take this patch and push it towards arm-soc.

Thanks
	Andrew

> ---
> v5
>  Remove unit address for dsa node
>  Removed newline from dsa node
>  Fix switch unit address
>  Add newlines to dsa child nodes before subchildren
>  Renamed regulators
>  Sorted node alphabetically
>  Removed serial port dma workaround
>  Moved status to end of usbdev0 node
>  Moved pinctrl_i2c_mux_reset into i2c mux node as a hog
>  flattened the iomux structure
>  Sorted pinmux children
> 
> v4
>  Rebase onto 4.6-rc1.
> 
> v3
>  Remove unused labels
>  Replace _ with - in labels.
>  Added Acked-by
> 
> v2
>  Add ZII Copyright
>  Dual license
>  Remove bootargs and extend stdout-path
>  Remove address format from regulator nodes
>  Remove extraneous space i2c_3 node
>  Move iomuxc to end
>  Remove L2 node
>  Add missing gpio-controller to gpio6
>  Removed unused fixed clocks
>  Add an spi node
>  Fix memory range
>  Fix naming of GPIO i2c expanders
>  Disable DMA on serial port, which appears to cause corrupt.
> 
> Documentation/devicetree/bindings/net/mdio-mux.txt says:
> 
> Required properties for child nodes:
> - #address-cells = <1>;
> - #size-cells = <0>;
> - reg : The sub-bus number.
> 
> So i ignored the request to remove these properties.
> ---
>  arch/arm/boot/dts/Makefile                |   3 +-
>  arch/arm/boot/dts/vf610-zii-dev-rev-b.dts | 736 ++++++++++++++++++++++++++++++
>  2 files changed, 738 insertions(+), 1 deletion(-)
>  create mode 100644 arch/arm/boot/dts/vf610-zii-dev-rev-b.dts
> 
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 95c1923ce6fa..92074ff300f4 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -388,7 +388,8 @@ dtb-$(CONFIG_SOC_VF610) += \
>  	vf610m4-colibri.dtb \
>  	vf610-cosmic.dtb \
>  	vf610m4-cosmic.dtb \
> -	vf610-twr.dtb
> +	vf610-twr.dtb \
> +	vf610-zii-dev-rev-b.dtb
>  dtb-$(CONFIG_ARCH_MXS) += \
>  	imx23-evk.dtb \
>  	imx23-olinuxino.dtb \
> diff --git a/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts b/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts
> new file mode 100644
> index 000000000000..8c6c2549f49f
> --- /dev/null
> +++ b/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts
> @@ -0,0 +1,736 @@
> +/*
> + * Copyright (C) 2015, 2016 Zodiac Inflight Innovations
> + *
> + * Based on an original 'vf610-twr.dts' which is Copyright 2015,
> + * Freescale Semiconductor, Inc.
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + *  a) This file is free software; you can redistribute it and/or
> + *     modify it under the terms of the GNU General Public License
> + *     version 2 as published by the Free Software Foundation.
> + *
> + *     This file is distributed in the hope that it will be useful
> + *     but WITHOUT ANY WARRANTY; without even the implied warranty of
> + *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + *     GNU General Public License for more details.
> + *
> + * Or, alternatively
> + *
> + *  b) Permission is hereby granted, free of charge, to any person
> + *     obtaining a copy of this software and associated documentation
> + *     files (the "Software"), to deal in the Software without
> + *     restriction, including without limitation the rights to use
> + *     copy, modify, merge, publish, distribute, sublicense, and/or
> + *     sell copies of the Software, and to permit persons to whom the
> + *     Software is furnished to do so, subject to the following
> + *     conditions:
> + *
> + *     The above copyright notice and this permission notice shall be
> + *     included in all copies or substantial portions of the Software.
> + *
> + *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
> + *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
> + *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + *     OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +/dts-v1/;
> +#include "vf610.dtsi"
> +
> +/ {
> +	model = "ZII VF610 Development Board, Rev B";
> +	compatible = "zii,vf610dev-b", "zii,vf610dev", "fsl,vf610";
> +
> +	chosen {
> +		stdout-path = "serial0:115200n8";
> +	};
> +
> +	memory {
> +		reg = <0x80000000 0x20000000>;
> +	};
> +
> +	gpio-leds {
> +		compatible = "gpio-leds";
> +		pinctrl-0 = <&pinctrl_leds_debug>;
> +		pinctrl-names = "default";
> +
> +		debug {
> +			label = "zii:green:debug1";
> +			gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
> +			linux,default-trigger = "heartbeat";
> +		};
> +	};
> +
> +	mdio-mux {
> +		compatible = "mdio-mux-gpio";
> +		pinctrl-0 = <&pinctrl_mdio_mux>;
> +		pinctrl-names = "default";
> +		gpios = <&gpio0 8  GPIO_ACTIVE_HIGH
> +			 &gpio0 9  GPIO_ACTIVE_HIGH
> +			 &gpio0 24 GPIO_ACTIVE_HIGH
> +			 &gpio0 25 GPIO_ACTIVE_HIGH>;
> +		mdio-parent-bus = <&mdio1>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		mdio_mux_1: mdio at 1 {
> +			reg = <1>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		mdio_mux_2: mdio at 2 {
> +			reg = <2>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		mdio_mux_4: mdio at 4 {
> +			reg = <4>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		mdio_mux_8: mdio at 8 {
> +			reg = <8>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +	};
> +
> +	dsa {
> +		compatible = "marvell,dsa";
> +		#address-cells = <2>;
> +		#size-cells = <0>;
> +		dsa,ethernet = <&fec1>;
> +		dsa,mii-bus = <&mdio_mux_1>;
> +
> +		/* 6352 - Primary - 7 ports */
> +		switch0: switch at 0-0 {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			reg = <0x00 0>;
> +			eeprom-length = <512>;
> +
> +			port at 0 {
> +				reg = <0>;
> +				label = "lan0";
> +			};
> +
> +			port at 1 {
> +				reg = <1>;
> +				label = "lan1";
> +			};
> +
> +			port at 2 {
> +				reg = <2>;
> +				label = "lan2";
> +			};
> +
> +			switch0port5: port at 5 {
> +				reg = <5>;
> +				label = "dsa";
> +				phy-mode = "rgmii-txid";
> +				link = <&switch1port6
> +					&switch2port9>;
> +
> +				fixed-link {
> +					speed = <1000>;
> +					full-duplex;
> +				};
> +			};
> +
> +			port at 6 {
> +				reg = <6>;
> +				label = "cpu";
> +
> +				fixed-link {
> +					speed = <100>;
> +					full-duplex;
> +				};
> +			};
> +
> +		};
> +
> +		/* 6352 - Secondary - 7 ports */
> +		switch1: switch at 0-1 {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			reg = <0x00 1>;
> +			eeprom-length = <512>;
> +			mii-bus = <&mdio_mux_2>;
> +
> +			port at 0 {
> +				reg = <0>;
> +				label = "lan3";
> +			};
> +
> +			port at 1 {
> +				reg = <1>;
> +				label = "lan4";
> +			};
> +
> +			port at 2 {
> +				reg = <2>;
> +				label = "lan5";
> +			};
> +
> +			switch1port5: port at 5 {
> +				reg = <5>;
> +				label = "dsa";
> +				link = <&switch2port9>;
> +				phy-mode = "rgmii-txid";
> +
> +				fixed-link {
> +					speed = <1000>;
> +					full-duplex;
> +				};
> +			};
> +
> +			switch1port6: port at 6 {
> +				reg = <6>;
> +				label = "dsa";
> +				phy-mode = "rgmii-txid";
> +				link = <&switch0port5>;
> +
> +				fixed-link {
> +					speed = <1000>;
> +					full-duplex;
> +				};
> +			};
> +		};
> +
> +		/* 6185 - 10 ports */
> +		switch2: switch at 0-2 {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			reg = <0x00 2>;
> +			mii-bus = <&mdio_mux_4>;
> +
> +			port at 0 {
> +				reg = <0>;
> +				label = "lan6";
> +			};
> +
> +			port at 1 {
> +				reg = <1>;
> +				label = "lan7";
> +			};
> +
> +			port at 2 {
> +				reg = <2>;
> +				label = "lan8";
> +			};
> +
> +			port at 3 {
> +				reg = <3>;
> +				label = "optical3";
> +
> +				fixed-link {
> +					speed = <1000>;
> +					full-duplex;
> +					link-gpios = <&gpio6 2
> +						      GPIO_ACTIVE_HIGH>;
> +				};
> +			};
> +
> +			port at 4 {
> +				reg = <4>;
> +				label = "optical4";
> +
> +				fixed-link {
> +					speed = <1000>;
> +					full-duplex;
> +					link-gpios = <&gpio6 3
> +						      GPIO_ACTIVE_HIGH>;
> +				};
> +			};
> +
> +			switch2port9: port at 9 {
> +				reg = <9>;
> +				label = "dsa";
> +				phy-mode = "rgmii-txid";
> +				link = <&switch1port5
> +					&switch0port5>;
> +
> +				fixed-link {
> +					speed = <1000>;
> +					full-duplex;
> +				};
> +			};
> +		};
> +	};
> +
> +	reg_vcc_3v3_mcu: regulator-vcc-3v3-mcu {
> +		compatible = "regulator-fixed";
> +		regulator-name = "vcc_3v3_mcu";
> +		regulator-min-microvolt = <3300000>;
> +		regulator-max-microvolt = <3300000>;
> +	};
> +
> +	usb0_vbus: regulator-usb0-vbus {
> +		compatible = "regulator-fixed";
> +		pinctrl-0 = <&pinctrl_usb_vbus>;
> +		regulator-name = "usb_vbus";
> +		regulator-min-microvolt = <5000000>;
> +		regulator-max-microvolt = <5000000>;
> +		enable-active-high;
> +		regulator-always-on;
> +		regulator-boot-on;
> +		gpio = <&gpio0 6 0>;
> +	};
> +
> +	spi0 {
> +		compatible = "spi-gpio";
> +		pinctrl-0 = <&pinctrl_gpio_spi0>;
> +		pinctrl-names = "default";
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		gpio-sck  = <&gpio1 12 GPIO_ACTIVE_HIGH>;
> +		gpio-mosi = <&gpio1 11 GPIO_ACTIVE_HIGH>;
> +		gpio-miso = <&gpio1 10 GPIO_ACTIVE_HIGH>;
> +		cs-gpios  = <&gpio1  9 GPIO_ACTIVE_HIGH
> +			     &gpio1  8 GPIO_ACTIVE_HIGH>;
> +		num-chipselects = <2>;
> +
> +		m25p128 at 0 {
> +			compatible = "m25p128", "jedec,spi-nor";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			reg = <0>;
> +			spi-max-frequency = <1000000>;
> +		};
> +
> +		at93c46d at 1 {
> +			compatible = "atmel,at93c46d";
> +			pinctrl-0 = <&pinctrl_gpio_e6185_eeprom_sel>;
> +			pinctrl-names = "default";
> +			#address-cells = <0>;
> +			#size-cells = <0>;
> +			reg = <1>;
> +			spi-max-frequency = <500000>;
> +			spi-cs-high;
> +			data-size = <16>;
> +			select-gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>;
> +		};
> +	};
> +};
> +
> +&adc0 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_adc0_ad5>;
> +	vref-supply = <&reg_vcc_3v3_mcu>;
> +	status = "okay";
> +};
> +
> +&edma0 {
> +	status = "okay";
> +};
> +
> +&esdhc1 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_esdhc1>;
> +	bus-width = <4>;
> +	status = "okay";
> +};
> +
> +&fec0 {
> +	phy-mode = "rmii";
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_fec0>;
> +	status = "okay";
> +};
> +
> +&fec1 {
> +	phy-mode = "rmii";
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_fec1>;
> +	status = "okay";
> +
> +	fixed-link {
> +		   speed = <100>;
> +		   full-duplex;
> +	};
> +
> +	mdio1: mdio {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		status = "okay";
> +	};
> +};
> +
> +&i2c0 {
> +	clock-frequency = <100000>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_i2c0>;
> +	status = "okay";
> +
> +	gpio5: pca9554 at 20 {
> +		compatible = "nxp,pca9554";
> +		reg = <0x20>;
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +
> +	};
> +
> +	gpio6: pca9554 at 22 {
> +		compatible = "nxp,pca9554";
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_pca9554_22>;
> +		reg = <0x22>;
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +		interrupt-parent = <&gpio2>;
> +		interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
> +	};
> +
> +	lm75 at 48 {
> +		compatible = "national,lm75";
> +		reg = <0x48>;
> +	};
> +
> +	at24c04 at 50 {
> +		compatible = "atmel,24c04";
> +		reg = <0x50>;
> +	};
> +
> +	at24c04 at 52 {
> +		compatible = "atmel,24c04";
> +		reg = <0x52>;
> +	};
> +
> +	ds1682 at 6b {
> +		compatible = "dallas,ds1682";
> +		reg = <0x6b>;
> +	};
> +};
> +
> +&i2c1 {
> +	clock-frequency = <100000>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_i2c1>;
> +	status = "okay";
> +};
> +
> +&i2c2 {
> +	clock-frequency = <100000>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_i2c2>;
> +	status = "okay";
> +
> +	tca9548 at 70 {
> +		compatible = "nxp,pca9548";
> +		pinctrl-0 = <&pinctrl_i2c_mux_reset>;
> +		pinctrl-names = "default";
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		reg = <0x70>;
> +		reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
> +
> +		i2c at 0 {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			reg = <0>;
> +
> +			sfp1: at24c04 at 50 {
> +				compatible = "atmel,24c02";
> +				reg = <0x50>;
> +			};
> +		};
> +
> +		i2c at 1 {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			reg = <1>;
> +
> +			sfp2: at24c04 at 50 {
> +				compatible = "atmel,24c02";
> +				reg = <0x50>;
> +			};
> +		};
> +
> +		i2c at 2 {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			reg = <2>;
> +
> +			sfp3: at24c04 at 50 {
> +				compatible = "atmel,24c02";
> +				reg = <0x50>;
> +			};
> +		};
> +
> +		i2c at 3 {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			reg = <3>;
> +
> +			sfp4: at24c04 at 50 {
> +				compatible = "atmel,24c02";
> +				reg = <0x50>;
> +			};
> +		};
> +
> +		i2c at 4 {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			reg = <4>;
> +		};
> +	};
> +};
> +
> +&i2c3 {
> +	clock-frequency = <100000>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_i2c3>;
> +	status = "okay";
> +};
> +
> +&iomuxc {
> +	pinctrl_adc0_ad5: adc0ad5grp {
> +		fsl,pins = <
> +			VF610_PAD_PTC30__ADC0_SE5	0x00a1
> +		>;
> +	};
> +
> +	pinctrl_dspi0: dspi0grp {
> +		fsl,pins = <
> +			VF610_PAD_PTB18__DSPI0_CS1	0x1182
> +			VF610_PAD_PTB19__DSPI0_CS0	0x1182
> +			VF610_PAD_PTB20__DSPI0_SIN	0x1181
> +			VF610_PAD_PTB21__DSPI0_SOUT	0x1182
> +			VF610_PAD_PTB22__DSPI0_SCK	0x1182
> +		>;
> +	};
> +
> +	pinctrl_dspi2: dspi2grp {
> +		fsl,pins = <
> +			VF610_PAD_PTD31__DSPI2_CS1	0x1182
> +			VF610_PAD_PTD30__DSPI2_CS0	0x1182
> +			VF610_PAD_PTD29__DSPI2_SIN	0x1181
> +			VF610_PAD_PTD28__DSPI2_SOUT	0x1182
> +			VF610_PAD_PTD27__DSPI2_SCK	0x1182
> +		>;
> +	};
> +
> +	pinctrl_esdhc1: esdhc1grp {
> +		fsl,pins = <
> +			VF610_PAD_PTA24__ESDHC1_CLK	0x31ef
> +			VF610_PAD_PTA25__ESDHC1_CMD	0x31ef
> +			VF610_PAD_PTA26__ESDHC1_DAT0	0x31ef
> +			VF610_PAD_PTA27__ESDHC1_DAT1	0x31ef
> +			VF610_PAD_PTA28__ESDHC1_DATA2	0x31ef
> +			VF610_PAD_PTA29__ESDHC1_DAT3	0x31ef
> +			VF610_PAD_PTA7__GPIO_134	0x219d
> +		>;
> +	};
> +
> +	pinctrl_fec0: fec0grp {
> +		fsl,pins = <
> +			VF610_PAD_PTC0__ENET_RMII0_MDC	0x30d2
> +			VF610_PAD_PTC1__ENET_RMII0_MDIO	0x30d3
> +			VF610_PAD_PTC2__ENET_RMII0_CRS	0x30d1
> +			VF610_PAD_PTC3__ENET_RMII0_RXD1	0x30d1
> +			VF610_PAD_PTC4__ENET_RMII0_RXD0	0x30d1
> +			VF610_PAD_PTC5__ENET_RMII0_RXER	0x30d1
> +			VF610_PAD_PTC6__ENET_RMII0_TXD1	0x30d2
> +			VF610_PAD_PTC7__ENET_RMII0_TXD0	0x30d2
> +			VF610_PAD_PTC8__ENET_RMII0_TXEN	0x30d2
> +		>;
> +	};
> +
> +	pinctrl_fec1: fec1grp {
> +		fsl,pins = <
> +			VF610_PAD_PTA6__RMII_CLKIN		0x30d1
> +			VF610_PAD_PTC9__ENET_RMII1_MDC		0x30d2
> +			VF610_PAD_PTC10__ENET_RMII1_MDIO	0x30d3
> +			VF610_PAD_PTC11__ENET_RMII1_CRS		0x30d1
> +			VF610_PAD_PTC12__ENET_RMII1_RXD1	0x30d1
> +			VF610_PAD_PTC13__ENET_RMII1_RXD0	0x30d1
> +			VF610_PAD_PTC14__ENET_RMII1_RXER	0x30d1
> +			VF610_PAD_PTC15__ENET_RMII1_TXD1	0x30d2
> +			VF610_PAD_PTC16__ENET_RMII1_TXD0	0x30d2
> +			VF610_PAD_PTC17__ENET_RMII1_TXEN	0x30d2
> +		>;
> +	};
> +
> +	pinctrl_gpio_e6185_eeprom_sel: pinctrl-gpio-e6185-eeprom-spi0 {
> +		fsl,pins = <
> +			VF610_PAD_PTE27__GPIO_132	0x33e2
> +		>;
> +	};
> +
> +	pinctrl_gpio_spi0: pinctrl-gpio-spi0 {
> +		fsl,pins = <
> +			VF610_PAD_PTB22__GPIO_44	0x33e2
> +			VF610_PAD_PTB21__GPIO_43	0x33e2
> +			VF610_PAD_PTB20__GPIO_42	0x33e1
> +			VF610_PAD_PTB19__GPIO_41	0x33e2
> +			VF610_PAD_PTB18__GPIO_40	0x33e2
> +		>;
> +	};
> +
> +	pinctrl_i2c_mux_reset: pinctrl-i2c-mux-reset {
> +		fsl,pins = <
> +			 VF610_PAD_PTE14__GPIO_119	0x31c2
> +			 >;
> +	};
> +
> +	pinctrl_i2c0: i2c0grp {
> +		fsl,pins = <
> +			VF610_PAD_PTB14__I2C0_SCL	0x37ff
> +			VF610_PAD_PTB15__I2C0_SDA	0x37ff
> +		>;
> +	};
> +
> +	pinctrl_i2c1: i2c1grp {
> +		fsl,pins = <
> +			VF610_PAD_PTB16__I2C1_SCL	0x37ff
> +			VF610_PAD_PTB17__I2C1_SDA	0x37ff
> +		>;
> +	};
> +
> +	pinctrl_i2c2: i2c2grp {
> +		fsl,pins = <
> +			VF610_PAD_PTA22__I2C2_SCL	0x37ff
> +			VF610_PAD_PTA23__I2C2_SDA	0x37ff
> +		>;
> +	};
> +
> +	pinctrl_i2c3: i2c3grp {
> +		fsl,pins = <
> +			VF610_PAD_PTA30__I2C3_SCL	0x37ff
> +			VF610_PAD_PTA31__I2C3_SDA	0x37ff
> +		>;
> +	};
> +
> +	pinctrl_leds_debug: pinctrl-leds-debug {
> +		fsl,pins = <
> +			 VF610_PAD_PTD20__GPIO_74	0x31c2
> +			 >;
> +	};
> +
> +	pinctrl_mdio_mux: pinctrl-mdio-mux {
> +		fsl,pins = <
> +			VF610_PAD_PTA18__GPIO_8		0x31c2
> +			VF610_PAD_PTA19__GPIO_9		0x31c2
> +			VF610_PAD_PTB2__GPIO_24		0x31c2
> +			VF610_PAD_PTB3__GPIO_25		0x31c2
> +		>;
> +	};
> +
> +	pinctrl_pca9554_22: pinctrl-pca95540-22 {
> +		fsl,pins = <
> +			VF610_PAD_PTB28__GPIO_98	0x219d
> +		>;
> +	};
> +
> +	pinctrl_pwm0: pwm0grp {
> +		fsl,pins = <
> +			VF610_PAD_PTB0__FTM0_CH0	0x1582
> +			VF610_PAD_PTB1__FTM0_CH1	0x1582
> +			VF610_PAD_PTB2__FTM0_CH2	0x1582
> +			VF610_PAD_PTB3__FTM0_CH3	0x1582
> +		>;
> +	};
> +
> +	pinctrl_qspi0: qspi0grp {
> +		fsl,pins = <
> +			VF610_PAD_PTD7__QSPI0_B_QSCK	0x31c3
> +			VF610_PAD_PTD8__QSPI0_B_CS0	0x31ff
> +			VF610_PAD_PTD9__QSPI0_B_DATA3	0x31c3
> +			VF610_PAD_PTD10__QSPI0_B_DATA2	0x31c3
> +			VF610_PAD_PTD11__QSPI0_B_DATA1	0x31c3
> +			VF610_PAD_PTD12__QSPI0_B_DATA0	0x31c3
> +		>;
> +	};
> +
> +	pinctrl_uart0: uart0grp {
> +		fsl,pins = <
> +			VF610_PAD_PTB10__UART0_TX	0x21a2
> +			VF610_PAD_PTB11__UART0_RX	0x21a1
> +		>;
> +	};
> +
> +	pinctrl_uart1: uart1grp {
> +		fsl,pins = <
> +			VF610_PAD_PTB23__UART1_TX	0x21a2
> +			VF610_PAD_PTB24__UART1_RX	0x21a1
> +		>;
> +	};
> +
> +	pinctrl_uart2: uart2grp {
> +		fsl,pins = <
> +			VF610_PAD_PTD0__UART2_TX	0x21a2
> +			VF610_PAD_PTD1__UART2_RX	0x21a1
> +		>;
> +	};
> +
> +	pinctrl_usb_vbus: pinctrl-usb-vbus {
> +		fsl,pins = <
> +			VF610_PAD_PTA16__GPIO_6	0x31c2
> +		>;
> +	};
> +
> +	pinctrl_usb0_host: usb0-host-grp {
> +		fsl,pins = <
> +			VF610_PAD_PTD6__GPIO_85		0x0062
> +		>;
> +	};
> +};
> +
> +
> +&uart0 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_uart0>;
> +	status = "okay";
> +};
> +
> +&uart1 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_uart1>;
> +	status = "okay";
> +};
> +
> +&uart2 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_uart2>;
> +	status = "okay";
> +};
> +
> +&usbdev0 {
> +	disable-over-current;
> +	vbus-supply = <&usb0_vbus>;
> +	dr_mode = "host";
> +	status = "okay";
> +};
> +
> +&usbh1 {
> +	disable-over-current;
> +	status = "okay";
> +};
> +
> +&usbmisc0 {
> +	status = "okay";
> +};
> +
> +&usbmisc1 {
> +	status = "okay";
> +};
> +
> +&usbphy0 {
> +	status = "okay";
> +};
> +
> +&usbphy1 {
> +	status = "okay";
> +};
> +
> -- 
> 2.7.0
> 

[PATCH v5 2/2] ARM: dts: vf610-zii-dev: Add ZII development board.

[Shawn Guo]

On Mon, Apr 04, 2016 at 11:53:12PM +0200, Andrew Lunn wrote:
> +&iomuxc {

We usually put iomuxc node at the end of the file to make the file a bit
easier for reading.

> +	pinctrl_adc0_ad5: adc0ad5grp {
> +		fsl,pins = <
> +			VF610_PAD_PTC30__ADC0_SE5	0x00a1
> +		>;
> +	};
> +
> +	pinctrl_dspi0: dspi0grp {
> +		fsl,pins = <
> +			VF610_PAD_PTB18__DSPI0_CS1	0x1182
> +			VF610_PAD_PTB19__DSPI0_CS0	0x1182
> +			VF610_PAD_PTB20__DSPI0_SIN	0x1181
> +			VF610_PAD_PTB21__DSPI0_SOUT	0x1182
> +			VF610_PAD_PTB22__DSPI0_SCK	0x1182
> +		>;
> +	};
> +
> +	pinctrl_dspi2: dspi2grp {
> +		fsl,pins = <
> +			VF610_PAD_PTD31__DSPI2_CS1	0x1182
> +			VF610_PAD_PTD30__DSPI2_CS0	0x1182
> +			VF610_PAD_PTD29__DSPI2_SIN	0x1181
> +			VF610_PAD_PTD28__DSPI2_SOUT	0x1182
> +			VF610_PAD_PTD27__DSPI2_SCK	0x1182
> +		>;
> +	};
> +
> +	pinctrl_esdhc1: esdhc1grp {
> +		fsl,pins = <
> +			VF610_PAD_PTA24__ESDHC1_CLK	0x31ef
> +			VF610_PAD_PTA25__ESDHC1_CMD	0x31ef
> +			VF610_PAD_PTA26__ESDHC1_DAT0	0x31ef
> +			VF610_PAD_PTA27__ESDHC1_DAT1	0x31ef
> +			VF610_PAD_PTA28__ESDHC1_DATA2	0x31ef
> +			VF610_PAD_PTA29__ESDHC1_DAT3	0x31ef
> +			VF610_PAD_PTA7__GPIO_134	0x219d
> +		>;
> +	};
> +
> +	pinctrl_fec0: fec0grp {
> +		fsl,pins = <
> +			VF610_PAD_PTC0__ENET_RMII0_MDC	0x30d2
> +			VF610_PAD_PTC1__ENET_RMII0_MDIO	0x30d3
> +			VF610_PAD_PTC2__ENET_RMII0_CRS	0x30d1
> +			VF610_PAD_PTC3__ENET_RMII0_RXD1	0x30d1
> +			VF610_PAD_PTC4__ENET_RMII0_RXD0	0x30d1
> +			VF610_PAD_PTC5__ENET_RMII0_RXER	0x30d1
> +			VF610_PAD_PTC6__ENET_RMII0_TXD1	0x30d2
> +			VF610_PAD_PTC7__ENET_RMII0_TXD0	0x30d2
> +			VF610_PAD_PTC8__ENET_RMII0_TXEN	0x30d2
> +		>;
> +	};
> +
> +	pinctrl_fec1: fec1grp {
> +		fsl,pins = <
> +			VF610_PAD_PTA6__RMII_CLKIN		0x30d1
> +			VF610_PAD_PTC9__ENET_RMII1_MDC		0x30d2
> +			VF610_PAD_PTC10__ENET_RMII1_MDIO	0x30d3
> +			VF610_PAD_PTC11__ENET_RMII1_CRS		0x30d1
> +			VF610_PAD_PTC12__ENET_RMII1_RXD1	0x30d1
> +			VF610_PAD_PTC13__ENET_RMII1_RXD0	0x30d1
> +			VF610_PAD_PTC14__ENET_RMII1_RXER	0x30d1
> +			VF610_PAD_PTC15__ENET_RMII1_TXD1	0x30d2
> +			VF610_PAD_PTC16__ENET_RMII1_TXD0	0x30d2
> +			VF610_PAD_PTC17__ENET_RMII1_TXEN	0x30d2
> +		>;
> +	};
> +
> +	pinctrl_gpio_e6185_eeprom_sel: pinctrl-gpio-e6185-eeprom-spi0 {
> +		fsl,pins = <
> +			VF610_PAD_PTE27__GPIO_132	0x33e2
> +		>;
> +	};
> +
> +	pinctrl_gpio_spi0: pinctrl-gpio-spi0 {
> +		fsl,pins = <
> +			VF610_PAD_PTB22__GPIO_44	0x33e2
> +			VF610_PAD_PTB21__GPIO_43	0x33e2
> +			VF610_PAD_PTB20__GPIO_42	0x33e1
> +			VF610_PAD_PTB19__GPIO_41	0x33e2
> +			VF610_PAD_PTB18__GPIO_40	0x33e2
> +		>;
> +	};
> +
> +	pinctrl_i2c_mux_reset: pinctrl-i2c-mux-reset {
> +		fsl,pins = <
> +			 VF610_PAD_PTE14__GPIO_119	0x31c2
> +			 >;
> +	};
> +
> +	pinctrl_i2c0: i2c0grp {
> +		fsl,pins = <
> +			VF610_PAD_PTB14__I2C0_SCL	0x37ff
> +			VF610_PAD_PTB15__I2C0_SDA	0x37ff
> +		>;
> +	};
> +
> +	pinctrl_i2c1: i2c1grp {
> +		fsl,pins = <
> +			VF610_PAD_PTB16__I2C1_SCL	0x37ff
> +			VF610_PAD_PTB17__I2C1_SDA	0x37ff
> +		>;
> +	};
> +
> +	pinctrl_i2c2: i2c2grp {
> +		fsl,pins = <
> +			VF610_PAD_PTA22__I2C2_SCL	0x37ff
> +			VF610_PAD_PTA23__I2C2_SDA	0x37ff
> +		>;
> +	};
> +
> +	pinctrl_i2c3: i2c3grp {
> +		fsl,pins = <
> +			VF610_PAD_PTA30__I2C3_SCL	0x37ff
> +			VF610_PAD_PTA31__I2C3_SDA	0x37ff
> +		>;
> +	};
> +
> +	pinctrl_leds_debug: pinctrl-leds-debug {
> +		fsl,pins = <
> +			 VF610_PAD_PTD20__GPIO_74	0x31c2
> +			 >;
> +	};
> +
> +	pinctrl_mdio_mux: pinctrl-mdio-mux {
> +		fsl,pins = <
> +			VF610_PAD_PTA18__GPIO_8		0x31c2
> +			VF610_PAD_PTA19__GPIO_9		0x31c2
> +			VF610_PAD_PTB2__GPIO_24		0x31c2
> +			VF610_PAD_PTB3__GPIO_25		0x31c2
> +		>;
> +	};
> +
> +	pinctrl_pca9554_22: pinctrl-pca95540-22 {
> +		fsl,pins = <
> +			VF610_PAD_PTB28__GPIO_98	0x219d
> +		>;
> +	};
> +
> +	pinctrl_pwm0: pwm0grp {
> +		fsl,pins = <
> +			VF610_PAD_PTB0__FTM0_CH0	0x1582
> +			VF610_PAD_PTB1__FTM0_CH1	0x1582
> +			VF610_PAD_PTB2__FTM0_CH2	0x1582
> +			VF610_PAD_PTB3__FTM0_CH3	0x1582
> +		>;
> +	};
> +
> +	pinctrl_qspi0: qspi0grp {
> +		fsl,pins = <
> +			VF610_PAD_PTD7__QSPI0_B_QSCK	0x31c3
> +			VF610_PAD_PTD8__QSPI0_B_CS0	0x31ff
> +			VF610_PAD_PTD9__QSPI0_B_DATA3	0x31c3
> +			VF610_PAD_PTD10__QSPI0_B_DATA2	0x31c3
> +			VF610_PAD_PTD11__QSPI0_B_DATA1	0x31c3
> +			VF610_PAD_PTD12__QSPI0_B_DATA0	0x31c3
> +		>;
> +	};
> +
> +	pinctrl_uart0: uart0grp {
> +		fsl,pins = <
> +			VF610_PAD_PTB10__UART0_TX	0x21a2
> +			VF610_PAD_PTB11__UART0_RX	0x21a1
> +		>;
> +	};
> +
> +	pinctrl_uart1: uart1grp {
> +		fsl,pins = <
> +			VF610_PAD_PTB23__UART1_TX	0x21a2
> +			VF610_PAD_PTB24__UART1_RX	0x21a1
> +		>;
> +	};
> +
> +	pinctrl_uart2: uart2grp {
> +		fsl,pins = <
> +			VF610_PAD_PTD0__UART2_TX	0x21a2
> +			VF610_PAD_PTD1__UART2_RX	0x21a1
> +		>;
> +	};
> +
> +	pinctrl_usb_vbus: pinctrl-usb-vbus {
> +		fsl,pins = <
> +			VF610_PAD_PTA16__GPIO_6	0x31c2
> +		>;
> +	};
> +
> +	pinctrl_usb0_host: usb0-host-grp {
> +		fsl,pins = <
> +			VF610_PAD_PTD6__GPIO_85		0x0062
> +		>;
> +	};
> +};
> +
> +

One new line is enough.

> +&uart0 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_uart0>;
> +	status = "okay";
> +};
> +
> +&uart1 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_uart1>;
> +	status = "okay";
> +};
> +
> +&uart2 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_uart2>;
> +	status = "okay";
> +};
> +
> +&usbdev0 {
> +	disable-over-current;
> +	vbus-supply = <&usb0_vbus>;
> +	dr_mode = "host";
> +	status = "okay";
> +};
> +
> +&usbh1 {
> +	disable-over-current;
> +	status = "okay";
> +};
> +
> +&usbmisc0 {
> +	status = "okay";
> +};
> +
> +&usbmisc1 {
> +	status = "okay";
> +};
> +
> +&usbphy0 {
> +	status = "okay";
> +};
> +
> +&usbphy1 {
> +	status = "okay";
> +};
> +

No newline at EOF.

All above comments are trivial, so I decided to fix them up and apply
the patch.

Shawn

> -- 
> 2.7.0
> 
> 

[PATCH v5 2/2] ARM: dts: vf610-zii-dev: Add ZII development board.

[Andrew Lunn]

On Tue, Apr 12, 2016 at 02:38:02PM +0800, Shawn Guo wrote:
> On Mon, Apr 04, 2016 at 11:53:12PM +0200, Andrew Lunn wrote:
> > +&iomuxc {
> 
> We usually put iomuxc node at the end of the file to make the file a bit
> easier for reading.

Hi Shawn

You asked me to sort the nodes, so i did.
 
> All above comments are trivial, so I decided to fix them up and apply
> the patch.

Great, thanks.

Any comments on the serial port issue? Quirk vs module parameter?

Thanks
	Andrew