From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>, Intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915/gen8+: Do not enable DPF interrupt since the handler does not exist
Date: Tue, 19 Apr 2016 16:33:14 +0300 [thread overview]
Message-ID: <20160419133314.GS4329@intel.com> (raw)
In-Reply-To: <1461072411-30750-1-git-send-email-tvrtko.ursulin@linux.intel.com>
On Tue, Apr 19, 2016 at 02:26:51PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> Looks like DPF was not implemented for gen8+ but the IER and IMR
> are still enabled on initialization.
>
> Since there is no code to handle this interrupt, gate the irq
> enablement behind HAS_L3_DPF in case the feature gets enabled
> in the future.
In addition to hooking it up in the irq handler, we'd need to
use the w/a BB to do the remapping when execlists are enabled IIRC.
Patch is
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> drivers/gpu/drm/i915/i915_irq.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 93da4feb3048..2f6fd33c07ba 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -3796,7 +3796,6 @@ static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
> uint32_t gt_interrupts[] = {
> GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
> GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
> - GT_RENDER_L3_PARITY_ERROR_INTERRUPT |
> GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT |
> GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
> GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
> @@ -3808,6 +3807,9 @@ static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
> GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT
> };
>
> + if (HAS_L3_DPF(dev_priv))
> + gt_interrupts[0] |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
> +
> dev_priv->pm_irq_mask = 0xffffffff;
> GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]);
> GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]);
> --
> 1.9.1
--
Ville Syrjälä
Intel OTC
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next prev parent reply other threads:[~2016-04-19 13:33 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-04-19 13:26 [PATCH] drm/i915/gen8+: Do not enable DPF interrupt since the handler does not exist Tvrtko Ursulin
2016-04-19 13:33 ` Ville Syrjälä [this message]
2016-04-19 14:27 ` ✗ Fi.CI.BAT: failure for " Patchwork
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