From: Thierry Reding <thierry.reding@gmail.com>
To: Lucas Stach <dev@lynxeye.de>
Cc: Peter De Schrijver <pdeschrijver@nvidia.com>,
Prashant Gaikwad <pgaikwad@nvidia.com>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@codeaurora.org>,
Stephen Warren <swarren@wwwdotorg.org>,
Alexandre Courbot <gnurou@gmail.com>,
linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org
Subject: Re: [PATCH 1/2] clk: tegra30: init PLL_C to sane rate
Date: Fri, 22 Apr 2016 13:52:56 +0200 [thread overview]
Message-ID: <20160422115256.GE9047@ulmo.ba.sec> (raw)
In-Reply-To: <1456778767-18413-1-git-send-email-dev@lynxeye.de>
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On Mon, Feb 29, 2016 at 09:46:06PM +0100, Lucas Stach wrote:
> If the bootloader does not touch PLL_C it will stay in its reset
> state, failing to lock when enabled. This leads to consumers of
> this clock to fail probing. Fix this by always programming the
> PLL with a sane rate, which allows it to lock, at startup.
>
> Signed-off-by: Lucas Stach <dev@lynxeye.de>
> ---
> drivers/clk/tegra/clk-tegra30.c | 1 +
> 1 file changed, 1 insertion(+)
Applied, thanks.
Thierry
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prev parent reply other threads:[~2016-04-22 11:52 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-02-29 20:46 [PATCH 1/2] clk: tegra30: init PLL_C to sane rate Lucas Stach
2016-02-29 20:46 ` Lucas Stach
2016-02-29 20:46 ` [PATCH 2/2] clk: tegra30: fix PLL_U post divider and init rate Lucas Stach
2016-02-29 20:46 ` Lucas Stach
2016-04-22 11:53 ` Thierry Reding
2016-04-22 11:53 ` Thierry Reding
2016-04-21 18:16 ` [PATCH 1/2] clk: tegra30: init PLL_C to sane rate Lucas Stach
2016-04-21 18:16 ` Lucas Stach
2016-04-22 11:52 ` Thierry Reding [this message]
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