From: Thierry Reding <thierry.reding@gmail.com>
To: Lucas Stach <dev@lynxeye.de>
Cc: Peter De Schrijver <pdeschrijver@nvidia.com>,
Prashant Gaikwad <pgaikwad@nvidia.com>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@codeaurora.org>,
Stephen Warren <swarren@wwwdotorg.org>,
Alexandre Courbot <gnurou@gmail.com>,
linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org
Subject: Re: [PATCH 2/2] clk: tegra30: fix PLL_U post divider and init rate
Date: Fri, 22 Apr 2016 13:53:14 +0200 [thread overview]
Message-ID: <20160422115314.GF9047@ulmo.ba.sec> (raw)
In-Reply-To: <1456778767-18413-2-git-send-email-dev@lynxeye.de>
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On Mon, Feb 29, 2016 at 09:46:07PM +0100, Lucas Stach wrote:
> The post divider value in the frequency table is wrong as it
> would lead to the PLL producing a output rate of 960MHz instead
> of the desired 480MHz. This wasn't a problem as nothing used the
> table to actually init the PLL rate, but the bootloader
> configuration was used unaltered.
>
> If the bootloader does not set up the PLL it will fail to come
> when used under Linux. To fix this don't rely on the bootloader,
> but set the correct rate in the clock driver.
>
> Signed-off-by: Lucas Stach <dev@lynxeye.de>
> ---
> drivers/clk/tegra/clk-tegra30.c | 11 ++++++-----
> 1 file changed, 6 insertions(+), 5 deletions(-)
Applied, thanks.
Thierry
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WARNING: multiple messages have this Message-ID (diff)
From: Thierry Reding <thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
To: Lucas Stach <dev-8ppwABl0HbeELgA04lAiVw@public.gmane.org>
Cc: Peter De Schrijver
<pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>,
Prashant Gaikwad
<pgaikwad-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>,
Michael Turquette
<mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>,
Stephen Boyd <sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>,
Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>,
Alexandre Courbot
<gnurou-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Subject: Re: [PATCH 2/2] clk: tegra30: fix PLL_U post divider and init rate
Date: Fri, 22 Apr 2016 13:53:14 +0200 [thread overview]
Message-ID: <20160422115314.GF9047@ulmo.ba.sec> (raw)
In-Reply-To: <1456778767-18413-2-git-send-email-dev-8ppwABl0HbeELgA04lAiVw@public.gmane.org>
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On Mon, Feb 29, 2016 at 09:46:07PM +0100, Lucas Stach wrote:
> The post divider value in the frequency table is wrong as it
> would lead to the PLL producing a output rate of 960MHz instead
> of the desired 480MHz. This wasn't a problem as nothing used the
> table to actually init the PLL rate, but the bootloader
> configuration was used unaltered.
>
> If the bootloader does not set up the PLL it will fail to come
> when used under Linux. To fix this don't rely on the bootloader,
> but set the correct rate in the clock driver.
>
> Signed-off-by: Lucas Stach <dev-8ppwABl0HbeELgA04lAiVw@public.gmane.org>
> ---
> drivers/clk/tegra/clk-tegra30.c | 11 ++++++-----
> 1 file changed, 6 insertions(+), 5 deletions(-)
Applied, thanks.
Thierry
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next prev parent reply other threads:[~2016-04-22 11:53 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-02-29 20:46 [PATCH 1/2] clk: tegra30: init PLL_C to sane rate Lucas Stach
2016-02-29 20:46 ` Lucas Stach
2016-02-29 20:46 ` [PATCH 2/2] clk: tegra30: fix PLL_U post divider and init rate Lucas Stach
2016-02-29 20:46 ` Lucas Stach
2016-04-22 11:53 ` Thierry Reding [this message]
2016-04-22 11:53 ` Thierry Reding
2016-04-21 18:16 ` [PATCH 1/2] clk: tegra30: init PLL_C to sane rate Lucas Stach
2016-04-21 18:16 ` Lucas Stach
2016-04-22 11:52 ` Thierry Reding
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