[PATCH] advsync: fix trivial typos

[PATCH] advsync: fix trivial typos

[SeongJae Park]

Earlier two commits to advsync/memorybarriers.tex file, commit
8de1474e3282 ("Add larger multiple-value-write scenario") and commit
514f21cd4156 ("Add caveats to the Software Logic Analyzer") has made few
trivial typos.  This commit fixes them.

Signed-off-by: SeongJae Park <sj38.park@gmail.com>
---
 advsync/memorybarriers.tex | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/advsync/memorybarriers.tex b/advsync/memorybarriers.tex
index cc39d2d..a0ef76d 100644
--- a/advsync/memorybarriers.tex
+++ b/advsync/memorybarriers.tex
@@ -363,7 +363,7 @@ consistent with the increase in number of CPUs.
 The remaining 15 columns in the table record the values most recently
 observed by the corresponding CPU at each point in time, with changes
 in value marked by italics and parentheses.
-Again, CPU 0 coordinates the test, so does not record any values.
+Again, CPU~0 coordinates the test, so does not record any values.

 \begin{table*}[htbp]
 \scriptsize
@@ -508,7 +508,7 @@ We have entered a regime where we must bid a fond farewell to
 comfortable intuitions about values of variables and the passage of time.
 This is the regime where memory barriers are needed.

-All that aside, is is important to remember the lessons from
+All that aside, it is important to remember the lessons from
 Chapters~\ref{chp:Hardware and its Habits}
 and~\ref{cha:Partitioning and Synchronization Design}.
 Having all CPUs write concurrently to the same variable
-- 
1.9.1

Re: [PATCH] advsync: fix trivial typos

[Paul E. McKenney]

On Tue, Apr 26, 2016 at 10:22:30AM +0900, SeongJae Park wrote:
> Earlier two commits to advsync/memorybarriers.tex file, commit
> 8de1474e3282 ("Add larger multiple-value-write scenario") and commit
> 514f21cd4156 ("Add caveats to the Software Logic Analyzer") has made few
> trivial typos.  This commit fixes them.
> 
> Signed-off-by: SeongJae Park <sj38.park@gmail.com>

Good eyes!  Queued and pushed.

							Thanx, Paul

> ---
>  advsync/memorybarriers.tex | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/advsync/memorybarriers.tex b/advsync/memorybarriers.tex
> index cc39d2d..a0ef76d 100644
> --- a/advsync/memorybarriers.tex
> +++ b/advsync/memorybarriers.tex
> @@ -363,7 +363,7 @@ consistent with the increase in number of CPUs.
>  The remaining 15 columns in the table record the values most recently
>  observed by the corresponding CPU at each point in time, with changes
>  in value marked by italics and parentheses.
> -Again, CPU 0 coordinates the test, so does not record any values.
> +Again, CPU~0 coordinates the test, so does not record any values.
> 
>  \begin{table*}[htbp]
>  \scriptsize
> @@ -508,7 +508,7 @@ We have entered a regime where we must bid a fond farewell to
>  comfortable intuitions about values of variables and the passage of time.
>  This is the regime where memory barriers are needed.
> 
> -All that aside, is is important to remember the lessons from
> +All that aside, it is important to remember the lessons from
>  Chapters~\ref{chp:Hardware and its Habits}
>  and~\ref{cha:Partitioning and Synchronization Design}.
>  Having all CPUs write concurrently to the same variable
> -- 
> 1.9.1
>