* [PATCH 0/2] ARM: dts: sunxi: Add display clocks to sun[47]i.dtsi @ 2016-05-10 19:24 ` Priit Laes 0 siblings, 0 replies; 11+ messages in thread From: Priit Laes @ 2016-05-10 19:24 UTC (permalink / raw) To: linux-arm-kernel Enable the display and TCON clocks that are needed to drive the display engine, tcon and TV encoders. Please note that currently the parent handling for clocks using 'allwinner,sun4i-a10-display-clk' compatible with number of parents !=4 is broken (like de_[bf]e[01]_clk clocks present in patches). Priit Laes (2): ARM: sun4i: A10: Add display and TCON clocks ARM: sun7i: A20: Add display and TCON clocks arch/arm/boot/dts/sun4i-a10.dtsi | 91 ++++++++++++++++++++++++++++++++++++---- arch/arm/boot/dts/sun7i-a20.dtsi | 85 ++++++++++++++++++++++++++++++++++--- 2 files changed, 164 insertions(+), 12 deletions(-) -- 2.8.2 ^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 0/2] ARM: dts: sunxi: Add display clocks to sun[47]i.dtsi @ 2016-05-10 19:24 ` Priit Laes 0 siblings, 0 replies; 11+ messages in thread From: Priit Laes @ 2016-05-10 19:24 UTC (permalink / raw) To: Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Russell King, Maxime Ripard, Chen-Yu Tsai, Emilio López, Michael Turquette, Stephen Boyd Cc: devicetree, linux-arm-kernel, linux-kernel, linux-sunxi, Priit Laes Enable the display and TCON clocks that are needed to drive the display engine, tcon and TV encoders. Please note that currently the parent handling for clocks using 'allwinner,sun4i-a10-display-clk' compatible with number of parents !=4 is broken (like de_[bf]e[01]_clk clocks present in patches). Priit Laes (2): ARM: sun4i: A10: Add display and TCON clocks ARM: sun7i: A20: Add display and TCON clocks arch/arm/boot/dts/sun4i-a10.dtsi | 91 ++++++++++++++++++++++++++++++++++++---- arch/arm/boot/dts/sun7i-a20.dtsi | 85 ++++++++++++++++++++++++++++++++++--- 2 files changed, 164 insertions(+), 12 deletions(-) -- 2.8.2 ^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 1/2] ARM: sun4i: A10: Add display and TCON clocks @ 2016-05-10 19:24 ` Priit Laes 0 siblings, 0 replies; 11+ messages in thread From: Priit Laes @ 2016-05-10 19:24 UTC (permalink / raw) To: linux-arm-kernel Enable the display and TCON clocks that are needed to drive the display engine, tcon and TV encoders. Signed-off-by: Priit Laes <plaes@plaes.org> --- arch/arm/boot/dts/sun4i-a10.dtsi | 91 ++++++++++++++++++++++++++++++++++++---- 1 file changed, 84 insertions(+), 7 deletions(-) diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index a03e56f..a9c3190 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -65,8 +65,8 @@ compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_be0-lcd0-hdmi"; - clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>, - <&ahb_gates 44>, <&dram_gates 26>; + clocks = <&ahb_gates 36>, <&ahb_gates 43>, <&ahb_gates 44>, + <&de_be0_clk>, <&tcon0_ch0_clk>, <&dram_gates 26>; status = "disabled"; }; @@ -74,8 +74,9 @@ compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi"; - clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>, + clocks = <&ahb_gates 36>, <&ahb_gates 43>, <&ahb_gates 44>, <&ahb_gates 46>, + <&de_be0_clk>, <&de_fe0_clk>, <&tcon0_ch0_clk>, <&dram_gates 25>, <&dram_gates 26>; status = "disabled"; }; @@ -84,9 +85,9 @@ compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_fe0-de_be0-lcd0"; - clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>, - <&ahb_gates 46>, <&dram_gates 25>, - <&dram_gates 26>; + clocks = <&ahb_gates 36>, <&ahb_gates 44>, <&ahb_gates 46>, + <&de_be0_clk>, <&de_fe0_clk>, <&tcon0_ch0_clk>, + <&dram_gates 25>, <&dram_gates 26>; status = "disabled"; }; @@ -94,8 +95,9 @@ compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0"; - clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>, + clocks = <&ahb_gates 34>, <&ahb_gates 36>, <&ahb_gates 44>, <&ahb_gates 46>, + <&de_be0_clk>, <&de_fe0_clk>, <&tcon0_ch0_clk>, <&dram_gates 5>, <&dram_gates 25>, <&dram_gates 26>; status = "disabled"; }; @@ -574,6 +576,81 @@ "dram_de_mp", "dram_ace"; }; + de_be0_clk: clk at 01c20104 { + #clock-cells = <0>; + #reset-cells = <0>; + compatible = "allwinner,sun4i-a10-display-clk"; + reg = <0x01c20104 0x4>; + clocks = <&pll3>, <&pll7>, <&pll5 1>; + clock-output-names = "de-be0"; + }; + + de_be1_clk: clk at 01c20108 { + #clock-cells = <0>; + #reset-cells = <0>; + compatible = "allwinner,sun4i-a10-display-clk"; + reg = <0x01c20108 0x4>; + clocks = <&pll3>, <&pll7>, <&pll5 1>; + clock-output-names = "de-be1"; + }; + + de_fe0_clk: clk at 01c2010c { + #clock-cells = <0>; + #reset-cells = <0>; + compatible = "allwinner,sun4i-a10-display-clk"; + reg = <0x01c2010c 0x4>; + clocks = <&pll3>, <&pll7>, <&pll5 1>; + clock-output-names = "de-fe0"; + }; + + de_fe1_clk: clk at 01c20110 { + #clock-cells = <0>; + #reset-cells = <0>; + compatible = "allwinner,sun4i-a10-display-clk"; + reg = <0x01c20110 0x4>; + clocks = <&pll3>, <&pll7>, <&pll5 1>; + clock-output-names = "de-fe1"; + }; + + + tcon0_ch0_clk: clk at 01c20118 { + #clock-cells = <0>; + #reset-cells = <1>; + compatible = "allwinner,sun4i-a10-tcon-ch0-clk"; + reg = <0x01c20118 0x4>; + clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; + clock-output-names = "tcon0-ch0-sclk"; + + }; + + tcon1_ch0_clk: clk at 01c2011c { + #clock-cells = <0>; + #reset-cells = <1>; + compatible = "allwinner,sun4i-a10-tcon-ch1-clk"; + reg = <0x01c2011c 0x4>; + clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; + clock-output-names = "tcon1-ch0-sclk"; + + }; + + tcon0_ch1_clk: clk at 01c2012c { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-tcon-ch0-clk"; + reg = <0x01c2012c 0x4>; + clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; + clock-output-names = "tcon0-ch1-sclk"; + + }; + + tcon1_ch1_clk: clk at 01c20130 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-tcon-ch1-clk"; + reg = <0x01c20130 0x4>; + clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; + clock-output-names = "tcon1-ch1-sclk"; + + }; + ve_clk: clk at 01c2013c { #clock-cells = <0>; #reset-cells = <0>; -- 2.8.2 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 1/2] ARM: sun4i: A10: Add display and TCON clocks @ 2016-05-10 19:24 ` Priit Laes 0 siblings, 0 replies; 11+ messages in thread From: Priit Laes @ 2016-05-10 19:24 UTC (permalink / raw) To: Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Russell King, Maxime Ripard, Chen-Yu Tsai, Emilio López, Michael Turquette, Stephen Boyd Cc: devicetree, linux-arm-kernel, linux-kernel, linux-sunxi, Priit Laes Enable the display and TCON clocks that are needed to drive the display engine, tcon and TV encoders. Signed-off-by: Priit Laes <plaes@plaes.org> --- arch/arm/boot/dts/sun4i-a10.dtsi | 91 ++++++++++++++++++++++++++++++++++++---- 1 file changed, 84 insertions(+), 7 deletions(-) diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index a03e56f..a9c3190 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -65,8 +65,8 @@ compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_be0-lcd0-hdmi"; - clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>, - <&ahb_gates 44>, <&dram_gates 26>; + clocks = <&ahb_gates 36>, <&ahb_gates 43>, <&ahb_gates 44>, + <&de_be0_clk>, <&tcon0_ch0_clk>, <&dram_gates 26>; status = "disabled"; }; @@ -74,8 +74,9 @@ compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi"; - clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>, + clocks = <&ahb_gates 36>, <&ahb_gates 43>, <&ahb_gates 44>, <&ahb_gates 46>, + <&de_be0_clk>, <&de_fe0_clk>, <&tcon0_ch0_clk>, <&dram_gates 25>, <&dram_gates 26>; status = "disabled"; }; @@ -84,9 +85,9 @@ compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_fe0-de_be0-lcd0"; - clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>, - <&ahb_gates 46>, <&dram_gates 25>, - <&dram_gates 26>; + clocks = <&ahb_gates 36>, <&ahb_gates 44>, <&ahb_gates 46>, + <&de_be0_clk>, <&de_fe0_clk>, <&tcon0_ch0_clk>, + <&dram_gates 25>, <&dram_gates 26>; status = "disabled"; }; @@ -94,8 +95,9 @@ compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0"; - clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>, + clocks = <&ahb_gates 34>, <&ahb_gates 36>, <&ahb_gates 44>, <&ahb_gates 46>, + <&de_be0_clk>, <&de_fe0_clk>, <&tcon0_ch0_clk>, <&dram_gates 5>, <&dram_gates 25>, <&dram_gates 26>; status = "disabled"; }; @@ -574,6 +576,81 @@ "dram_de_mp", "dram_ace"; }; + de_be0_clk: clk@01c20104 { + #clock-cells = <0>; + #reset-cells = <0>; + compatible = "allwinner,sun4i-a10-display-clk"; + reg = <0x01c20104 0x4>; + clocks = <&pll3>, <&pll7>, <&pll5 1>; + clock-output-names = "de-be0"; + }; + + de_be1_clk: clk@01c20108 { + #clock-cells = <0>; + #reset-cells = <0>; + compatible = "allwinner,sun4i-a10-display-clk"; + reg = <0x01c20108 0x4>; + clocks = <&pll3>, <&pll7>, <&pll5 1>; + clock-output-names = "de-be1"; + }; + + de_fe0_clk: clk@01c2010c { + #clock-cells = <0>; + #reset-cells = <0>; + compatible = "allwinner,sun4i-a10-display-clk"; + reg = <0x01c2010c 0x4>; + clocks = <&pll3>, <&pll7>, <&pll5 1>; + clock-output-names = "de-fe0"; + }; + + de_fe1_clk: clk@01c20110 { + #clock-cells = <0>; + #reset-cells = <0>; + compatible = "allwinner,sun4i-a10-display-clk"; + reg = <0x01c20110 0x4>; + clocks = <&pll3>, <&pll7>, <&pll5 1>; + clock-output-names = "de-fe1"; + }; + + + tcon0_ch0_clk: clk@01c20118 { + #clock-cells = <0>; + #reset-cells = <1>; + compatible = "allwinner,sun4i-a10-tcon-ch0-clk"; + reg = <0x01c20118 0x4>; + clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; + clock-output-names = "tcon0-ch0-sclk"; + + }; + + tcon1_ch0_clk: clk@01c2011c { + #clock-cells = <0>; + #reset-cells = <1>; + compatible = "allwinner,sun4i-a10-tcon-ch1-clk"; + reg = <0x01c2011c 0x4>; + clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; + clock-output-names = "tcon1-ch0-sclk"; + + }; + + tcon0_ch1_clk: clk@01c2012c { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-tcon-ch0-clk"; + reg = <0x01c2012c 0x4>; + clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; + clock-output-names = "tcon0-ch1-sclk"; + + }; + + tcon1_ch1_clk: clk@01c20130 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-tcon-ch1-clk"; + reg = <0x01c20130 0x4>; + clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; + clock-output-names = "tcon1-ch1-sclk"; + + }; + ve_clk: clk@01c2013c { #clock-cells = <0>; #reset-cells = <0>; -- 2.8.2 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 1/2] ARM: sun4i: A10: Add display and TCON clocks @ 2016-05-10 19:24 ` Priit Laes 0 siblings, 0 replies; 11+ messages in thread From: Priit Laes @ 2016-05-10 19:24 UTC (permalink / raw) To: Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Russell King, Maxime Ripard, Chen-Yu Tsai, Emilio López, Michael Turquette, Stephen Boyd Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, linux-kernel-u79uwXL29TY76Z2rM5mHXA, linux-sunxi-/JYPxA39Uh5TLH3MbocFFw, Priit Laes Enable the display and TCON clocks that are needed to drive the display engine, tcon and TV encoders. Signed-off-by: Priit Laes <plaes-q/aMd4JkU83YtjvyW6yDsg@public.gmane.org> --- arch/arm/boot/dts/sun4i-a10.dtsi | 91 ++++++++++++++++++++++++++++++++++++---- 1 file changed, 84 insertions(+), 7 deletions(-) diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index a03e56f..a9c3190 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -65,8 +65,8 @@ compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_be0-lcd0-hdmi"; - clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>, - <&ahb_gates 44>, <&dram_gates 26>; + clocks = <&ahb_gates 36>, <&ahb_gates 43>, <&ahb_gates 44>, + <&de_be0_clk>, <&tcon0_ch0_clk>, <&dram_gates 26>; status = "disabled"; }; @@ -74,8 +74,9 @@ compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi"; - clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>, + clocks = <&ahb_gates 36>, <&ahb_gates 43>, <&ahb_gates 44>, <&ahb_gates 46>, + <&de_be0_clk>, <&de_fe0_clk>, <&tcon0_ch0_clk>, <&dram_gates 25>, <&dram_gates 26>; status = "disabled"; }; @@ -84,9 +85,9 @@ compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_fe0-de_be0-lcd0"; - clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>, - <&ahb_gates 46>, <&dram_gates 25>, - <&dram_gates 26>; + clocks = <&ahb_gates 36>, <&ahb_gates 44>, <&ahb_gates 46>, + <&de_be0_clk>, <&de_fe0_clk>, <&tcon0_ch0_clk>, + <&dram_gates 25>, <&dram_gates 26>; status = "disabled"; }; @@ -94,8 +95,9 @@ compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0"; - clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>, + clocks = <&ahb_gates 34>, <&ahb_gates 36>, <&ahb_gates 44>, <&ahb_gates 46>, + <&de_be0_clk>, <&de_fe0_clk>, <&tcon0_ch0_clk>, <&dram_gates 5>, <&dram_gates 25>, <&dram_gates 26>; status = "disabled"; }; @@ -574,6 +576,81 @@ "dram_de_mp", "dram_ace"; }; + de_be0_clk: clk@01c20104 { + #clock-cells = <0>; + #reset-cells = <0>; + compatible = "allwinner,sun4i-a10-display-clk"; + reg = <0x01c20104 0x4>; + clocks = <&pll3>, <&pll7>, <&pll5 1>; + clock-output-names = "de-be0"; + }; + + de_be1_clk: clk@01c20108 { + #clock-cells = <0>; + #reset-cells = <0>; + compatible = "allwinner,sun4i-a10-display-clk"; + reg = <0x01c20108 0x4>; + clocks = <&pll3>, <&pll7>, <&pll5 1>; + clock-output-names = "de-be1"; + }; + + de_fe0_clk: clk@01c2010c { + #clock-cells = <0>; + #reset-cells = <0>; + compatible = "allwinner,sun4i-a10-display-clk"; + reg = <0x01c2010c 0x4>; + clocks = <&pll3>, <&pll7>, <&pll5 1>; + clock-output-names = "de-fe0"; + }; + + de_fe1_clk: clk@01c20110 { + #clock-cells = <0>; + #reset-cells = <0>; + compatible = "allwinner,sun4i-a10-display-clk"; + reg = <0x01c20110 0x4>; + clocks = <&pll3>, <&pll7>, <&pll5 1>; + clock-output-names = "de-fe1"; + }; + + + tcon0_ch0_clk: clk@01c20118 { + #clock-cells = <0>; + #reset-cells = <1>; + compatible = "allwinner,sun4i-a10-tcon-ch0-clk"; + reg = <0x01c20118 0x4>; + clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; + clock-output-names = "tcon0-ch0-sclk"; + + }; + + tcon1_ch0_clk: clk@01c2011c { + #clock-cells = <0>; + #reset-cells = <1>; + compatible = "allwinner,sun4i-a10-tcon-ch1-clk"; + reg = <0x01c2011c 0x4>; + clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; + clock-output-names = "tcon1-ch0-sclk"; + + }; + + tcon0_ch1_clk: clk@01c2012c { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-tcon-ch0-clk"; + reg = <0x01c2012c 0x4>; + clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; + clock-output-names = "tcon0-ch1-sclk"; + + }; + + tcon1_ch1_clk: clk@01c20130 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-tcon-ch1-clk"; + reg = <0x01c20130 0x4>; + clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; + clock-output-names = "tcon1-ch1-sclk"; + + }; + ve_clk: clk@01c2013c { #clock-cells = <0>; #reset-cells = <0>; -- 2.8.2 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 2/2] ARM: sun7i: A20: Add display and TCON clocks @ 2016-05-10 19:24 ` Priit Laes 0 siblings, 0 replies; 11+ messages in thread From: Priit Laes @ 2016-05-10 19:24 UTC (permalink / raw) To: linux-arm-kernel Enable the display and TCON clocks that are needed to drive the display engine, tcon and TV encoders. Signed-off-by: Priit Laes <plaes@plaes.org> --- arch/arm/boot/dts/sun7i-a20.dtsi | 85 +++++++++++++++++++++++++++++++++++++--- 1 file changed, 80 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index febdf4c..82e28c3 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -67,8 +67,8 @@ compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_be0-lcd0-hdmi"; - clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>, - <&ahb_gates 44>, <&dram_gates 26>; + clocks = <&ahb_gates 36>, <&ahb_gates 43>, <&ahb_gates 44>, + <&de_be0_clk>, <&tcon0_ch0_clk>, <&dram_gates 26>; status = "disabled"; }; @@ -76,7 +76,8 @@ compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_be0-lcd0"; - clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>, + clocks = <&ahb_gates 36>, <&ahb_gates 44>, + <&de_be0_clk>, <&tcon0_ch0_clk>, <&dram_gates 26>; status = "disabled"; }; @@ -85,8 +86,8 @@ compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_be0-lcd0-tve0"; - clocks = <&pll5 1>, - <&ahb_gates 34>, <&ahb_gates 36>, <&ahb_gates 44>, + clocks = <&ahb_gates 34>, <&ahb_gates 36>, <&ahb_gates 44>, + <&de_be0_clk>, <&tcon0_ch0_clk>, <&dram_gates 5>, <&dram_gates 26>; status = "disabled"; }; @@ -580,6 +581,80 @@ "dram_de_mp", "dram_ace"; }; + de_be0_clk: clk at 01c20104 { + #clock-cells = <0>; + #reset-cells = <0>; + compatible = "allwinner,sun4i-a10-display-clk"; + reg = <0x01c20104 0x4>; + clocks = <&pll3>, <&pll7>, <&pll5 1>; + clock-output-names = "de-be0"; + }; + + de_be1_clk: clk at 01c20108 { + #clock-cells = <0>; + #reset-cells = <0>; + compatible = "allwinner,sun4i-a10-display-clk"; + reg = <0x01c20108 0x4>; + clocks = <&pll3>, <&pll7>, <&pll5 1>; + clock-output-names = "de-be1"; + }; + + de_fe0_clk: clk at 01c2010c { + #clock-cells = <0>; + #reset-cells = <0>; + compatible = "allwinner,sun4i-a10-display-clk"; + reg = <0x01c2010c 0x4>; + clocks = <&pll3>, <&pll7>, <&pll5 1>; + clock-output-names = "de-fe0"; + }; + + de_fe1_clk: clk at 01c20110 { + #clock-cells = <0>; + #reset-cells = <0>; + compatible = "allwinner,sun4i-a10-display-clk"; + reg = <0x01c20110 0x4>; + clocks = <&pll3>, <&pll7>, <&pll5 1>; + clock-output-names = "de-fe1"; + }; + + tcon0_ch0_clk: clk at 01c20118 { + #clock-cells = <0>; + #reset-cells = <1>; + compatible = "allwinner,sun4i-a10-tcon-ch0-clk"; + reg = <0x01c20118 0x4>; + clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; + clock-output-names = "tcon0-ch0-sclk"; + + }; + + tcon1_ch0_clk: clk at 01c2011c { + #clock-cells = <0>; + #reset-cells = <1>; + compatible = "allwinner,sun4i-a10-tcon-ch1-clk"; + reg = <0x01c2011c 0x4>; + clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; + clock-output-names = "tcon1-ch0-sclk"; + + }; + + tcon0_ch1_clk: clk at 01c2012c { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-tcon-ch0-clk"; + reg = <0x01c2012c 0x4>; + clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; + clock-output-names = "tcon0-ch1-sclk"; + + }; + + tcon1_ch1_clk: clk at 01c20130 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-tcon-ch1-clk"; + reg = <0x01c20130 0x4>; + clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; + clock-output-names = "tcon1-ch1-sclk"; + + }; + ve_clk: clk at 01c2013c { #clock-cells = <0>; #reset-cells = <0>; -- 2.8.2 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 2/2] ARM: sun7i: A20: Add display and TCON clocks @ 2016-05-10 19:24 ` Priit Laes 0 siblings, 0 replies; 11+ messages in thread From: Priit Laes @ 2016-05-10 19:24 UTC (permalink / raw) To: Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Russell King, Maxime Ripard, Chen-Yu Tsai, Emilio López, Michael Turquette, Stephen Boyd Cc: devicetree, linux-arm-kernel, linux-kernel, linux-sunxi, Priit Laes Enable the display and TCON clocks that are needed to drive the display engine, tcon and TV encoders. Signed-off-by: Priit Laes <plaes@plaes.org> --- arch/arm/boot/dts/sun7i-a20.dtsi | 85 +++++++++++++++++++++++++++++++++++++--- 1 file changed, 80 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index febdf4c..82e28c3 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -67,8 +67,8 @@ compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_be0-lcd0-hdmi"; - clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>, - <&ahb_gates 44>, <&dram_gates 26>; + clocks = <&ahb_gates 36>, <&ahb_gates 43>, <&ahb_gates 44>, + <&de_be0_clk>, <&tcon0_ch0_clk>, <&dram_gates 26>; status = "disabled"; }; @@ -76,7 +76,8 @@ compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_be0-lcd0"; - clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>, + clocks = <&ahb_gates 36>, <&ahb_gates 44>, + <&de_be0_clk>, <&tcon0_ch0_clk>, <&dram_gates 26>; status = "disabled"; }; @@ -85,8 +86,8 @@ compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_be0-lcd0-tve0"; - clocks = <&pll5 1>, - <&ahb_gates 34>, <&ahb_gates 36>, <&ahb_gates 44>, + clocks = <&ahb_gates 34>, <&ahb_gates 36>, <&ahb_gates 44>, + <&de_be0_clk>, <&tcon0_ch0_clk>, <&dram_gates 5>, <&dram_gates 26>; status = "disabled"; }; @@ -580,6 +581,80 @@ "dram_de_mp", "dram_ace"; }; + de_be0_clk: clk@01c20104 { + #clock-cells = <0>; + #reset-cells = <0>; + compatible = "allwinner,sun4i-a10-display-clk"; + reg = <0x01c20104 0x4>; + clocks = <&pll3>, <&pll7>, <&pll5 1>; + clock-output-names = "de-be0"; + }; + + de_be1_clk: clk@01c20108 { + #clock-cells = <0>; + #reset-cells = <0>; + compatible = "allwinner,sun4i-a10-display-clk"; + reg = <0x01c20108 0x4>; + clocks = <&pll3>, <&pll7>, <&pll5 1>; + clock-output-names = "de-be1"; + }; + + de_fe0_clk: clk@01c2010c { + #clock-cells = <0>; + #reset-cells = <0>; + compatible = "allwinner,sun4i-a10-display-clk"; + reg = <0x01c2010c 0x4>; + clocks = <&pll3>, <&pll7>, <&pll5 1>; + clock-output-names = "de-fe0"; + }; + + de_fe1_clk: clk@01c20110 { + #clock-cells = <0>; + #reset-cells = <0>; + compatible = "allwinner,sun4i-a10-display-clk"; + reg = <0x01c20110 0x4>; + clocks = <&pll3>, <&pll7>, <&pll5 1>; + clock-output-names = "de-fe1"; + }; + + tcon0_ch0_clk: clk@01c20118 { + #clock-cells = <0>; + #reset-cells = <1>; + compatible = "allwinner,sun4i-a10-tcon-ch0-clk"; + reg = <0x01c20118 0x4>; + clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; + clock-output-names = "tcon0-ch0-sclk"; + + }; + + tcon1_ch0_clk: clk@01c2011c { + #clock-cells = <0>; + #reset-cells = <1>; + compatible = "allwinner,sun4i-a10-tcon-ch1-clk"; + reg = <0x01c2011c 0x4>; + clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; + clock-output-names = "tcon1-ch0-sclk"; + + }; + + tcon0_ch1_clk: clk@01c2012c { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-tcon-ch0-clk"; + reg = <0x01c2012c 0x4>; + clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; + clock-output-names = "tcon0-ch1-sclk"; + + }; + + tcon1_ch1_clk: clk@01c20130 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-tcon-ch1-clk"; + reg = <0x01c20130 0x4>; + clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; + clock-output-names = "tcon1-ch1-sclk"; + + }; + ve_clk: clk@01c2013c { #clock-cells = <0>; #reset-cells = <0>; -- 2.8.2 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 2/2] ARM: sun7i: A20: Add display and TCON clocks @ 2016-05-10 19:24 ` Priit Laes 0 siblings, 0 replies; 11+ messages in thread From: Priit Laes @ 2016-05-10 19:24 UTC (permalink / raw) To: Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Russell King, Maxime Ripard, Chen-Yu Tsai, Emilio López, Michael Turquette, Stephen Boyd Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, linux-kernel-u79uwXL29TY76Z2rM5mHXA, linux-sunxi-/JYPxA39Uh5TLH3MbocFFw, Priit Laes Enable the display and TCON clocks that are needed to drive the display engine, tcon and TV encoders. Signed-off-by: Priit Laes <plaes-q/aMd4JkU83YtjvyW6yDsg@public.gmane.org> --- arch/arm/boot/dts/sun7i-a20.dtsi | 85 +++++++++++++++++++++++++++++++++++++--- 1 file changed, 80 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index febdf4c..82e28c3 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -67,8 +67,8 @@ compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_be0-lcd0-hdmi"; - clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>, - <&ahb_gates 44>, <&dram_gates 26>; + clocks = <&ahb_gates 36>, <&ahb_gates 43>, <&ahb_gates 44>, + <&de_be0_clk>, <&tcon0_ch0_clk>, <&dram_gates 26>; status = "disabled"; }; @@ -76,7 +76,8 @@ compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_be0-lcd0"; - clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>, + clocks = <&ahb_gates 36>, <&ahb_gates 44>, + <&de_be0_clk>, <&tcon0_ch0_clk>, <&dram_gates 26>; status = "disabled"; }; @@ -85,8 +86,8 @@ compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_be0-lcd0-tve0"; - clocks = <&pll5 1>, - <&ahb_gates 34>, <&ahb_gates 36>, <&ahb_gates 44>, + clocks = <&ahb_gates 34>, <&ahb_gates 36>, <&ahb_gates 44>, + <&de_be0_clk>, <&tcon0_ch0_clk>, <&dram_gates 5>, <&dram_gates 26>; status = "disabled"; }; @@ -580,6 +581,80 @@ "dram_de_mp", "dram_ace"; }; + de_be0_clk: clk@01c20104 { + #clock-cells = <0>; + #reset-cells = <0>; + compatible = "allwinner,sun4i-a10-display-clk"; + reg = <0x01c20104 0x4>; + clocks = <&pll3>, <&pll7>, <&pll5 1>; + clock-output-names = "de-be0"; + }; + + de_be1_clk: clk@01c20108 { + #clock-cells = <0>; + #reset-cells = <0>; + compatible = "allwinner,sun4i-a10-display-clk"; + reg = <0x01c20108 0x4>; + clocks = <&pll3>, <&pll7>, <&pll5 1>; + clock-output-names = "de-be1"; + }; + + de_fe0_clk: clk@01c2010c { + #clock-cells = <0>; + #reset-cells = <0>; + compatible = "allwinner,sun4i-a10-display-clk"; + reg = <0x01c2010c 0x4>; + clocks = <&pll3>, <&pll7>, <&pll5 1>; + clock-output-names = "de-fe0"; + }; + + de_fe1_clk: clk@01c20110 { + #clock-cells = <0>; + #reset-cells = <0>; + compatible = "allwinner,sun4i-a10-display-clk"; + reg = <0x01c20110 0x4>; + clocks = <&pll3>, <&pll7>, <&pll5 1>; + clock-output-names = "de-fe1"; + }; + + tcon0_ch0_clk: clk@01c20118 { + #clock-cells = <0>; + #reset-cells = <1>; + compatible = "allwinner,sun4i-a10-tcon-ch0-clk"; + reg = <0x01c20118 0x4>; + clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; + clock-output-names = "tcon0-ch0-sclk"; + + }; + + tcon1_ch0_clk: clk@01c2011c { + #clock-cells = <0>; + #reset-cells = <1>; + compatible = "allwinner,sun4i-a10-tcon-ch1-clk"; + reg = <0x01c2011c 0x4>; + clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; + clock-output-names = "tcon1-ch0-sclk"; + + }; + + tcon0_ch1_clk: clk@01c2012c { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-tcon-ch0-clk"; + reg = <0x01c2012c 0x4>; + clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; + clock-output-names = "tcon0-ch1-sclk"; + + }; + + tcon1_ch1_clk: clk@01c20130 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-tcon-ch1-clk"; + reg = <0x01c20130 0x4>; + clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; + clock-output-names = "tcon1-ch1-sclk"; + + }; + ve_clk: clk@01c2013c { #clock-cells = <0>; #reset-cells = <0>; -- 2.8.2 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 0/2] ARM: dts: sunxi: Add display clocks to sun[47]i.dtsi @ 2016-05-11 19:12 ` Maxime Ripard 0 siblings, 0 replies; 11+ messages in thread From: Maxime Ripard @ 2016-05-11 19:12 UTC (permalink / raw) To: linux-arm-kernel On Tue, May 10, 2016 at 10:24:05PM +0300, Priit Laes wrote: > Enable the display and TCON clocks that are needed to drive the display > engine, tcon and TV encoders. > > Please note that currently the parent handling for clocks using > 'allwinner,sun4i-a10-display-clk' compatible with number of parents !=4 > is broken (like de_[bf]e[01]_clk clocks present in patches). > > Priit Laes (2): > ARM: sun4i: A10: Add display and TCON clocks > ARM: sun7i: A20: Add display and TCON clocks Applied both for 4.8, thanks! Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 819 bytes Desc: not available URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20160511/291b88ba/attachment.sig> ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 0/2] ARM: dts: sunxi: Add display clocks to sun[47]i.dtsi @ 2016-05-11 19:12 ` Maxime Ripard 0 siblings, 0 replies; 11+ messages in thread From: Maxime Ripard @ 2016-05-11 19:12 UTC (permalink / raw) To: Priit Laes Cc: Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Russell King, Chen-Yu Tsai, Emilio López, Michael Turquette, Stephen Boyd, devicetree, linux-arm-kernel, linux-kernel, linux-sunxi [-- Attachment #1: Type: text/plain, Size: 657 bytes --] On Tue, May 10, 2016 at 10:24:05PM +0300, Priit Laes wrote: > Enable the display and TCON clocks that are needed to drive the display > engine, tcon and TV encoders. > > Please note that currently the parent handling for clocks using > 'allwinner,sun4i-a10-display-clk' compatible with number of parents !=4 > is broken (like de_[bf]e[01]_clk clocks present in patches). > > Priit Laes (2): > ARM: sun4i: A10: Add display and TCON clocks > ARM: sun7i: A20: Add display and TCON clocks Applied both for 4.8, thanks! Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 819 bytes --] ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 0/2] ARM: dts: sunxi: Add display clocks to sun[47]i.dtsi @ 2016-05-11 19:12 ` Maxime Ripard 0 siblings, 0 replies; 11+ messages in thread From: Maxime Ripard @ 2016-05-11 19:12 UTC (permalink / raw) To: Priit Laes Cc: Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Russell King, Chen-Yu Tsai, Emilio López, Michael Turquette, Stephen Boyd, devicetree-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, linux-kernel-u79uwXL29TY76Z2rM5mHXA, linux-sunxi-/JYPxA39Uh5TLH3MbocFFw [-- Attachment #1: Type: text/plain, Size: 637 bytes --] On Tue, May 10, 2016 at 10:24:05PM +0300, Priit Laes wrote: > Enable the display and TCON clocks that are needed to drive the display > engine, tcon and TV encoders. > > Please note that currently the parent handling for clocks using > 'allwinner,sun4i-a10-display-clk' compatible with number of parents !=4 > is broken (like de_[bf]e[01]_clk clocks present in patches). > > Priit Laes (2): > ARM: sun4i: A10: Add display and TCON clocks > ARM: sun7i: A20: Add display and TCON clocks Applied both for 4.8, thanks! Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com ^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2016-05-11 19:12 UTC | newest] Thread overview: 11+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2016-05-10 19:24 [PATCH 0/2] ARM: dts: sunxi: Add display clocks to sun[47]i.dtsi Priit Laes 2016-05-10 19:24 ` Priit Laes 2016-05-10 19:24 ` [PATCH 1/2] ARM: sun4i: A10: Add display and TCON clocks Priit Laes 2016-05-10 19:24 ` Priit Laes 2016-05-10 19:24 ` Priit Laes 2016-05-10 19:24 ` [PATCH 2/2] ARM: sun7i: A20: " Priit Laes 2016-05-10 19:24 ` Priit Laes 2016-05-10 19:24 ` Priit Laes 2016-05-11 19:12 ` [PATCH 0/2] ARM: dts: sunxi: Add display clocks to sun[47]i.dtsi Maxime Ripard 2016-05-11 19:12 ` Maxime Ripard 2016-05-11 19:12 ` Maxime Ripard
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