From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: Laurent Desnogues <laurent.desnogues@gmail.com>,
qemu-arm@nongnu.org, qemu-devel@nongnu.org, patches@linaro.org
Subject: Re: [Qemu-devel] [PATCH 1/2] target-arm: Set IL bit in syndromes for insn abort, watchpoint, swstep
Date: Tue, 17 May 2016 14:50:58 +0200 [thread overview]
Message-ID: <20160517125058.GU3731@toto> (raw)
In-Reply-To: <1463487258-27468-2-git-send-email-peter.maydell@linaro.org>
On Tue, May 17, 2016 at 01:14:17PM +0100, Peter Maydell wrote:
> For some exception syndrome types, the IL bit should always be set.
> This includes the instruction abort, watchpoint and software step
> syndrome types; add the missing ARM_EL_IL bit to the syndrome
> values returned by syn_insn_abort(), syn_swstep() and syn_watchpoint().
Hi,
Maybe we should have a reference in a comment to the table in
the pseudo code for AArch64.ExceptionClass?
It makes it a little easier to understand some of these settings...
Either way:
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Cheers,
Edgar
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> target-arm/internals.h | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/target-arm/internals.h b/target-arm/internals.h
> index 54a0fb1..7768a24 100644
> --- a/target-arm/internals.h
> +++ b/target-arm/internals.h
> @@ -382,7 +382,7 @@ static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_16bit)
> static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int fsc)
> {
> return (EC_INSNABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
> - | (ea << 9) | (s1ptw << 7) | fsc;
> + | ARM_EL_IL | (ea << 9) | (s1ptw << 7) | fsc;
> }
>
> static inline uint32_t syn_data_abort_no_iss(int same_el,
> @@ -411,13 +411,13 @@ static inline uint32_t syn_data_abort_with_iss(int same_el,
> static inline uint32_t syn_swstep(int same_el, int isv, int ex)
> {
> return (EC_SOFTWARESTEP << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
> - | (isv << 24) | (ex << 6) | 0x22;
> + | ARM_EL_IL | (isv << 24) | (ex << 6) | 0x22;
> }
>
> static inline uint32_t syn_watchpoint(int same_el, int cm, int wnr)
> {
> return (EC_WATCHPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
> - | (cm << 8) | (wnr << 6) | 0x22;
> + | ARM_EL_IL | (cm << 8) | (wnr << 6) | 0x22;
> }
>
> static inline uint32_t syn_breakpoint(int same_el)
> --
> 1.9.1
>
WARNING: multiple messages have this Message-ID (diff)
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, patches@linaro.org,
Laurent Desnogues <laurent.desnogues@gmail.com>
Subject: Re: [Qemu-devel] [PATCH 1/2] target-arm: Set IL bit in syndromes for insn abort, watchpoint, swstep
Date: Tue, 17 May 2016 14:50:58 +0200 [thread overview]
Message-ID: <20160517125058.GU3731@toto> (raw)
In-Reply-To: <1463487258-27468-2-git-send-email-peter.maydell@linaro.org>
On Tue, May 17, 2016 at 01:14:17PM +0100, Peter Maydell wrote:
> For some exception syndrome types, the IL bit should always be set.
> This includes the instruction abort, watchpoint and software step
> syndrome types; add the missing ARM_EL_IL bit to the syndrome
> values returned by syn_insn_abort(), syn_swstep() and syn_watchpoint().
Hi,
Maybe we should have a reference in a comment to the table in
the pseudo code for AArch64.ExceptionClass?
It makes it a little easier to understand some of these settings...
Either way:
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Cheers,
Edgar
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> target-arm/internals.h | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/target-arm/internals.h b/target-arm/internals.h
> index 54a0fb1..7768a24 100644
> --- a/target-arm/internals.h
> +++ b/target-arm/internals.h
> @@ -382,7 +382,7 @@ static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_16bit)
> static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int fsc)
> {
> return (EC_INSNABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
> - | (ea << 9) | (s1ptw << 7) | fsc;
> + | ARM_EL_IL | (ea << 9) | (s1ptw << 7) | fsc;
> }
>
> static inline uint32_t syn_data_abort_no_iss(int same_el,
> @@ -411,13 +411,13 @@ static inline uint32_t syn_data_abort_with_iss(int same_el,
> static inline uint32_t syn_swstep(int same_el, int isv, int ex)
> {
> return (EC_SOFTWARESTEP << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
> - | (isv << 24) | (ex << 6) | 0x22;
> + | ARM_EL_IL | (isv << 24) | (ex << 6) | 0x22;
> }
>
> static inline uint32_t syn_watchpoint(int same_el, int cm, int wnr)
> {
> return (EC_WATCHPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
> - | (cm << 8) | (wnr << 6) | 0x22;
> + | ARM_EL_IL | (cm << 8) | (wnr << 6) | 0x22;
> }
>
> static inline uint32_t syn_breakpoint(int same_el)
> --
> 1.9.1
>
next prev parent reply other threads:[~2016-05-17 12:51 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-05-17 12:14 [Qemu-arm] [PATCH 0/2] target-arm: ESR IL bit fixes Peter Maydell
2016-05-17 12:14 ` [Qemu-devel] " Peter Maydell
2016-05-17 12:14 ` [Qemu-arm] [PATCH 1/2] target-arm: Set IL bit in syndromes for insn abort, watchpoint, swstep Peter Maydell
2016-05-17 12:14 ` [Qemu-devel] " Peter Maydell
2016-05-17 12:50 ` Edgar E. Iglesias [this message]
2016-05-17 12:50 ` Edgar E. Iglesias
2016-05-17 13:06 ` [Qemu-arm] " Peter Maydell
2016-05-17 13:06 ` [Qemu-devel] " Peter Maydell
2016-05-17 13:12 ` Edgar E. Iglesias
2016-05-17 13:12 ` Edgar E. Iglesias
2016-05-17 12:14 ` [Qemu-arm] [PATCH 2/2] target-arm: Don't try to set ESR IL bit in arm_cpu_do_interrupt_aarch64() Peter Maydell
2016-05-17 12:14 ` [Qemu-devel] " Peter Maydell
2016-05-17 12:51 ` Edgar E. Iglesias
2016-05-17 12:51 ` Edgar E. Iglesias
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