From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Intel Graphics Development <intel-gfx@lists.freedesktop.org>,
Daniel Vetter <daniel.vetter@intel.com>,
stable <stable@vger.kernel.org>,
"Pandiyan, Dhinakaran" <dhinakaran.pandiyan@intel.com>,
Rodrigo Vivi <rodrigo.vivi@intel.com>
Subject: Re: [Intel-gfx] [PATCH 2/7] drm/i915/psr: Try to program link training times correctly
Date: Wed, 18 May 2016 21:09:49 +0300 [thread overview]
Message-ID: <20160518180949.GC4329@intel.com> (raw)
In-Reply-To: <CAKMK7uGdvG95HsKMy71aExc0LkxGVo09ArCg1+ACDkd-V6fXGA@mail.gmail.com>
On Wed, May 18, 2016 at 08:04:02PM +0200, Daniel Vetter wrote:
> On Wed, May 18, 2016 at 7:39 PM, Ville Syrjälä
> <ville.syrjala@linux.intel.com> wrote:
> > On Wed, May 18, 2016 at 06:47:11PM +0200, Daniel Vetter wrote:
> >> Oops. Hw default for programming these fields to 0 is "skip link
> >> training". Display won't take that too well usually.
> >
> > s/skip/500 usec/
>
> Yeah, my reading skills have reached an all time low ;-) But we
> confirmed on irc that the hardcoded 500usec was indeed wrong, since
> the fixed machines now run on 2.5ms of link training time. I'll update
> the commit message when merging to reflect that. Also
>
> Tested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
That can be slapped onto the entire series.
> Tested-by: fritsch@kodi.tv
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch
--
Ville Syrjälä
Intel OTC
WARNING: multiple messages have this Message-ID (diff)
From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Intel Graphics Development <intel-gfx@lists.freedesktop.org>,
Daniel Vetter <daniel.vetter@intel.com>,
stable <stable@vger.kernel.org>,
"Pandiyan, Dhinakaran" <dhinakaran.pandiyan@intel.com>,
Rodrigo Vivi <rodrigo.vivi@intel.com>
Subject: Re: [Intel-gfx] [PATCH 2/7] drm/i915/psr: Try to program link training times correctly
Date: Wed, 18 May 2016 21:09:49 +0300 [thread overview]
Message-ID: <20160518180949.GC4329@intel.com> (raw)
In-Reply-To: <CAKMK7uGdvG95HsKMy71aExc0LkxGVo09ArCg1+ACDkd-V6fXGA@mail.gmail.com>
On Wed, May 18, 2016 at 08:04:02PM +0200, Daniel Vetter wrote:
> On Wed, May 18, 2016 at 7:39 PM, Ville Syrj�l�
> <ville.syrjala@linux.intel.com> wrote:
> > On Wed, May 18, 2016 at 06:47:11PM +0200, Daniel Vetter wrote:
> >> Oops. Hw default for programming these fields to 0 is "skip link
> >> training". Display won't take that too well usually.
> >
> > s/skip/500 usec/
>
> Yeah, my reading skills have reached an all time low ;-) But we
> confirmed on irc that the hardcoded 500usec was indeed wrong, since
> the fixed machines now run on 2.5ms of link training time. I'll update
> the commit message when merging to reflect that. Also
>
> Tested-by: Ville Syrj�l� <ville.syrjala@linux.intel.com>
That can be slapped onto the entire series.
> Tested-by: fritsch@kodi.tv
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch
--
Ville Syrj�l�
Intel OTC
next prev parent reply other threads:[~2016-05-18 18:09 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-05-18 16:47 [PATCH 1/7] drm/i915: Enable edp psr error interrupts on hsw Daniel Vetter
2016-05-18 16:47 ` [PATCH 2/7] drm/i915/psr: Try to program link training times correctly Daniel Vetter
2016-05-18 17:39 ` [Intel-gfx] " Ville Syrjälä
2016-05-18 17:39 ` Ville Syrjälä
2016-05-18 18:04 ` Daniel Vetter
2016-05-18 18:09 ` Ville Syrjälä [this message]
2016-05-18 18:09 ` Ville Syrjälä
2016-05-19 10:50 ` Jindal, Sonika
2016-05-20 7:33 ` Daniel Vetter
2016-05-20 7:33 ` Daniel Vetter
2016-05-18 16:47 ` [PATCH 3/7] drm/i915/psr: Make idle_frames sensible again Daniel Vetter
2016-05-18 17:46 ` Ville Syrjälä
2016-05-25 22:52 ` Rodrigo Vivi
2016-05-18 16:47 ` [PATCH 4/7] drm/i915/psr: Skip aux handeshake if the vbt tells us to Daniel Vetter
2016-05-18 17:47 ` Ville Syrjälä
2016-05-18 16:47 ` [PATCH 5/7] drm/i915/psr: Order DP aux transactions correctly Daniel Vetter
2016-05-18 17:51 ` Ville Syrjälä
2016-05-18 16:47 ` [PATCH 6/7] drm/i915/psr: Use ->get_aux_send_ctl functions Daniel Vetter
2016-05-18 18:09 ` Ville Syrjälä
2016-05-18 16:47 ` [PATCH 7/7] drm/i915/psr: Implement PSR2 w/a for skl/kbl Daniel Vetter
2016-05-18 18:22 ` Ville Syrjälä
2016-05-18 18:46 ` Daniel Vetter
2016-05-18 22:07 ` Runyan, Arthur J
2016-05-19 7:14 ` [PATCH] drm/i915/psr: Implement PSR2 w/a for gen9 Daniel Vetter
2016-05-19 8:55 ` Jindal, Sonika
2016-05-20 7:53 ` Daniel Vetter
2016-05-18 17:17 ` ✗ Ro.CI.BAT: failure for series starting with [1/7] drm/i915: Enable edp psr error interrupts on hsw Patchwork
2016-05-18 18:26 ` [PATCH 1/7] " Ville Syrjälä
2016-05-19 9:36 ` Jindal, Sonika
2016-05-19 8:01 ` ✗ Ro.CI.BAT: warning for series starting with [1/7] drm/i915: Enable edp psr error interrupts on hsw (rev2) Patchwork
2016-05-20 7:48 ` Daniel Vetter
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